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Merge branch 'fix/fix_cache_hit_bypass_iram_safe_assertion' into 'master'

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fix(esp_hw_support): fix cache hit bypass iram safe assertion on p4

See merge request espressif/esp-idf!38371
This commit is contained in:
Wu Zheng Hui
2025-04-22 16:22:37 +08:00
parent 6dc71c2b52 dbec79a508
commit d41cb1346e
1 changed files with 6 additions and 0 deletions
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6
components/esp_hw_support/sleep_modes.c
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@@ -519,6 +519,12 @@ static int s_cache_suspend_cnt = 0;
static void IRAM_ATTR suspend_cache(void) {
s_cache_suspend_cnt++;
if (s_cache_suspend_cnt == 1) {
#if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION && CONFIG_IDF_TARGET_ESP32P4
// The implementation of P4 L2 cache suspend is to shut down MSPI AXI instead of shutting down Cache BUS.
// If the access to external memory hits in the cache, it will not trigger a cache error. So in order to
// fully check the access to external memory, writeback & invalidate is needed here.
Cache_WriteBack_Invalidate_All(CACHE_MAP_MASK);
#endif
spi_flash_disable_cache(esp_cpu_get_core_id(), NULL);
}
}