feat(hal): Add CPU_APM support for ESP32-C61

2025-08-04 21:24:32 +02:00 · 2025-06-21 14:35:03 +05:30
parent 37733a877c
commit d8601f8245
7 changed files with 335 additions and 37 deletions
--- a/components/hal/apm_hal.c
+++ b/components/hal/apm_hal.c
@@ -218,9 +218,82 @@ void apm_hal_enable_region_filter(apm_ctrl_module_t ctrl_mod, uint32_t regn_num,
    }
 }

+void apm_hal_set_region_start_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr)
+{
+    switch (ctrl_mod) {
+        case APM_CTRL_HP_APM:
+            apm_ll_hp_apm_set_region_start_addr(regn_num, addr);
+            break;
+#if SOC_APM_LP_APM0_SUPPORTED
+        case APM_CTRL_LP_APM0:
+            apm_ll_lp_apm0_set_region_start_addr(regn_num, addr);
+            break;
+#endif
+        case APM_CTRL_LP_APM:
+            apm_ll_lp_apm_set_region_start_addr(regn_num, addr);
+            break;
+#if SOC_APM_CPU_APM_SUPPORTED
+        case APM_CTRL_CPU_APM:
+            apm_ll_cpu_apm_set_region_start_addr(regn_num, addr);
+            break;
+#endif
+        default:
+            break;
+    }
+}
+
+void apm_hal_set_region_end_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr)
+{
+    switch (ctrl_mod) {
+        case APM_CTRL_HP_APM:
+            apm_ll_hp_apm_set_region_end_addr(regn_num, addr);
+            break;
+#if SOC_APM_LP_APM0_SUPPORTED
+        case APM_CTRL_LP_APM0:
+            apm_ll_lp_apm0_set_region_end_addr(regn_num, addr);
+            break;
+#endif
+        case APM_CTRL_LP_APM:
+            apm_ll_lp_apm_set_region_end_addr(regn_num, addr);
+            break;
+#if SOC_APM_CPU_APM_SUPPORTED
+        case APM_CTRL_CPU_APM:
+            apm_ll_cpu_apm_set_region_end_addr(regn_num, addr);
+            break;
+#endif
+        default:
+            break;
+    }
+}
+
+void apm_hal_set_sec_mode_region_attr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
+{
+    switch (ctrl_mod) {
+        case APM_CTRL_HP_APM:
+            apm_ll_hp_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+            break;
+#if SOC_APM_LP_APM0_SUPPORTED
+        case APM_CTRL_LP_APM0:
+            apm_ll_lp_apm0_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+            break;
+#endif
+        case APM_CTRL_LP_APM:
+            apm_ll_lp_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+            break;
+#if SOC_APM_CPU_APM_SUPPORTED
+        case APM_CTRL_CPU_APM:
+            apm_ll_cpu_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+            break;
+#endif
+        default:
+            break;
+    }
+}
+
 void apm_hal_set_region_filter_cfg(apm_ctrl_module_t ctrl_mod, apm_security_mode_t mode, const apm_hal_ctrl_region_cfg_t *regn_cfg)
 {
    HAL_ASSERT(regn_cfg);
+    HAL_ASSERT(mode != APM_SEC_MODE_TEE);

    switch (ctrl_mod) {
        case APM_CTRL_HP_APM:
--- a/components/hal/esp32c61/include/hal/apm_ll.h
+++ b/components/hal/esp32c61/include/hal/apm_ll.h
@@ -14,6 +14,8 @@
 #include "soc/hp_apm_struct.h"
 #include "soc/lp_apm_reg.h"
 #include "soc/lp_apm_struct.h"
+#include "soc/cpu_apm_reg.h"
+#include "soc/cpu_apm_struct.h"

 #include "soc/pcr_reg.h"
 #include "soc/interrupts.h"
@@ -448,6 +450,195 @@ static inline int apm_ll_lp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path)
    return ETS_LP_APM_M0_INTR_SOURCE;
 }

+/**
+ * @brief Enable/disable controller filter for specific path in CPU-APM
+ *
+ * @param path Access path
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path));
+    } else {
+        REG_CLR_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path));
+    }
+}
+
+/**
+ * @brief Enable/disable all controller filters in CPU-APM
+ *
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_ctrl_filter_all(bool enable)
+{
+    REG_WRITE(CPU_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0);
+}
+
+/**
+ * @brief Enable/disable region filter in CPU-APM
+ *
+ * @param regn_num Region number
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_region_filter(uint32_t regn_num, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num));
+    } else {
+        REG_CLR_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num));
+    }
+}
+
+/**
+ * @brief Set region start address in CPU-APM
+ *
+ * @param regn_num Region number
+ * @param addr Start address
+ */
+static inline void apm_ll_cpu_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr)
+{
+    REG_WRITE(CPU_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
+}
+
+/**
+ * @brief Set region end address in CPU-APM
+ *
+ * @param regn_num Region number
+ * @param addr End address
+ */
+static inline void apm_ll_cpu_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr)
+{
+    REG_WRITE(CPU_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
+}
+
+/**
+ * @brief Set security mode region attributes in CPU-APM
+ *
+ * @param regn_num Region number
+ * @param mode Security mode
+ * @param regn_pms Region PMS attributes
+ */
+static inline void apm_ll_cpu_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
+{
+    uint32_t reg = CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num;
+    uint32_t val = REG_READ(reg);
+    val &= ~APM_REGION_PMS_MASK(mode);
+    val |= APM_REGION_PMS_FIELD(mode, regn_pms);
+    REG_WRITE(reg, val);
+}
+
+/**
+ * @brief Lock security mode region attributes in CPU-APM
+ *
+ * @param regn_num Region number
+ */
+static inline void apm_ll_cpu_apm_lock_sec_mode_region_attr(uint32_t regn_num)
+{
+    REG_SET_BIT(CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT);
+}
+
+/**
+ * @brief Get exception data (regn, master, security mode) from CPU-APM
+ *
+ * @param path Access path
+ * @return Exception data
+ */
+static inline uint32_t apm_ll_cpu_apm_get_excp_data(apm_ctrl_access_path_t path)
+{
+    return REG_READ(CPU_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path);
+}
+
+/**
+ * @brief Get exception status from CPU-APM
+ *
+ * @param path Access path
+ * @return Exception type
+ */
+static inline uint32_t apm_ll_cpu_apm_get_excp_type(apm_ctrl_access_path_t path)
+{
+    return REG_READ(CPU_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path);
+}
+
+/**
+ * @brief Get exception address from CPU-APM
+ *
+ * @param path Access path
+ * @return Exception address
+ */
+static inline uint32_t apm_ll_cpu_apm_get_excp_addr(apm_ctrl_access_path_t path)
+{
+    return REG_READ(CPU_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path);
+}
+
+/**
+ * @brief Get exception information from CPU-APM
+ *
+ * @param path Access path
+ * @param info Pointer to store exception information
+ */
+static inline void apm_ll_cpu_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info)
+{
+    cpu_apm_m0_exception_info0_reg_t reg;
+    reg.val = apm_ll_cpu_apm_get_excp_data(path);
+    info->regn = reg.apm_m0_exception_region;
+    info->mode = reg.apm_m0_exception_mode;
+    info->id   = reg.apm_m0_exception_id;
+
+    info->type = apm_ll_cpu_apm_get_excp_type(path);
+    info->addr = apm_ll_cpu_apm_get_excp_addr(path);
+}
+
+/**
+ * @brief Clear controller exception status in CPU-APM
+ *
+ * @param path Access path
+ */
+static inline void apm_ll_cpu_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path)
+{
+    REG_SET_BIT(CPU_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT);
+}
+
+/**
+ * @brief Enable/disable controller interrupt in CPU-APM
+ *
+ * @param path Access path
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(CPU_APM_INT_EN_REG, BIT(path));
+    } else {
+        REG_CLR_BIT(CPU_APM_INT_EN_REG, BIT(path));
+    }
+}
+
+/**
+ * @brief Enable/disable controller clock gating in CPU-APM
+ *
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_ctrl_clk_gating(bool enable)
+{
+    if (enable) {
+        REG_CLR_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN);
+    } else {
+        REG_SET_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN);
+    }
+}
+
+/**
+ * @brief Get controller interrupt source number from CPU-APM
+ *
+ * @param path Access path
+ * @return Interrupt source number
+ */
+static inline int apm_ll_cpu_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path)
+{
+    return ETS_CPU_APM_M0_INTR_SOURCE + path;
+}
+
 /**
 * @brief Enable/disable APM reset event bypass
 *
--- a/components/hal/include/hal/apm_hal.h
+++ b/components/hal/include/hal/apm_hal.h
@@ -253,6 +253,33 @@ void apm_hal_enable_ctrl_filter_all(bool enable);
 */
 void apm_hal_enable_region_filter(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, bool enable);

+/**
+ * @brief Set the start address for the given region
+ *
+ * @param ctrl_mod APM controller module
+ * @param regn_num Region number
+ * @param addr Address
+ */
+void apm_hal_set_region_start_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr);
+
+/**
+ * @brief Set the end address for the given region
+ *
+ * @param ctrl_mod APM controller module
+ * @param regn_num Region number
+ * @param addr Address
+ */
+void apm_hal_set_region_end_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr);
+
+/**
+ * @brief Set the permissions for the specified security mode for the given region
+ *
+ * @param ctrl_mod APM controller module
+ * @param regn_num Region number
+ * @param mode Security mode
+ */
+void apm_hal_set_sec_mode_region_attr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms);
+
 /**
 * @brief Set region filter configuration
 *
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -999,6 +999,10 @@ config SOC_APM_CTRL_FILTER_SUPPORTED
    bool
    default y

+config SOC_APM_CPU_APM_SUPPORTED
+    bool
+    default y
+
 config SOC_APM_SUPPORT_CTRL_CFG_LOCK
    bool
    default y
--- a/components/soc/esp32c61/include/soc/apm_defs.h
+++ b/components/soc/esp32c61/include/soc/apm_defs.h
@@ -15,9 +15,11 @@ extern "C" {
 /* Number of paths for each supported APM controller */
 #define APM_CTRL_HP_APM_PATH_NUM    (4)
 #define APM_CTRL_LP_APM_PATH_NUM    (1)
+#define APM_CTRL_CPU_APM_PATH_NUM   (2)
 /* Number of regions for each supported APM controller */
 #define APM_CTRL_HP_APM_REGION_NUM  (16)
 #define APM_CTRL_LP_APM_REGION_NUM  (4)
+#define APM_CTRL_CPU_APM_REGION_NUM (8)

 /* Register offset for TEE mode control */
 #define APM_TEE_MODE_CTRL_OFFSET        (0x04)
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -412,6 +412,7 @@

 /*-------------------------- APM CAPS ----------------------------------------*/
 #define SOC_APM_CTRL_FILTER_SUPPORTED   1 /*!< Support for APM control filter */
+#define SOC_APM_CPU_APM_SUPPORTED       1 /*!< Support for CPU APM control filter */
 #define SOC_APM_SUPPORT_CTRL_CFG_LOCK   1 /*!< Support for APM controller configuration lock */

 /*------------------------ Anti DPA (Security) CAPS --------------------------*/
--- a/components/soc/esp32c61/register/soc/cpu_apm_reg.h
+++ b/components/soc/esp32c61/register/soc/cpu_apm_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** CPU_APM_REGION_FILTER_EN_REG register
 *  Region filter enable register
 */
-#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_BASE + 0x0)
+#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_REG_BASE + 0x0)
 /** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1;
 *  Configure bit $n (0-7) to enable region $n.
 *  0: disable
@@ -28,7 +28,7 @@ extern "C" {
 /** CPU_APM_REGION0_ADDR_START_REG register
 *  Region address register
 */
-#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_BASE + 0x4)
+#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x4)
 /** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
 *  Low 12 bit, start address of region 0.
 */
@@ -54,7 +54,7 @@ extern "C" {
 /** CPU_APM_REGION0_ADDR_END_REG register
 *  Region address register
 */
-#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_BASE + 0x8)
+#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x8)
 /** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
 *  Low 12 bit, end address of region 0.
 */
@@ -80,7 +80,7 @@ extern "C" {
 /** CPU_APM_REGION0_ATTR_REG register
 *  Region access authority attribute register
 */
-#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_BASE + 0xc)
+#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0xc)
 /** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
 *  Configures the execution authority of REE_MODE 0 in region 0.
 */
@@ -155,7 +155,7 @@ extern "C" {
 /** CPU_APM_REGION1_ADDR_START_REG register
 *  Region address register
 */
-#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_BASE + 0x10)
+#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x10)
 /** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
 *  Low 12 bit, start address of region 1.
 */
@@ -181,7 +181,7 @@ extern "C" {
 /** CPU_APM_REGION1_ADDR_END_REG register
 *  Region address register
 */
-#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_BASE + 0x14)
+#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x14)
 /** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
 *  Low 12 bit, end address of region 1.
 */
@@ -207,7 +207,7 @@ extern "C" {
 /** CPU_APM_REGION1_ATTR_REG register
 *  Region access authority attribute register
 */
-#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_BASE + 0x18)
+#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x18)
 /** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
 *  Configures the execution authority of REE_MODE 0 in region 1.
 */
@@ -282,7 +282,7 @@ extern "C" {
 /** CPU_APM_REGION2_ADDR_START_REG register
 *  Region address register
 */
-#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_BASE + 0x1c)
+#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x1c)
 /** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
 *  Low 12 bit, start address of region 2.
 */
@@ -308,7 +308,7 @@ extern "C" {
 /** CPU_APM_REGION2_ADDR_END_REG register
 *  Region address register
 */
-#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_BASE + 0x20)
+#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x20)
 /** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
 *  Low 12 bit, end address of region 2.
 */
@@ -334,7 +334,7 @@ extern "C" {
 /** CPU_APM_REGION2_ATTR_REG register
 *  Region access authority attribute register
 */
-#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_BASE + 0x24)
+#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x24)
 /** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
 *  Configures the execution authority of REE_MODE 0 in region 2.
 */
@@ -409,7 +409,7 @@ extern "C" {
 /** CPU_APM_REGION3_ADDR_START_REG register
 *  Region address register
 */
-#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_BASE + 0x28)
+#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x28)
 /** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
 *  Low 12 bit, start address of region 3.
 */
@@ -435,7 +435,7 @@ extern "C" {
 /** CPU_APM_REGION3_ADDR_END_REG register
 *  Region address register
 */
-#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_BASE + 0x2c)
+#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x2c)
 /** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
 *  Low 12 bit, end address of region 3.
 */
@@ -461,7 +461,7 @@ extern "C" {
 /** CPU_APM_REGION3_ATTR_REG register
 *  Region access authority attribute register
 */
-#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_BASE + 0x30)
+#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x30)
 /** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
 *  Configures the execution authority of REE_MODE 0 in region 3.
 */
@@ -536,7 +536,7 @@ extern "C" {
 /** CPU_APM_REGION4_ADDR_START_REG register
 *  Region address register
 */
-#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_BASE + 0x34)
+#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x34)
 /** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
 *  Low 12 bit, start address of region 4.
 */
@@ -562,7 +562,7 @@ extern "C" {
 /** CPU_APM_REGION4_ADDR_END_REG register
 *  Region address register
 */
-#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_BASE + 0x38)
+#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x38)
 /** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
 *  Low 12 bit, end address of region 4.
 */
@@ -588,7 +588,7 @@ extern "C" {
 /** CPU_APM_REGION4_ATTR_REG register
 *  Region access authority attribute register
 */
-#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_BASE + 0x3c)
+#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x3c)
 /** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
 *  Configures the execution authority of REE_MODE 0 in region 4.
 */
@@ -663,7 +663,7 @@ extern "C" {
 /** CPU_APM_REGION5_ADDR_START_REG register
 *  Region address register
 */
-#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_BASE + 0x40)
+#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x40)
 /** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
 *  Low 12 bit, start address of region 5.
 */
@@ -689,7 +689,7 @@ extern "C" {
 /** CPU_APM_REGION5_ADDR_END_REG register
 *  Region address register
 */
-#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_BASE + 0x44)
+#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x44)
 /** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
 *  Low 12 bit, end address of region 5.
 */
@@ -715,7 +715,7 @@ extern "C" {
 /** CPU_APM_REGION5_ATTR_REG register
 *  Region access authority attribute register
 */
-#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_BASE + 0x48)
+#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x48)
 /** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
 *  Configures the execution authority of REE_MODE 0 in region 5.
 */
@@ -790,7 +790,7 @@ extern "C" {
 /** CPU_APM_REGION6_ADDR_START_REG register
 *  Region address register
 */
-#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_BASE + 0x4c)
+#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x4c)
 /** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
 *  Low 12 bit, start address of region 6.
 */
@@ -816,7 +816,7 @@ extern "C" {
 /** CPU_APM_REGION6_ADDR_END_REG register
 *  Region address register
 */
-#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_BASE + 0x50)
+#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x50)
 /** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
 *  Low 12 bit, end address of region 6.
 */
@@ -842,7 +842,7 @@ extern "C" {
 /** CPU_APM_REGION6_ATTR_REG register
 *  Region access authority attribute register
 */
-#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_BASE + 0x54)
+#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x54)
 /** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
 *  Configures the execution authority of REE_MODE 0 in region 6.
 */
@@ -917,7 +917,7 @@ extern "C" {
 /** CPU_APM_REGION7_ADDR_START_REG register
 *  Region address register
 */
-#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_BASE + 0x58)
+#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x58)
 /** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [11:0]; default: 0;
 *  Low 12 bit, start address of region 7.
 */
@@ -943,7 +943,7 @@ extern "C" {
 /** CPU_APM_REGION7_ADDR_END_REG register
 *  Region address register
 */
-#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_BASE + 0x5c)
+#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x5c)
 /** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095;
 *  Low 12 bit, end address of region 7.
 */
@@ -969,7 +969,7 @@ extern "C" {
 /** CPU_APM_REGION7_ATTR_REG register
 *  Region access authority attribute register
 */
-#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_BASE + 0x60)
+#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x60)
 /** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
 *  Configures the execution authority of REE_MODE 0 in region 7.
 */
@@ -1044,7 +1044,7 @@ extern "C" {
 /** CPU_APM_FUNC_CTRL_REG register
 *  APM function control register
 */
-#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_BASE + 0xc4)
+#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_REG_BASE + 0xc4)
 /** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
 *  PMS M0 function enable
 */
@@ -1063,7 +1063,7 @@ extern "C" {
 /** CPU_APM_M0_STATUS_REG register
 *  M0 status register
 */
-#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_BASE + 0xc8)
+#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_REG_BASE + 0xc8)
 /** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
 *  Represents exception status.
 *  bit0: 1 represents authority_exception
@@ -1077,7 +1077,7 @@ extern "C" {
 /** CPU_APM_M0_STATUS_CLR_REG register
 *  M0 status clear register
 */
-#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xcc)
+#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_REG_BASE + 0xcc)
 /** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
 *  Configures to clear exception status.
 */
@@ -1089,7 +1089,7 @@ extern "C" {
 /** CPU_APM_M0_EXCEPTION_INFO0_REG register
 *  M0 exception_info0 register
 */
-#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xd0)
+#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_REG_BASE + 0xd0)
 /** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
 *  Represents exception region.
 */
@@ -1115,7 +1115,7 @@ extern "C" {
 /** CPU_APM_M0_EXCEPTION_INFO1_REG register
 *  M0 exception_info1 register
 */
-#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xd4)
+#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_REG_BASE + 0xd4)
 /** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
 *  Represents exception addr.
 */
@@ -1127,7 +1127,7 @@ extern "C" {
 /** CPU_APM_M1_STATUS_REG register
 *  M1 status register
 */
-#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_BASE + 0xd8)
+#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_REG_BASE + 0xd8)
 /** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
 *  Represents exception status.
 *  bit0: 1 represents authority_exception
@@ -1141,7 +1141,7 @@ extern "C" {
 /** CPU_APM_M1_STATUS_CLR_REG register
 *  M1 status clear register
 */
-#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xdc)
+#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_REG_BASE + 0xdc)
 /** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
 *  Configures to clear exception status.
 */
@@ -1153,7 +1153,7 @@ extern "C" {
 /** CPU_APM_M1_EXCEPTION_INFO0_REG register
 *  M1 exception_info0 register
 */
-#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xe0)
+#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_REG_BASE + 0xe0)
 /** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
 *  Represents exception region.
 */
@@ -1179,7 +1179,7 @@ extern "C" {
 /** CPU_APM_M1_EXCEPTION_INFO1_REG register
 *  M1 exception_info1 register
 */
-#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xe4)
+#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_REG_BASE + 0xe4)
 /** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
 *  Represents exception addr.
 */
@@ -1191,7 +1191,7 @@ extern "C" {
 /** CPU_APM_INT_EN_REG register
 *  APM interrupt enable register
 */
-#define CPU_APM_INT_EN_REG (DR_REG_CPU_BASE + 0x118)
+#define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_REG_BASE + 0x118)
 /** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
 *  Configures to enable APM M0 interrupt.
 *  0: disable
@@ -1214,7 +1214,7 @@ extern "C" {
 /** CPU_APM_CLOCK_GATE_REG register
 *  Clock gating register
 */
-#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_BASE + 0x7f8)
+#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_REG_BASE + 0x7f8)
 /** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
 *  Configures whether to keep the clock always on.
 *  0: enable automatic clock gating
@@ -1228,7 +1228,7 @@ extern "C" {
 /** CPU_APM_DATE_REG register
 *  Version control register
 */
-#define CPU_APM_DATE_REG (DR_REG_CPU_BASE + 0x7fc)
+#define CPU_APM_DATE_REG (DR_REG_CPU_APM_REG_BASE + 0x7fc)
 /** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 37823248;
 *  Version control register.
 */