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mmu: fix macro MMU_ENTRY_NUM and add new macro MMU_MAX_PADDR_PAGE_NUM

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This commit is contained in:
Armando
2022-04-26 23:18:18 +08:00
parent 2764cd5682
commit e09787d851
13 changed files with 51 additions and 48 deletions
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4
components/hal/esp32/include/hal/mmu_ll.h
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@@ -78,7 +78,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
__attribute__((always_inline)) __attribute__((always_inline))
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{ {
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
DPORT_INTERRUPT_DISABLE(); DPORT_INTERRUPT_DISABLE();
switch (mmu_id) { switch (mmu_id) {
@@ -102,7 +102,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
__attribute__((always_inline)) __attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id) static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{ {
for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { for (int i = 0; i < MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i); mmu_ll_set_entry_invalid(mmu_id, i);
} }
} }

6
components/hal/esp32c2/include/hal/mmu_ll.h
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@@ -142,7 +142,7 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(target == MMU_TARGET_FLASH0); HAL_ASSERT(target == MMU_TARGET_FLASH0);
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
} }
@@ -157,7 +157,7 @@ __attribute__((always_inline))
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
} }
@@ -170,7 +170,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
__attribute__((always_inline)) __attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id) static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{ {
for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { for (int i = 0; i < MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i); mmu_ll_set_entry_invalid(mmu_id, i);
} }
} }

6
components/hal/esp32c3/include/hal/mmu_ll.h
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@@ -109,7 +109,7 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(target == MMU_TARGET_FLASH0); HAL_ASSERT(target == MMU_TARGET_FLASH0);
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
} }
@@ -124,7 +124,7 @@ __attribute__((always_inline))
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
} }
@@ -137,7 +137,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
__attribute__((always_inline)) __attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id) static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{ {
for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { for (int i = 0; i < MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i); mmu_ll_set_entry_invalid(mmu_id, i);
} }
} }

6
components/hal/esp32h2/include/hal/mmu_ll.h
View File

@@ -109,7 +109,7 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(target == MMU_TARGET_FLASH0); HAL_ASSERT(target == MMU_TARGET_FLASH0);
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
} }
@@ -124,7 +124,7 @@ __attribute__((always_inline))
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
} }
@@ -137,7 +137,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
__attribute__((always_inline)) __attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id) static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{ {
for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { for (int i = 0; i < MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i); mmu_ll_set_entry_invalid(mmu_id, i);
} }
} }

6
components/hal/esp32s2/include/hal/mmu_ll.h
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@@ -132,7 +132,7 @@ __attribute__((always_inline))
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM; uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM;
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID;
@@ -148,7 +148,7 @@ __attribute__((always_inline))
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
} }
@@ -161,7 +161,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
__attribute__((always_inline)) __attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id) static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{ {
for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { for (int i = 0; i < MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i); mmu_ll_set_entry_invalid(mmu_id, i);
} }
} }

6
components/hal/esp32s3/include/hal/mmu_ll.h
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@@ -108,7 +108,7 @@ __attribute__((always_inline))
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM; uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM;
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID;
@@ -124,7 +124,7 @@ __attribute__((always_inline))
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{ {
(void)mmu_id; (void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM); HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
} }
@@ -137,7 +137,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
__attribute__((always_inline)) __attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id) static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{ {
for (int i = 0; i < MMU_MAX_ENTRY_NUM; i++) { for (int i = 0; i < MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i); mmu_ll_set_entry_invalid(mmu_id, i);
} }
} }

2
components/hal/mmu_hal.c
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@@ -83,7 +83,7 @@ void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr,
uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1); uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1);
HAL_ASSERT(vaddr % page_size_in_bytes == 0); HAL_ASSERT(vaddr % page_size_in_bytes == 0);
HAL_ASSERT(paddr % page_size_in_bytes == 0); HAL_ASSERT(paddr % page_size_in_bytes == 0);
HAL_ASSERT((paddr + len) <= mmu_hal_pages_to_bytes(mmu_id, MMU_MAX_ENTRY_NUM)); HAL_ASSERT((paddr + len) <= mmu_hal_pages_to_bytes(mmu_id, MMU_MAX_PADDR_PAGE_NUM));
HAL_ASSERT(mmu_ll_check_valid_ext_vaddr_region(mmu_id, vaddr, len)); HAL_ASSERT(mmu_ll_check_valid_ext_vaddr_region(mmu_id, vaddr, len));
uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes; uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes;

8
components/soc/esp32/include/soc/ext_mem_defs.h
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@@ -37,12 +37,8 @@ extern "C" {
#define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr) #define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr)
#define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr) #define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr)
/** //MMU entry num
* Max MMU entry num. #define MMU_ENTRY_NUM 256
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
* 256 * 64KB, means MMU can map 16MB at most
*/
#define MMU_MAX_ENTRY_NUM 256
#ifdef __cplusplus #ifdef __cplusplus
} }

13
components/soc/esp32c2/include/soc/ext_mem_defs.h
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@@ -42,9 +42,6 @@ extern "C" {
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) #define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) #define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
//IDF-3821
// #define MMU_SIZE 0x100
#define CACHE_IBUS 0 #define CACHE_IBUS 0
#define CACHE_IBUS_MMU_START 0 #define CACHE_IBUS_MMU_START 0
#define CACHE_IBUS_MMU_END 0x100 #define CACHE_IBUS_MMU_END 0x100
@@ -95,16 +92,18 @@ extern "C" {
*/ */
#define INVALID_PHY_PAGE 0x7f #define INVALID_PHY_PAGE 0x7f
/** /**
* Max MMU entry num. * Max MMU available paddr page num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 64 * 64KB, means MMU can map 4MB at most * 64 * 64KB, means MMU can support 4MB paddr at most
*/ */
#define MMU_MAX_ENTRY_NUM 64 #define MMU_MAX_PADDR_PAGE_NUM 64
/** /**
* This is the mask used for mapping. e.g.: * This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK * 0x4200_0000 & MMU_VADDR_MASK
*/ */
#define MMU_VADDR_MASK ((0x100000 << (MMU_PAGE_MODE)) - 1) #define MMU_VADDR_MASK ((0x100000 << (MMU_PAGE_MODE)) - 1)
//MMU entry num
#define MMU_ENTRY_NUM 64
#define BUS_PMS_MASK 0xffffff #define BUS_PMS_MASK 0xffffff

11
components/soc/esp32c3/include/soc/ext_mem_defs.h
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@@ -86,17 +86,18 @@ extern "C" {
*/ */
#define INVALID_PHY_PAGE 0xffff #define INVALID_PHY_PAGE 0xffff
/** /**
* Max MMU entry num. * Max MMU available paddr page num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can map 16MB at most * 256 * 64KB, means MMU can support 16MB paddr at most
*/ */
#define MMU_MAX_ENTRY_NUM 256 #define MMU_MAX_PADDR_PAGE_NUM 256
/** /**
* This is the mask used for mapping. e.g.: * This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK * 0x4200_0000 & MMU_VADDR_MASK
*/ */
#define MMU_VADDR_MASK 0x7FFFFF #define MMU_VADDR_MASK 0x7FFFFF
//MMU entry num
#define MMU_ENTRY_NUM 128
#define CACHE_ICACHE_LOW_SHIFT 0 #define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2 #define CACHE_ICACHE_HIGH_SHIFT 2

10
components/soc/esp32h2/include/soc/ext_mem_defs.h
View File

@@ -86,16 +86,18 @@ extern "C" {
*/ */
#define INVALID_PHY_PAGE 0xffff #define INVALID_PHY_PAGE 0xffff
/** /**
* Max MMU entry num. * Max MMU available paddr page num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can map 16MB at most * 256 * 64KB, means MMU can support 16MB paddr at most
*/ */
#define MMU_MAX_ENTRY_NUM 256 #define MMU_MAX_PADDR_PAGE_NUM 256
/** /**
* This is the mask used for mapping. e.g.: * This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK * 0x4200_0000 & MMU_VADDR_MASK
*/ */
#define MMU_VADDR_MASK 0x7fffff #define MMU_VADDR_MASK 0x7fffff
//MMU entry num
#define MMU_ENTRY_NUM 128
#define CACHE_ICACHE_LOW_SHIFT 0 #define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2 #define CACHE_ICACHE_HIGH_SHIFT 2

11
components/soc/esp32s2/include/soc/ext_mem_defs.h
View File

@@ -111,16 +111,19 @@ extern "C" {
*/ */
#define MMU_VALID_VAL_MASK 0x3fff #define MMU_VALID_VAL_MASK 0x3fff
/** /**
* Max MMU entry num. * Max MMU available paddr page num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 16384 * 64KB, means MMU can map 1GB at most * 16384 * 64KB, means MMU can support 1GB paddr at most
*/ */
#define MMU_MAX_ENTRY_NUM 16384 #define MMU_MAX_PADDR_PAGE_NUM 16384
/** /**
* This is the mask used for mapping. e.g.: * This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK * 0x4200_0000 & MMU_VADDR_MASK
*/ */
#define MMU_VADDR_MASK 0x3FFFFF #define MMU_VADDR_MASK 0x3FFFFF
//MMU entry num
#define MMU_ENTRY_NUM 384
#define BUS_NUM_MASK 0x3 #define BUS_NUM_MASK 0x3
#define CACHE_MEMORY_BANK_SIZE 8192 #define CACHE_MEMORY_BANK_SIZE 8192

10
components/soc/esp32s3/include/soc/ext_mem_defs.h
View File

@@ -86,16 +86,18 @@ extern "C" {
*/ */
#define INVALID_PHY_PAGE 0xffff #define INVALID_PHY_PAGE 0xffff
/** /**
* Max MMU entry num. * Max MMU available paddr page num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.: * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 16384 * 64KB, means MMU can map 1GB at most * 16384 * 64KB, means MMU can support 1GB paddr at most
*/ */
#define MMU_MAX_ENTRY_NUM 16384 #define MMU_MAX_PADDR_PAGE_NUM 16384
/** /**
* This is the mask used for mapping. e.g.: * This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK * 0x4200_0000 & MMU_VADDR_MASK
*/ */
#define MMU_VADDR_MASK 0x1FFFFFF #define MMU_VADDR_MASK 0x1FFFFFF
//MMU entry num
#define MMU_ENTRY_NUM 512
#define CACHE_ICACHE_LOW_SHIFT 0 #define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2 #define CACHE_ICACHE_HIGH_SHIFT 2