Merge branch 'feat/soc_config_h' into 'master'

split soc_caps.h and standardize its name/usage Closes IDF-11815 See merge request espressif/esp-idf!35445
2025-08-03 12:44:33 +02:00 · 2025-07-17 21:46:44 +08:00
parent 4e12ed0655 0999aeedbd
commit e1213c8874
126 changed files with 955 additions and 978 deletions
--- a/components/esp_driver_gptimer/src/gptimer.c
+++ b/components/esp_driver_gptimer/src/gptimer.c
@@ -17,9 +17,9 @@ static esp_err_t gptimer_create_sleep_retention_link_cb(void *timer)
 {
    int group_id = ((gptimer_t *)timer)->group->group_id;
    int timer_id = ((gptimer_t *)timer)->timer_id;
-    esp_err_t err = sleep_retention_entries_create(tg_timer_reg_retention_info[group_id][timer_id].regdma_entry_array,
-                                                   tg_timer_reg_retention_info[group_id][timer_id].array_size,
-                                                   REGDMA_LINK_PRI_GPTIMER, tg_timer_reg_retention_info[group_id][timer_id].module);
+    esp_err_t err = sleep_retention_entries_create(soc_timg_gptimer_retention_infos[group_id][timer_id].regdma_entry_array,
+                                                   soc_timg_gptimer_retention_infos[group_id][timer_id].array_size,
+                                                   REGDMA_LINK_PRI_GPTIMER, soc_timg_gptimer_retention_infos[group_id][timer_id].module);
    return err;
 }

@@ -27,7 +27,7 @@ static void gptimer_create_retention_module(gptimer_t *timer)
 {
    int group_id = timer->group->group_id;
    int timer_id = timer->timer_id;
-    sleep_retention_module_t module = tg_timer_reg_retention_info[group_id][timer_id].module;
+    sleep_retention_module_t module = soc_timg_gptimer_retention_infos[group_id][timer_id].module;
    if (sleep_retention_is_module_inited(module) && !sleep_retention_is_module_created(module)) {
        if (sleep_retention_module_allocate(module) != ESP_OK) {
            // even though the sleep retention module create failed, GPTimer driver should still work, so just warning here
@@ -41,12 +41,12 @@ static esp_err_t gptimer_register_to_group(gptimer_t *timer)
 {
    gptimer_group_t *group = NULL;
    int timer_id = -1;
-    for (int i = 0; i < SOC_TIMER_GROUPS; i++) {
+    for (int i = 0; i < SOC_TIMG_ATTR(INST_NUM); i++) {
        group = gptimer_acquire_group_handle(i);
        ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no mem for group (%d)", i);
        // loop to search free timer in the group
        portENTER_CRITICAL(&group->spinlock);
-        for (int j = 0; j < SOC_TIMER_GROUP_TIMERS_PER_GROUP; j++) {
+        for (int j = 0; j < SOC_GPTIMER_ATTR(TIMERS_PER_TIMG); j++) {
            if (!group->timers[j]) {
                timer_id = j;
                group->timers[j] = timer;
@@ -65,7 +65,7 @@ static esp_err_t gptimer_register_to_group(gptimer_t *timer)
    ESP_RETURN_ON_FALSE(timer_id != -1, ESP_ERR_NOT_FOUND, TAG, "no free timer");

 #if GPTIMER_USE_RETENTION_LINK
-    sleep_retention_module_t module = tg_timer_reg_retention_info[group->group_id][timer_id].module;
+    sleep_retention_module_t module = soc_timg_gptimer_retention_infos[group->group_id][timer_id].module;
    sleep_retention_module_init_param_t init_param = {
        .cbs = {
            .create = {
@@ -93,7 +93,7 @@ static void gptimer_unregister_from_group(gptimer_t *timer)
    portEXIT_CRITICAL(&group->spinlock);

 #if GPTIMER_USE_RETENTION_LINK
-    sleep_retention_module_t module = tg_timer_reg_retention_info[group->group_id][timer_id].module;
+    sleep_retention_module_t module = soc_timg_gptimer_retention_infos[group->group_id][timer_id].module;
    if (sleep_retention_is_module_created(module)) {
        sleep_retention_module_free(module);
    }
@@ -209,11 +209,11 @@ esp_err_t gptimer_del_timer(gptimer_handle_t timer)
    ESP_RETURN_ON_ERROR(gptimer_destroy(timer), TAG, "destroy gptimer failed");

    switch (clk_src) {
-#if SOC_TIMER_GROUP_SUPPORT_RC_FAST
+#if TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST
    case GPTIMER_CLK_SRC_RC_FAST:
        periph_rtc_dig_clk8m_disable();
        break;
-#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST
+#endif // TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST
    default:
        break;
    }
@@ -288,7 +288,7 @@ esp_err_t gptimer_register_event_callbacks(gptimer_handle_t timer, const gptimer
        if (timer->intr_priority) {
            isr_flags |= 1 << (timer->intr_priority);
        }
-        ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(timer_group_periph_signals.groups[group_id].timer_irq_id[timer_id], isr_flags,
+        ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(soc_timg_gptimer_signals[group_id][timer_id].irq_id, isr_flags,
                                                      (uint32_t)timer_ll_get_intr_status_reg(timer->hal.dev), TIMER_LL_EVENT_ALARM(timer_id),
                                                      gptimer_default_isr, timer, &timer->intr), TAG, "install interrupt service failed");
    }
--- a/components/esp_driver_gptimer/src/gptimer_common.c
+++ b/components/esp_driver_gptimer/src/gptimer_common.c
@@ -12,8 +12,8 @@

 typedef struct gptimer_platform_t {
    _lock_t mutex;                             // platform level mutex lock
-    gptimer_group_t *groups[SOC_TIMER_GROUPS]; // timer group pool
-    int group_ref_counts[SOC_TIMER_GROUPS];    // reference count used to protect group install/uninstall
+    gptimer_group_t *groups[SOC_TIMG_ATTR(INST_NUM)]; // timer group pool
+    int group_ref_counts[SOC_TIMG_ATTR(INST_NUM)];    // reference count used to protect group install/uninstall
 } gptimer_platform_t;

 // gptimer driver platform, it's always a singleton
@@ -48,7 +48,7 @@ gptimer_group_t *gptimer_acquire_group_handle(int group_id)
        // !!! HARDWARE SHARED RESOURCE !!!
        // the gptimer and watchdog reside in the same the timer group
        // we need to increase/decrease the reference count before enable/disable/reset the peripheral
-        PERIPH_RCC_ACQUIRE_ATOMIC(timer_group_periph_signals.groups[group_id].module, ref_count) {
+        PERIPH_RCC_ACQUIRE_ATOMIC(soc_timg_gptimer_signals[group_id][0].parent_module, ref_count) {
            if (ref_count == 0) {
                timer_ll_enable_bus_clock(group_id, true);
                timer_ll_reset_register(group_id);
@@ -76,7 +76,7 @@ void gptimer_release_group_handle(gptimer_group_t *group)

    if (do_deinitialize) {
        // disable bus clock for the timer group
-        PERIPH_RCC_RELEASE_ATOMIC(timer_group_periph_signals.groups[group_id].module, ref_count) {
+        PERIPH_RCC_RELEASE_ATOMIC(soc_timg_gptimer_signals[group_id][0].parent_module, ref_count) {
            if (ref_count == 0) {
                timer_ll_enable_bus_clock(group_id, false);
            }
@@ -92,13 +92,13 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
    int timer_id = timer->timer_id;
    int group_id = timer->group->group_id;
    // TODO: [clk_tree] to use a generic clock enable/disable or acquire/release function for all clock source
-#if SOC_TIMER_GROUP_SUPPORT_RC_FAST
+#if TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST
    if (src_clk == GPTIMER_CLK_SRC_RC_FAST) {
        // RC_FAST clock is not enabled automatically on start up, we enable it here manually.
        // Note there's a ref count in the enable/disable function, we must call them in pair in the driver.
        periph_rtc_dig_clk8m_enable();
    }
-#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST
+#endif // TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST
    timer->clk_src = src_clk;

    // get clock source frequency
@@ -111,19 +111,19 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
    // driver will create different pm lock for that purpose, according to different clock source
    esp_pm_lock_type_t pm_lock_type = ESP_PM_NO_LIGHT_SLEEP;

-#if SOC_TIMER_GROUP_SUPPORT_RC_FAST
+#if TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST
    if (src_clk == GPTIMER_CLK_SRC_RC_FAST) {
        // RC_FAST won't be turn off in sleep and won't change its frequency during DFS
        need_pm_lock = false;
    }
-#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST
+#endif // TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST

-#if SOC_TIMER_GROUP_SUPPORT_APB
+#if TIMER_LL_FUNC_CLOCK_SUPPORT_APB
    if (src_clk == GPTIMER_CLK_SRC_APB) {
        // APB clock frequency can be changed during DFS
        pm_lock_type = ESP_PM_APB_FREQ_MAX;
    }
-#endif // SOC_TIMER_GROUP_SUPPORT_APB
+#endif // TIMER_LL_FUNC_CLOCK_SUPPORT_APB

 #if CONFIG_IDF_TARGET_ESP32C2
    if (src_clk == GPTIMER_CLK_SRC_PLL_F40M) {
@@ -135,7 +135,7 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
 #endif // CONFIG_IDF_TARGET_ESP32C2

    if (need_pm_lock) {
-        ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock_type, 0, timer_group_periph_signals.groups[group_id].module_name[timer_id], &timer->pm_lock),
+        ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock_type, 0, soc_timg_gptimer_signals[group_id][timer_id].module_name, &timer->pm_lock),
                            TAG, "create pm lock failed");
    }
 #endif // CONFIG_PM_ENABLE
--- a/components/esp_driver_gptimer/src/gptimer_priv.h
+++ b/components/esp_driver_gptimer/src/gptimer_priv.h
@@ -14,7 +14,7 @@
 // Set the maximum log level for gptimer driver
 #define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE
 #endif
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_err.h"
 #include "esp_log.h"
@@ -69,7 +69,7 @@ typedef struct gptimer_t gptimer_t;
 typedef struct gptimer_group_t {
    int group_id;
    portMUX_TYPE spinlock; // to protect per-group register level concurrent access
-    gptimer_t *timers[SOC_TIMER_GROUP_TIMERS_PER_GROUP];
+    gptimer_t *timers[SOC_GPTIMER_ATTR(TIMERS_PER_TIMG)];
 } gptimer_group_t;

 typedef enum {
--- a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer.c
+++ b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer.c
@@ -10,7 +10,7 @@
 #include "freertos/task.h"
 #include "unity.h"
 #include "driver/gptimer.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
 #include "esp_attr.h"

 #if CONFIG_GPTIMER_ISR_CACHE_SAFE
@@ -26,33 +26,33 @@ TEST_CASE("gptimer_set_get_raw_count", "[gptimer]")
        .direction = GPTIMER_COUNT_UP,
        .resolution_hz = 1 * 1000 * 1000,
    };
-    gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    gptimer_handle_t timers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_new_timer(&config, &timers[i]));
    }

    TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gptimer_new_timer(&config, &timers[0]));
    unsigned long long get_value = 0;
    printf("check gptimer initial count value\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_get_raw_count(timers[i], &get_value));
        TEST_ASSERT_EQUAL(0, get_value);
    }
    unsigned long long set_values[] = {100, 500, 666};
    for (size_t j = 0; j < sizeof(set_values) / sizeof(set_values[0]); j++) {
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            printf("set raw count to %llu for gptimer %d\r\n", set_values[j], i);
            TEST_ESP_OK(gptimer_set_raw_count(timers[i], set_values[j]));
        }
        vTaskDelay(pdMS_TO_TICKS(10));
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_get_raw_count(timers[i], &get_value));
            printf("get raw count of gptimer %d: %llu\r\n", i, get_value);
            TEST_ASSERT_EQUAL(set_values[j], get_value);
        }
    }

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_del_timer(timers[i]));
    }
 }
@@ -60,7 +60,7 @@ TEST_CASE("gptimer_set_get_raw_count", "[gptimer]")
 TEST_CASE("gptimer_wallclock_with_various_clock_sources", "[gptimer]")
 {
    gptimer_clock_source_t test_clk_srcs[] = SOC_GPTIMER_CLKS;
-    uint32_t timer_resolution_hz[SOC_TIMER_GROUP_TOTAL_TIMERS];
+    uint32_t timer_resolution_hz[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];

    // test with various clock sources
    for (size_t i = 0; i < sizeof(test_clk_srcs) / sizeof(test_clk_srcs[0]); i++) {
@@ -69,36 +69,36 @@ TEST_CASE("gptimer_wallclock_with_various_clock_sources", "[gptimer]")
            .direction = GPTIMER_COUNT_UP,
            .resolution_hz = 1 * 1000 * 1000,
        };
-        gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        gptimer_handle_t timers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_new_timer(&timer_config, &timers[i]));
            TEST_ESP_OK(gptimer_get_resolution(timers[i], &timer_resolution_hz[i]));
        }
        // start timer before enable should fail
        TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gptimer_start(timers[0]));
        printf("enable timers\r\n");
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_enable(timers[i]));
        }
        printf("start timers\r\n");
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_start(timers[i]));
        }
        esp_rom_delay_us(20 * 1000); // 20ms = 20_000 ticks
        uint64_t value = 0;
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_get_raw_count(timers[i], &value));
            // convert the raw count to us
            value = value * 1000000 / timer_resolution_hz[i];
            TEST_ASSERT_UINT_WITHIN(200, 20000, value);
        }
        printf("stop timers\r\n");
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_stop(timers[i]));
        }
        printf("check whether timers have stopped\r\n");
        esp_rom_delay_us(20 * 1000);
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_get_raw_count(timers[i], &value));
            printf("get raw count of gptimer %d: %llu\r\n", i, value);
            // convert the raw count to us
@@ -106,17 +106,17 @@ TEST_CASE("gptimer_wallclock_with_various_clock_sources", "[gptimer]")
            TEST_ASSERT_UINT_WITHIN(400, 20000, value);     //200 more threshold for cpu on stop process
        }
        printf("restart timers\r\n");
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_start(timers[i]));
        }
        esp_rom_delay_us(20 * 1000);
        printf("stop timers again\r\n");
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_stop(timers[i]));
        }
        printf("check whether timers have stopped\r\n");
        esp_rom_delay_us(20 * 1000);
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_get_raw_count(timers[i], &value));
            printf("get raw count of gptimer %d: %llu\r\n", i, value);
            // convert the raw count to us
@@ -124,11 +124,11 @@ TEST_CASE("gptimer_wallclock_with_various_clock_sources", "[gptimer]")
            TEST_ASSERT_UINT_WITHIN(600, 40000, value);     //same 200 for cpu time
        }
        printf("disable timers\r\n");
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_disable(timers[i]));
        }
        printf("delete timers\r\n");
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ESP_OK(gptimer_del_timer(timers[i]));
        }
    }
@@ -163,8 +163,8 @@ TEST_CASE("gptimer_stop_on_alarm", "[gptimer]")
        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
        .direction = GPTIMER_COUNT_UP,
    };
-    gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    gptimer_handle_t timers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_new_timer(&timer_config, &timers[i]));
    }

@@ -174,7 +174,7 @@ TEST_CASE("gptimer_stop_on_alarm", "[gptimer]")
    gptimer_alarm_config_t alarm_config = {};

    printf("start timers\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        alarm_config.alarm_count = 100000 * (i + 1);
        TEST_ESP_OK(gptimer_set_alarm_action(timers[i], &alarm_config));
        TEST_ESP_OK(gptimer_register_event_callbacks(timers[i], &cbs, task_handle));
@@ -182,38 +182,38 @@ TEST_CASE("gptimer_stop_on_alarm", "[gptimer]")
        TEST_ESP_OK(gptimer_start(timers[i]));
        printf("alarm value for gptimer %d: %llu\r\n", i, alarm_config.alarm_count);
    }
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000)));
    }

    printf("check whether the timers have stopped in the ISR\r\n");
    vTaskDelay(pdMS_TO_TICKS(20));
    unsigned long long value = 0;
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_get_raw_count(timers[i], &value));
        printf("get raw count of gptimer %d: %llu\r\n", i, value);
        TEST_ASSERT_UINT_WITHIN(GPTIMER_STOP_ON_ALARM_COUNT_DELTA, 100000 * (i + 1), value);
    }

    printf("restart timers\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        alarm_config.alarm_count = 100000 * (i + 1);
        // reset counter value to zero
        TEST_ESP_OK(gptimer_set_raw_count(timers[i], 0));
        TEST_ESP_OK(gptimer_start(timers[i]));
    }
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000)));
    }
    printf("check whether the timers have stopped in the ISR\r\n");
    vTaskDelay(pdMS_TO_TICKS(20));
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_get_raw_count(timers[i], &value));
        printf("get raw count of gptimer %d: %llu\r\n", i, value);
        TEST_ASSERT_UINT_WITHIN(GPTIMER_STOP_ON_ALARM_COUNT_DELTA, 100000 * (i + 1), value);
    }

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_disable(timers[i]));
        TEST_ESP_OK(gptimer_del_timer(timers[i]));
    }
@@ -249,8 +249,8 @@ TEST_CASE("gptimer_auto_reload_on_alarm", "[gptimer]")
        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
        .direction = GPTIMER_COUNT_UP,
    };
-    gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    gptimer_handle_t timers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_new_timer(&timer_config, &timers[i]));
    }

@@ -264,7 +264,7 @@ TEST_CASE("gptimer_auto_reload_on_alarm", "[gptimer]")
    };

    printf("start timers\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_set_alarm_action(timers[i], &alarm_config));
        TEST_ESP_OK(gptimer_register_event_callbacks(timers[i], &cbs, task_handle));
        TEST_ESP_OK(gptimer_enable(timers[i]));
@@ -277,7 +277,7 @@ TEST_CASE("gptimer_auto_reload_on_alarm", "[gptimer]")
        TEST_ESP_OK(gptimer_stop(timers[i]));
    }

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_disable(timers[i]));
        TEST_ESP_OK(gptimer_del_timer(timers[i]));
    }
@@ -313,8 +313,8 @@ TEST_CASE("gptimer_one_shot_alarm", "[gptimer]")
        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
        .direction = GPTIMER_COUNT_UP,
    };
-    gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    gptimer_handle_t timers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        timer_config.intr_priority = i % 3 + 1; // test different priorities
        TEST_ESP_OK(gptimer_new_timer(&timer_config, &timers[i]));
    }
@@ -328,7 +328,7 @@ TEST_CASE("gptimer_one_shot_alarm", "[gptimer]")
    };

    printf("start timers\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_set_alarm_action(timers[i], &alarm_config));
        TEST_ESP_OK(gptimer_register_event_callbacks(timers[i], &cbs, task_handle));
        TEST_ESP_OK(gptimer_enable(timers[i]));
@@ -344,14 +344,14 @@ TEST_CASE("gptimer_one_shot_alarm", "[gptimer]")
    }

    printf("restart timers\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_start(timers[i]));
        // alarm should be triggered immediately as the counter value has across the target alarm value already
        TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, 0));
        TEST_ESP_OK(gptimer_stop(timers[i]));
    }

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_disable(timers[i]));
        TEST_ESP_OK(gptimer_del_timer(timers[i]));
    }
@@ -379,8 +379,8 @@ TEST_CASE("gptimer_update_alarm_dynamically", "[gptimer]")
        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
        .direction = GPTIMER_COUNT_UP,
    };
-    gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    gptimer_handle_t timers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_new_timer(&timer_config, &timers[i]));
    }

@@ -391,7 +391,7 @@ TEST_CASE("gptimer_update_alarm_dynamically", "[gptimer]")
        .alarm_count = 100000, // initial alarm count, 100ms
    };
    printf("start timers\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_set_alarm_action(timers[i], &alarm_config));
        TEST_ESP_OK(gptimer_register_event_callbacks(timers[i], &cbs, task_handle));
        TEST_ESP_OK(gptimer_enable(timers[i]));
@@ -406,7 +406,7 @@ TEST_CASE("gptimer_update_alarm_dynamically", "[gptimer]")
    }

    printf("restart timers\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_start(timers[i]));
        // check the alarm event for multiple times
        TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(500)));
@@ -417,7 +417,7 @@ TEST_CASE("gptimer_update_alarm_dynamically", "[gptimer]")
        TEST_ASSERT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(500)));
    }

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_disable(timers[i]));
        TEST_ESP_OK(gptimer_del_timer(timers[i]));
    }
@@ -453,8 +453,8 @@ TEST_CASE("gptimer_count_down_reload", "[gptimer]")
        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
        .direction = GPTIMER_COUNT_DOWN,
    };
-    gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    gptimer_handle_t timers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_new_timer(&timer_config, &timers[i]));
        TEST_ESP_OK(gptimer_set_raw_count(timers[i], 200000));
    }
@@ -468,7 +468,7 @@ TEST_CASE("gptimer_count_down_reload", "[gptimer]")
        .flags.auto_reload_on_alarm = true,
    };

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_set_alarm_action(timers[i], &alarm_config));
        TEST_ESP_OK(gptimer_register_event_callbacks(timers[i], &cbs, task_handle));
        TEST_ESP_OK(gptimer_enable(timers[i]));
@@ -480,7 +480,7 @@ TEST_CASE("gptimer_count_down_reload", "[gptimer]")
    }

    printf("restart gptimer with previous configuration\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_start(timers[i]));
        // check twice, as it's a period event
        TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000)));
@@ -488,7 +488,7 @@ TEST_CASE("gptimer_count_down_reload", "[gptimer]")
        TEST_ESP_OK(gptimer_stop(timers[i]));
    }

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_disable(timers[i]));
        TEST_ESP_OK(gptimer_del_timer(timers[i]));
    }
@@ -513,14 +513,14 @@ TEST_CASE("gptimer_overflow", "[gptimer]")
        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
        .direction = GPTIMER_COUNT_UP,
    };
-    gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    gptimer_handle_t timers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_new_timer(&timer_config, &timers[i]));
    }
-#if SOC_TIMER_GROUP_COUNTER_BIT_WIDTH == 64
+#if SOC_MODULE_ATTR(GPTIMER, COUNTER_BIT_WIDTH) == 64
    uint64_t reload_at = UINT64_MAX - 100000;
 #else
-    uint64_t reload_at = (1ULL << SOC_TIMER_GROUP_COUNTER_BIT_WIDTH) - 100000;
+    uint64_t reload_at = (1ULL << SOC_MODULE_ATTR(GPTIMER, COUNTER_BIT_WIDTH)) - 100000;
 #endif
    gptimer_event_callbacks_t cbs = {
        .on_alarm = test_gptimer_overflow_reload_callback,
@@ -533,7 +533,7 @@ TEST_CASE("gptimer_overflow", "[gptimer]")
    // The counter should start from [COUNTER_MAX-100000] and overflows to [0] and continue, then reached to alarm value [100000], reloaded to [COUNTER_MAX-100000] automatically
    // thus the period should be 200ms
    printf("start timers\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_set_alarm_action(timers[i], &alarm_config));
        TEST_ESP_OK(gptimer_register_event_callbacks(timers[i], &cbs, task_handle));
        // we start from the reload value
@@ -544,7 +544,7 @@ TEST_CASE("gptimer_overflow", "[gptimer]")
        TEST_ESP_OK(gptimer_stop(timers[i]));
    }

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_disable(timers[i]));
        TEST_ESP_OK(gptimer_del_timer(timers[i]));
    }
--- a/components/esp_gdbstub/src/gdbstub.c
+++ b/components/esp_gdbstub/src/gdbstub.c
@@ -120,10 +120,10 @@ static wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
 static bool rtc_wdt_ctx_enabled = false;
 static wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
 static bool wdt0_context_enabled = false;
-#if SOC_TIMER_GROUPS >= 2
+#if SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2
 static wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
 static bool wdt1_context_enabled = false;
-#endif // SOC_TIMER_GROUPS
+#endif // SOC_MODULE_ATTR(TIMG, INST_NUM)

 /**
 * Disable all enabled WDTs
@@ -131,7 +131,7 @@ static bool wdt1_context_enabled = false;
 static inline void disable_all_wdts(void)
 {
    wdt0_context_enabled = wdt_hal_is_enabled(&wdt0_context);
-    #if SOC_TIMER_GROUPS >= 2
+    #if SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2
    wdt1_context_enabled = wdt_hal_is_enabled(&wdt1_context);
    #endif
    rtc_wdt_ctx_enabled = wdt_hal_is_enabled(&rtc_wdt_ctx);
@@ -144,7 +144,7 @@ static inline void disable_all_wdts(void)
        wdt_hal_write_protect_enable(&wdt0_context);
    }

-    #if SOC_TIMER_GROUPS >= 2
+    #if SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2
    /* Interrupt WDT is the Main Watchdog Timer of Timer Group 1 */
    if (true == wdt1_context_enabled) {
        wdt_hal_write_protect_disable(&wdt1_context);
@@ -152,7 +152,7 @@ static inline void disable_all_wdts(void)
        wdt_hal_feed(&wdt1_context);
        wdt_hal_write_protect_enable(&wdt1_context);
    }
-    #endif // SOC_TIMER_GROUPS >= 2
+    #endif // SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2

    if (true == rtc_wdt_ctx_enabled) {
        wdt_hal_write_protect_disable(&rtc_wdt_ctx);
@@ -173,14 +173,14 @@ static inline void enable_all_wdts(void)
        wdt_hal_enable(&wdt0_context);
        wdt_hal_write_protect_enable(&wdt0_context);
    }
-    #if SOC_TIMER_GROUPS >= 2
+    #if SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2
    /* Interrupt WDT is the Main Watchdog Timer of Timer Group 1 */
    if (false == wdt1_context_enabled) {
        wdt_hal_write_protect_disable(&wdt1_context);
        wdt_hal_enable(&wdt1_context);
        wdt_hal_write_protect_enable(&wdt1_context);
    }
-    #endif // SOC_TIMER_GROUPS >= 2
+    #endif // SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2

    if (false == rtc_wdt_ctx_enabled) {
        wdt_hal_write_protect_disable(&rtc_wdt_ctx);
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -576,7 +576,7 @@ static SLEEP_FN_ATTR void suspend_timers(uint32_t sleep_flags) {
    if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) {
 #if SOC_SLEEP_TGWDT_STOP_WORKAROUND
        /* If timegroup implemented task watchdog or interrupt watchdog is running, we have to stop it. */
-        for (uint32_t tg_num = 0; tg_num < SOC_TIMER_GROUPS; ++tg_num) {
+        for (uint32_t tg_num = 0; tg_num < SOC_MODULE_ATTR(TIMG, INST_NUM); ++tg_num) {
            if (mwdt_ll_check_if_enabled(TIMER_LL_GET_HW(tg_num))) {
                mwdt_ll_write_protect_disable(TIMER_LL_GET_HW(tg_num));
                mwdt_ll_disable(TIMER_LL_GET_HW(tg_num));
@@ -602,7 +602,7 @@ static SLEEP_FN_ATTR void resume_timers(uint32_t sleep_flags) {
        }
 #endif
 #if SOC_SLEEP_TGWDT_STOP_WORKAROUND
-        for (uint32_t tg_num = 0; tg_num < SOC_TIMER_GROUPS; ++tg_num) {
+        for (uint32_t tg_num = 0; tg_num < SOC_MODULE_ATTR(TIMG, INST_NUM); ++tg_num) {
            if (s_stopped_tgwdt_bmap & BIT(tg_num)) {
                mwdt_ll_write_protect_disable(TIMER_LL_GET_HW(tg_num));
                mwdt_ll_enable(TIMER_LL_GET_HW(tg_num));
--- a/components/esp_hw_support/sleep_system_peripheral.c
+++ b/components/esp_hw_support/sleep_system_peripheral.c
@@ -8,9 +8,10 @@
 #include <string.h>

 #include "sdkconfig.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
 #include "soc/system_periph_retention.h"
 #include "soc/uart_periph.h"
+#include "soc/timer_periph.h"

 #include "esp_sleep.h"
 #include "esp_log.h"
@@ -188,7 +189,7 @@ bool peripheral_domain_pd_allowed(void)
 #if SOC_TIMER_SUPPORT_SLEEP_RETENTION
    mask.bitmap[SLEEP_RETENTION_MODULE_TG0_TIMER0 >> 5] |= BIT(SLEEP_RETENTION_MODULE_TG0_TIMER0 % 32);
    mask.bitmap[SLEEP_RETENTION_MODULE_TG1_TIMER0 >> 5] |= BIT(SLEEP_RETENTION_MODULE_TG1_TIMER0 % 32);
-#if (SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1)
+#if SOC_GPTIMER_ATTR(TIMERS_PER_TIMG) > 1
    mask.bitmap[SLEEP_RETENTION_MODULE_TG0_TIMER1 >> 5] |= BIT(SLEEP_RETENTION_MODULE_TG0_TIMER1 % 32);
    mask.bitmap[SLEEP_RETENTION_MODULE_TG1_TIMER1 >> 5] |= BIT(SLEEP_RETENTION_MODULE_TG1_TIMER1 % 32);
 #endif
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
@@ -18,7 +18,7 @@
 #include "unity.h"
 #include "esp_intr_alloc.h"
 #include "driver/gptimer.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
 #include "soc/system_intr.h"
 #if SOC_GPSPI_SUPPORTED
 #include "soc/spi_periph.h"
@@ -28,7 +28,7 @@
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/gptimer.h"

-#if SOC_GPTIMER_SUPPORTED
+#if SOC_HAS(GPTIMER)
 static bool on_timer_alarm(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_ctx)
 {
    volatile int *count = (volatile int *)user_ctx;
@@ -38,9 +38,9 @@ static bool on_timer_alarm(gptimer_handle_t timer, const gptimer_alarm_event_dat

 static void timer_test(int flags)
 {
-    static int count[SOC_TIMER_GROUP_TOTAL_TIMERS] = {0};
-    gptimer_handle_t gptimers[SOC_TIMER_GROUP_TOTAL_TIMERS];
-    intr_handle_t inth[SOC_TIMER_GROUP_TOTAL_TIMERS];
+    static int count[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)] = {0};
+    gptimer_handle_t gptimers[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];
+    intr_handle_t inth[SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)];

    gptimer_config_t config = {
        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
@@ -48,7 +48,7 @@ static void timer_test(int flags)
        .resolution_hz = 1000000,
        .flags.intr_shared = (flags & ESP_INTR_FLAG_SHARED) == ESP_INTR_FLAG_SHARED,
    };
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_new_timer(&config, &gptimers[i]));
    }
    gptimer_alarm_config_t alarm_config = {
@@ -60,7 +60,7 @@ static void timer_test(int flags)
        .on_alarm = on_timer_alarm,
    };

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_register_event_callbacks(gptimers[i], &cbs, &count[i]));
        alarm_config.alarm_count += 10000 * i;
        TEST_ESP_OK(gptimer_set_alarm_action(gptimers[i], &alarm_config));
@@ -73,39 +73,39 @@ static void timer_test(int flags)
    if ((flags & ESP_INTR_FLAG_SHARED)) {
        /* Check that the allocated interrupts are actually shared */
        int intr_num = esp_intr_get_intno(inth[0]);
-        for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+        for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
            TEST_ASSERT_EQUAL(intr_num, esp_intr_get_intno(inth[i]));
        }
    }

    vTaskDelay(1000 / portTICK_PERIOD_MS);
    printf("Timer values after 1 sec:");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        printf(" %d", count[i]);
    }
    printf("\r\n");

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ASSERT_NOT_EQUAL(0, count[i]);
    }

    printf("Disabling timers' interrupt...\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        esp_intr_disable(inth[i]);
        count[i] = 0;
    }

    vTaskDelay(1000 / portTICK_PERIOD_MS);
    printf("Timer values after 1 sec:");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        printf(" %d", count[i]);
    }
    printf("\r\n");
-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ASSERT_EQUAL(0, count[i]);
    }

-    for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) {
+    for (int i = 0; i < SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL); i++) {
        TEST_ESP_OK(gptimer_stop(gptimers[i]));
        TEST_ESP_OK(gptimer_disable(gptimers[i]));
        TEST_ESP_OK(gptimer_del_timer(gptimers[i]));
@@ -121,7 +121,7 @@ TEST_CASE("Intr_alloc test, shared ints", "[intr_alloc]")
 {
    timer_test(ESP_INTR_FLAG_SHARED);
 }
-#endif //SOC_GPTIMER_SUPPORTED
+#endif // SOC_HAS(GPTIMER)

 void static test_isr(void*arg)
 {
--- a/components/esp_rom/esp32/include/esp32/rom/sha.h
+++ b/components/esp_rom/esp32/include/esp32/rom/sha.h
@@ -27,15 +27,14 @@ typedef struct SHAContext {
    uint32_t total_input_bits[4];
 } SHA_CTX;

-enum SHA_TYPE {
+typedef enum SHA_TYPE {
    SHA1 = 0,
    SHA2_256,
    SHA2_384,
    SHA2_512,

-
    SHA_INVALID = -1,
-};
+} SHA_TYPE;

 /* Do not use these function in multi core mode due to
 * inside they have no safe implementation (without DPORT workaround).
--- a/components/esp_rom/patches/esp_rom_wdt.c
+++ b/components/esp_rom/patches/esp_rom_wdt.c
@@ -23,7 +23,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
    if (wdt_inst == WDT_MWDT0) {
        hal->mwdt_dev = &TIMERG0;
    }
-#if SOC_TIMER_GROUPS >= 2
+#if SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2
    else if (wdt_inst == WDT_MWDT1) {
        hal->mwdt_dev = &TIMERG1;
    }
--- a/components/esp_system/int_wdt.c
+++ b/components/esp_system/int_wdt.c
@@ -29,7 +29,7 @@
 #include "esp_private/sleep_retention.h"
 #endif

-#if SOC_TIMER_GROUPS > 1
+#if SOC_MODULE_ATTR(TIMG, INST_NUM) > 1

 /* If we have two hardware timer groups, use the second one for interrupt watchdog. */
 #define WDT_LEVEL_INTR_SOURCE   SYS_TG1_WDT_INTR_SOURCE
@@ -50,7 +50,7 @@
 #define IWDT_PERIPH             PERIPH_TIMG0_MODULE
 #define IWDT_TIMER_GROUP        0

-#endif // SOC_TIMER_GROUPS > 1
+#endif // SOC_MODULE_ATTR(TIMG, INST_NUM) > 1

 #if CONFIG_ESP_INT_WDT
 #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_MWDT_SUPPORT_SLEEP_RETENTION
--- a/components/esp_system/panic.c
+++ b/components/esp_system/panic.c
@@ -192,12 +192,12 @@ void esp_panic_handler_disable_timg_wdts(void)
    wdt_hal_disable(&wdt0_context);
    wdt_hal_write_protect_enable(&wdt0_context);

-#if SOC_TIMER_GROUPS >= 2
+#if SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2
    wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
    wdt_hal_write_protect_disable(&wdt1_context);
    wdt_hal_disable(&wdt1_context);
    wdt_hal_write_protect_enable(&wdt1_context);
-#endif /* SOC_TIMER_GROUPS >= 2 */
+#endif /* SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2 */
 }

 /* This function enables the RTC WDT with the given timeout in milliseconds */
@@ -232,7 +232,7 @@ void esp_panic_handler_feed_wdts(void)
        wdt_hal_write_protect_enable(&wdt0_context);
    }

-#if SOC_TIMER_GROUPS >= 2
+#if SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2
    // Feed Timer Group 1 WDT
    wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
    if (wdt_hal_is_enabled(&wdt1_context)) {
@@ -240,7 +240,7 @@ void esp_panic_handler_feed_wdts(void)
        wdt_hal_feed(&wdt1_context);
        wdt_hal_write_protect_enable(&wdt1_context);
    }
-#endif /* SOC_TIMER_GROUPS >= 2 */
+#endif /* SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2 */

    // Feed RTC WDT
    if (wdt_hal_is_enabled(&rtc_wdt_ctx)) {
--- a/components/hal/adc_hal.c
+++ b/components/hal/adc_hal.c
@@ -5,13 +5,12 @@
 */

 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "hal/adc_hal.h"
 #include "hal/assert.h"
 #include "soc/lldesc.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"

-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
 //ADC utilises I2S0 DMA on ESP32
 #include "hal/i2s_hal.h"
 #include "hal/i2s_types.h"
@@ -58,7 +57,7 @@ void adc_hal_digi_init(adc_hal_dma_ctx_t *hal)
    adc_ll_digi_set_clk_div(ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT);

    adc_ll_digi_dma_set_eof_num(hal->eof_num);
-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
    i2s_ll_rx_set_sample_bit(adc_hal_i2s_dev, SAMPLE_BITS, SAMPLE_BITS);
    i2s_ll_rx_enable_mono_mode(adc_hal_i2s_dev, 1);
    i2s_ll_rx_force_enable_fifo_mod(adc_hal_i2s_dev, 1);
@@ -91,20 +90,20 @@ void adc_hal_digi_deinit()
 ---------------------------------------------------------------*/
 static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t convert_mode)
 {
-#if CONFIG_IDF_TARGET_ESP32 || SOC_ADC_DIGI_CONTROLLER_NUM == 1
+#if SOC_IS(ESP32) || SOC_ADC_DIGI_CONTROLLER_NUM == 1
    return ADC_LL_DIGI_CONV_ONLY_ADC1;
 #elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2)
    switch (convert_mode) {
-        case ADC_CONV_SINGLE_UNIT_1:
-            return ADC_LL_DIGI_CONV_ONLY_ADC1;
-        case ADC_CONV_SINGLE_UNIT_2:
-            return ADC_LL_DIGI_CONV_ONLY_ADC2;
-        case ADC_CONV_BOTH_UNIT:
-            return ADC_LL_DIGI_CONV_BOTH_UNIT;
-        case ADC_CONV_ALTER_UNIT:
-            return ADC_LL_DIGI_CONV_ALTER_UNIT;
-        default:
-            abort();
+    case ADC_CONV_SINGLE_UNIT_1:
+        return ADC_LL_DIGI_CONV_ONLY_ADC1;
+    case ADC_CONV_SINGLE_UNIT_2:
+        return ADC_LL_DIGI_CONV_ONLY_ADC2;
+    case ADC_CONV_BOTH_UNIT:
+        return ADC_LL_DIGI_CONV_BOTH_UNIT;
+    case ADC_CONV_ALTER_UNIT:
+        return ADC_LL_DIGI_CONV_ALTER_UNIT;
+    default:
+        abort();
    }
 #endif
 }
@@ -118,7 +117,7 @@ static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t conve
 */
 static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuous_clk_src_t clk_src, uint32_t clk_src_freq_hz, uint32_t sample_freq_hz)
 {
-#if !CONFIG_IDF_TARGET_ESP32
+#if !SOC_IS(ESP32)
    uint32_t interval = clk_src_freq_hz / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / sample_freq_hz;
    //set sample interval
    adc_ll_digi_set_trigger_interval(interval);
@@ -218,14 +217,14 @@ void adc_hal_digi_dma_link(adc_hal_dma_ctx_t *hal, uint8_t *data_buf)
                .dw0.suc_eof = 0,
                .dw0.owner = 1,
                .buffer = data_buf,
-                .next = &desc[n+1]
+                .next = &desc[n + 1]
            };
            eof_size -= this_len;
            data_buf += this_len;
            n++;
        }
    }
-    desc[n-1].next = desc_head;
+    desc[n - 1].next = desc_head;
 }

 adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len)
--- a/components/hal/apm_hal.c
+++ b/components/hal/apm_hal.c
@@ -5,12 +5,13 @@
 */

 #include <stdbool.h>
+#include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/apm_hal.h"
 #include "hal/apm_ll.h"
 #include "hal/log.h"

-#if CONFIG_IDF_TARGET_ESP32P4
+#if SOC_IS(ESP32P4)
 void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri,
                                     apm_ll_secure_mode_t sec_mode, bool enable)
 {
@@ -523,4 +524,4 @@ void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable)
    }
 }

-#endif //CONFIG_IDF_TARGET_ESP32P4
+#endif //SOC_IS(ESP32P4)
--- a/components/hal/emac_hal.c
+++ b/components/hal/emac_hal.c
@@ -4,7 +4,7 @@
 * SPDX-License-Identifier: Apache-2.0
 */
 #include <string.h>
-#include "sdkconfig.h"
+#include "soc/soc_caps_full.h"
 #include "esp_attr.h"
 #include "hal/emac_hal.h"
 #include "hal/emac_ll.h"
@@ -29,7 +29,7 @@ void emac_hal_init(emac_hal_context_t *hal)
 {
    hal->dma_regs = &EMAC_DMA;
    hal->mac_regs = &EMAC_MAC;
-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
    hal->ext_regs = &EMAC_EXT;
 #else
    hal->ext_regs = NULL;
@@ -137,7 +137,7 @@ void emac_hal_init_dma_default(emac_hal_context_t *hal, emac_hal_dma_config_t *h
    /* DMAOMR Configuration */
    /* Enable Dropping of TCP/IP Checksum Error Frames */
    emac_ll_drop_tcp_err_frame_enable(hal->dma_regs, true);
-#if CONFIG_IDF_TARGET_ESP32P4
+#if SOC_IS(ESP32P4)
    /* Disable Receive Store Forward (Rx FIFO is only 256B) */
    emac_ll_recv_store_forward_enable(hal->dma_regs, false);
 #else
--- a/components/hal/esp32/efuse_hal.c
+++ b/components/hal/esp32/efuse_hal.c
@@ -1,15 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "sdkconfig.h"
 #include <sys/param.h>
-#include "soc/soc_caps.h"
 #include "hal/efuse_ll.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
+#include "hal/config.h"
 #include "soc/syscon_reg.h"
 #include "esp_attr.h"

@@ -30,11 +29,11 @@ IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
    case 3:
        chip_ver = 2;
        break;
-#if CONFIG_IDF_ENV_FPGA
+#if HAL_CONFIG_EFUSE_ENV_FPGA
    case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */
        chip_ver = 3;
        break;
-#endif // CONFIG_IDF_ENV_FPGA
+#endif // HAL_CONFIG_EFUSE_ENV_FPGA
    case 7:
        chip_ver = 3;
        break;
--- a/components/hal/esp32/include/hal/timer_ll.h
+++ b/components/hal/esp32/include/hal/timer_ll.h
@@ -23,8 +23,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support APB as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_APB 1
+
 /**
 * @brief Enable the bus clock for timer group module
 *
--- a/components/hal/esp32c2/clk_tree_hal.c
+++ b/components/hal/esp32c2/clk_tree_hal.c
@@ -4,9 +4,9 @@
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "sdkconfig.h"
 #include "soc/clkout_channel.h"
 #include "hal/assert.h"
+#include "hal/config.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/gpio_ll.h"
@@ -78,8 +78,8 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
 {
    uint32_t freq = clk_ll_xtal_load_freq_mhz();
    if (freq == 0) {
-        HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_XTAL_FREQ);
-        return CONFIG_XTAL_FREQ;
+        HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", HAL_CONFIG_XTAL_HINT_FREQ_MHZ);
+        return HAL_CONFIG_XTAL_HINT_FREQ_MHZ;
    }
    return freq;
 }
--- a/components/hal/esp32c3/include/hal/timer_ll.h
+++ b/components/hal/esp32c3/include/hal/timer_ll.h
@@ -22,8 +22,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support APB as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_APB 1
+
 /**
 * @brief Enable the bus clock for timer group module
 *
--- a/components/hal/esp32c5/efuse_hal.c
+++ b/components/hal/esp32c5/efuse_hal.c
@@ -5,7 +5,6 @@
 */

 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
--- a/components/hal/esp32c5/include/hal/timer_ll.h
+++ b/components/hal/esp32c5/include/hal/timer_ll.h
@@ -23,8 +23,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support RC_FAST as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST 1
+
 #define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                                     \
    (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{                                          \
                            [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER0, \
--- a/components/hal/esp32c6/efuse_hal.c
+++ b/components/hal/esp32c6/efuse_hal.c
@@ -5,7 +5,6 @@
 */

 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
--- a/components/hal/esp32c6/include/hal/timer_ll.h
+++ b/components/hal/esp32c6/include/hal/timer_ll.h
@@ -23,8 +23,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support RC_FAST as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST 1
+
 #define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                                        \
    (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{                                             \
                            [GPTIMER_ETM_TASK_START_COUNT] = TIMER0_TASK_CNT_START_TIMER0, \
--- a/components/hal/esp32c61/efuse_hal.c
+++ b/components/hal/esp32c61/efuse_hal.c
@@ -5,7 +5,6 @@
 */

 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
--- a/components/hal/esp32c61/include/hal/timer_ll.h
+++ b/components/hal/esp32c61/include/hal/timer_ll.h
@@ -23,8 +23,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support RC_FAST as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST 1
+
 #define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                                        \
    (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{                                             \
                            [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER0, \
--- a/components/hal/esp32h2/efuse_hal.c
+++ b/components/hal/esp32h2/efuse_hal.c
@@ -5,7 +5,6 @@
 */

 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "soc/chip_revision.h"
 #include "hal/assert.h"
--- a/components/hal/esp32h21/efuse_hal.c
+++ b/components/hal/esp32h21/efuse_hal.c
@@ -5,7 +5,6 @@
 */

 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
--- a/components/hal/esp32h21/include/hal/timer_ll.h
+++ b/components/hal/esp32h21/include/hal/timer_ll.h
@@ -23,8 +23,12 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
-#define TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id) ((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER: SLEEP_RETENTION_MODULE_TG1_TIMER)
+
+// Support RC_FAST as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST 1

 #define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                                        \
    (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{                                             \
--- a/components/hal/esp32h4/efuse_hal.c
+++ b/components/hal/esp32h4/efuse_hal.c
@@ -5,7 +5,6 @@
 */

 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
--- a/components/hal/esp32h4/include/hal/timer_ll.h
+++ b/components/hal/esp32h4/include/hal/timer_ll.h
@@ -23,8 +23,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support RC_FAST as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST 1
+
 #define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                                     \
    (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{                                          \
                            [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER0, \
--- a/components/hal/esp32p4/efuse_hal.c
+++ b/components/hal/esp32p4/efuse_hal.c
@@ -4,7 +4,6 @@
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "sdkconfig.h"
 #include "esp_attr.h"
 #include <sys/param.h>
 #include "soc/soc_caps.h"
--- a/components/hal/esp32p4/include/hal/timer_ll.h
+++ b/components/hal/esp32p4/include/hal/timer_ll.h
@@ -23,8 +23,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support RC_FAST as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST 1
+
 #define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                         \
    (uint32_t[2][2][GPTIMER_ETM_TASK_MAX]){                                 \
        {                                                                   \
--- a/components/hal/esp32s2/efuse_hal.c
+++ b/components/hal/esp32s2/efuse_hal.c
@@ -4,7 +4,6 @@
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "sdkconfig.h"
 #include <sys/param.h>
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
--- a/components/hal/esp32s2/include/hal/timer_ll.h
+++ b/components/hal/esp32s2/include/hal/timer_ll.h
@@ -22,8 +22,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support APB as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_APB 1
+
 /**
 * @brief Enable the bus clock for timer group module
 *
--- a/components/hal/esp32s3/efuse_hal.c
+++ b/components/hal/esp32s3/efuse_hal.c
@@ -4,7 +4,6 @@
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "sdkconfig.h"
 #include <sys/param.h>
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
--- a/components/hal/esp32s3/include/hal/timer_ll.h
+++ b/components/hal/esp32s3/include/hal/timer_ll.h
@@ -22,8 +22,13 @@ extern "C" {

 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+
+// Get alarm interrupt mask with the given timer ID
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))

+// Support APB as function clock
+#define TIMER_LL_FUNC_CLOCK_SUPPORT_APB 1
+
 /**
 * @brief Enable the bus clock for timer group module
 *
--- a/components/hal/include/hal/adc_hal.h
+++ b/components/hal/include/hal/adc_hal.h
@@ -19,12 +19,12 @@
 #include "hal/gdma_ll.h"
 #endif

-#if CONFIG_IDF_TARGET_ESP32S2
+#if SOC_IS(ESP32S2)
 //ADC utilises SPI3 DMA on ESP32S2
 #include "hal/spi_ll.h"
 #endif

-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
 //ADC utilises I2S0 DMA on ESP32
 #include "hal/i2s_ll.h"
 #endif
@@ -33,7 +33,7 @@
 extern "C" {
 #endif

-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
 #define ADC_HAL_DMA_I2S_HOST    0
 #endif

--- a/components/hal/include/hal/adc_types.h
+++ b/components/hal/include/hal/adc_types.h
@@ -7,7 +7,6 @@

 #include <stdbool.h>
 #include <stdint.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "soc/clk_tree_defs.h"
 #include "esp_attr.h"
@@ -159,7 +158,7 @@ typedef enum {
 /*---------------------------------------------------------------
                    Output Format
 ---------------------------------------------------------------*/
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#if SOC_IS(ESP32) || SOC_IS(ESP32S2)
 /**
 * @brief ADC digital controller (DMA mode) output data format.
 *        Used to analyze the acquired ADC (DMA) data.
@@ -184,7 +183,7 @@ typedef struct {
    };
 } adc_digi_output_data_t;

-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
+#elif SOC_IS(ESP32C3) || SOC_IS(ESP32C2)
 /**
 * @brief ADC digital controller (DMA mode) output data format.
 *        Used to analyze the acquired ADC (DMA) data.
@@ -204,7 +203,7 @@ typedef struct {
    };
 } adc_digi_output_data_t;

-#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4
+#elif SOC_IS(ESP32S3) || SOC_IS(ESP32P4)
 /**
 * @brief ADC digital controller (DMA mode) output data format.
 *        Used to analyze the acquired ADC (DMA) data.
@@ -224,7 +223,7 @@ typedef struct {
    };
 } adc_digi_output_data_t;

-#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+#elif SOC_IS(ESP32C6) || SOC_IS(ESP32H2) || SOC_IS(ESP32C5) || SOC_IS(ESP32C61)
 /**
 * @brief ADC digital controller (DMA mode) output data format.
 *        Used to analyze the acquired ADC (DMA) data.
--- a/components/hal/include/hal/apm_hal.h
+++ b/components/hal/include/hal/apm_hal.h
@@ -16,7 +16,7 @@ extern "C" {
 #include "hal/apm_ll.h"
 #include "hal/apm_types.h"

-#if CONFIG_IDF_TARGET_ESP32P4
+#if SOC_IS(ESP32P4)

 /**
 * @brief DMA configurable region configuration data.
@@ -360,11 +360,11 @@ void apm_hal_enable_reset_event_bypass(bool enable);
 */
 void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable);

-#endif //CONFIG_IDF_TARGET_ESP32P4
+#endif //SOC_IS(ESP32P4)

 #elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOC_APM_SUPPORTED

-#if CONFIG_IDF_TARGET_ESP32H4
+#if SOC_IS(ESP32H4)
 #include "soc/hp_apm_reg.h"
 #define apm_hal_enable_ctrl_filter_all(en) \
    REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0);
--- a/components/hal/include/hal/emac_hal.h
+++ b/components/hal/include/hal/emac_hal.h
@@ -12,6 +12,7 @@
 #include "esp_err.h"
 #include "hal/eth_types.h"
 #include "soc/soc_caps.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -25,7 +26,7 @@ extern "C" {
 #define TYPE_SIZE_ERR_MSG(DATATYPE, SIZE)  #DATATYPE " should occupy " STR(SIZE) " bytes in memory"
 #define ASSERT_TYPE_SIZE(DATATYPE, SIZE) ESP_STATIC_ASSERT(sizeof(DATATYPE) == SIZE, TYPE_SIZE_ERR_MSG(DATATYPE, SIZE))

-#if CONFIG_IDF_TARGET_ESP32P4
+#if SOC_IS(ESP32P4)
 // Descriptor must be 64B aligned for ESP32P4 due to cache arrangement
 #define EMAC_HAL_DMA_DESC_SIZE                              (64)
 #else
@@ -191,7 +192,7 @@ ASSERT_TYPE_SIZE(eth_dma_rx_descriptor_t, EMAC_HAL_DMA_DESC_SIZE);

 typedef struct emac_mac_dev_s *emac_mac_soc_regs_t;
 typedef struct emac_dma_dev_s *emac_dma_soc_regs_t;
-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
 typedef struct emac_ext_dev_s *emac_ext_soc_regs_t;
 #else
 typedef void *emac_ext_soc_regs_t;
@@ -236,9 +237,9 @@ void emac_hal_init(emac_hal_context_t *hal);

 #define emac_hal_clock_enable_rmii_input(hal) emac_ll_clock_enable_rmii_input((hal)->ext_regs)

-#ifdef CONFIG_IDF_TARGET_ESP32P4
+#if SOC_IS(ESP32P4)
 #define emac_hal_clock_rmii_rx_tx_div(hal, div) emac_ll_clock_rmii_rx_tx_div((hal)->ext_regs, div)
-#endif // CONFIG_IDF_TARGET_ESP32P4
+#endif // SOC_IS(ESP32P4)

 #define emac_hal_clock_enable_rmii_output(hal) emac_ll_clock_enable_rmii_output((hal)->ext_regs)

--- a/components/hal/include/hal/modem_clock_hal.h
+++ b/components/hal/include/hal/modem_clock_hal.h
@@ -9,7 +9,7 @@
 #pragma once

 #include "soc/soc_caps.h"
-#include "sdkconfig.h"
+
 #if SOC_MODEM_CLOCK_IS_INDEPENDENT && SOC_MODEM_CLOCK_SUPPORTED
 #include "hal/modem_syscon_ll.h"
 #include "hal/modem_lpcon_ll.h"
@@ -24,7 +24,7 @@ typedef struct {
    modem_lpcon_dev_t  *lpcon_dev;
 } modem_clock_hal_context_t;

-#if !CONFIG_IDF_TARGET_ESP32H2 //TODO: PM-92
+#if !SOC_IS(ESP32H2) //TODO: PM-92
 void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap);
 uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain);
 #endif
--- a/components/hal/include/hal/mpi_hal.h
+++ b/components/hal/include/hal/mpi_hal.h
@@ -16,8 +16,7 @@
 #include <stdint.h>
 #include <sys/param.h>
 #include "hal/mpi_types.h"
-#include "sdkconfig.h"
-
+#include "soc/soc_caps.h"

 #ifdef __cplusplus
 extern "C" {
@@ -32,7 +31,7 @@ extern "C" {
 size_t mpi_hal_calc_hardware_words(size_t words);

 /**
- * @brief Clear the MPI power control bit and intitialise the MPI hardware.
+ * @brief Clear the MPI power control bit and initialise the MPI hardware.
 *
 */
 void mpi_hal_enable_hardware_hw_op(void);
@@ -91,13 +90,13 @@ void mpi_hal_write_at_offset(mpi_param_t param, int offset, uint32_t value);
 void mpi_hal_write_m_prime(uint32_t Mprime);

 /**
- * @brief Write first word of the parametr Rinv.
+ * @brief Write first word of the parameter Rinv.
 *
 * @param rinv Value of first word of rinv.
 */
 void mpi_hal_write_rinv(uint32_t rinv);

-#if !CONFIG_IDF_TARGET_ESP32
+#if !SOC_IS(ESP32)
 /**
 * @brief Enable/Disable constant time acceleration option.
 *
@@ -118,7 +117,7 @@ void mpi_hal_enable_search(bool enable);
 * @param position Address to start search.
 */
 void mpi_hal_set_search_position(size_t position);
-#endif /* !CONFIG_IDF_TARGET_ESP32 */
+#endif /* !SOC_IS(ESP32) */

 /**
 * @brief Begin an MPI operation.
--- a/components/hal/include/hal/pmu_types.h
+++ b/components/hal/include/hal/pmu_types.h
@@ -8,7 +8,6 @@

 #include <stdint.h>
 #include "soc/soc_caps.h"
-#include "sdkconfig.h"

 #ifdef __cplusplus
 extern "C" {
@@ -36,7 +35,7 @@ typedef enum {
 /**
 * @brief PMU power domain of HP system
 */
-#if CONFIG_IDF_TARGET_ESP32P4
+#if SOC_IS(ESP32P4)
 typedef enum {
    PMU_HP_PD_TOP = 0,      /*!< Power domain of digital top */
    PMU_HP_PD_CNNT = 1,     /*!< Power domain of high-speed IO peripherals such as USB/SDIO/Ethernet etc.*/
--- a/components/hal/include/hal/rtc_hal.h
+++ b/components/hal/include/hal/rtc_hal.h
@@ -9,9 +9,8 @@
 #include <stdint.h>
 #include "soc/soc_caps.h"
 #include "hal/gpio_types.h"
-#include "sdkconfig.h"

-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
 #include "hal/rtc_cntl_ll.h"
 #endif

--- a/components/hal/include/hal/sha_types.h
+++ b/components/hal/include/hal/sha_types.h
@@ -6,21 +6,13 @@

 #pragma once

-#include "sdkconfig.h"
-
-/* Use enum from rom for backwards compatibility */
 #include "rom/sha.h"

 #ifdef __cplusplus
 extern "C" {
 #endif

-/* Use enum from rom for backwards compatibility */
-#if CONFIG_IDF_TARGET_ESP32
-typedef enum SHA_TYPE esp_sha_type;
-#else
 typedef SHA_TYPE esp_sha_type;
-#endif

 #ifdef __cplusplus
 }
--- a/components/hal/include/hal/touch_sensor_legacy_types.h
+++ b/components/hal/include/hal/touch_sensor_legacy_types.h
@@ -8,7 +8,6 @@

 #include <stdbool.h>
 #include <stdint.h>
-#include "sdkconfig.h"
 #include "esp_attr.h"
 #include "esp_bit_defs.h"
 #include "soc/soc_caps.h"
@@ -128,7 +127,7 @@ typedef enum {
 #define TOUCH_PAD_THRESHOLD_MAX             (0xFFFF)    /*!< If set touch threshold max value, The touch sensor can't be in touched status */
 #endif

-#ifdef CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)

 #define TOUCH_PAD_SLEEP_CYCLE_DEFAULT   (0x1000)  /*!<The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options), max value is 0xffff */
 #define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (0x7fff)  /*!<The timer frequency is 8Mhz, the max value is 0x7fff */
@@ -136,9 +135,9 @@ typedef enum {
 #define TOUCH_TRIGGER_MODE_DEFAULT      (TOUCH_TRIGGER_BELOW)   /*!<Interrupts can be triggered if sensor value gets below or above threshold */
 #define TOUCH_TRIGGER_SOURCE_DEFAULT    (TOUCH_TRIGGER_SOURCE_SET1)  /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */

-#endif // CONFIG_IDF_TARGET ESP32
+#endif // SOC_IS(ESP32)

-#if !CONFIG_IDF_TARGET_ESP32
+#if !SOC_IS(ESP32)
 /**
 * Excessive total time will slow down the touch response.
 * Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
@@ -301,7 +300,7 @@ typedef struct {
    bool en_proximity;              /*!<enable proximity function for sleep pad */
 } touch_pad_sleep_channel_t;

-#endif // !CONFIG_IDF_TARGET_ESP32
+#endif // !SOC_IS(ESP32)

 #ifdef __cplusplus
 }
--- a/components/hal/include/hal/twai_hal.h
+++ b/components/hal/include/hal/twai_hal.h
@@ -13,7 +13,6 @@

 #include <stddef.h>
 #include <stdbool.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/twai_types.h"

--- a/components/hal/mpi_hal.c
+++ b/components/hal/mpi_hal.c
@@ -5,8 +5,7 @@
 */
 #include "hal/mpi_hal.h"
 #include "hal/mpi_ll.h"
-#include "sdkconfig.h"
-
+#include "soc/soc_caps_full.h"

 size_t mpi_hal_calc_hardware_words(size_t words)
 {
@@ -19,7 +18,7 @@ void mpi_hal_enable_hardware_hw_op(void)
    }
    // Note: from enabling RSA clock to here takes about 1.3us

-#if !CONFIG_IDF_TARGET_ESP32
+#if !SOC_IS(ESP32)
    mpi_ll_disable_interrupt();
 #endif
 }
@@ -70,7 +69,7 @@ void mpi_hal_write_rinv(uint32_t rinv)
 }

 // Acceleration options
-#if !CONFIG_IDF_TARGET_ESP32
+#if !SOC_IS(ESP32)
 void mpi_hal_enable_constant_time(bool enable)
 {
    if (enable){
@@ -95,7 +94,7 @@ void mpi_hal_set_search_position(size_t position)
 {
    mpi_ll_set_search_position(position);
 }
-#endif /* !CONFIG_IDF_TARGET_ESP32 */
+#endif // !SOC_IS(ESP32)

 /* Begin an RSA operation.
 */
--- a/components/hal/platform_port/include/hal/config.h
+++ b/components/hal/platform_port/include/hal/config.h
@@ -11,8 +11,28 @@
 extern "C" {
 #endif

+/**
+ * @brief Enable this to reuse ROM APIs for GPIO operations.
+ *        It will save some code size.
+ */
 #define HAL_CONFIG_GPIO_USE_ROM_API CONFIG_HAL_GPIO_USE_ROM_IMPL

+/**
+ * @brief Enable this to indicate the target is an FPGA.
+ */
+#define HAL_CONFIG_EFUSE_ENV_FPGA   CONFIG_IDF_ENV_FPGA
+
+/**
+ * @brief When the hardware fails in measuring the XTAL frequency, use this value as a hint.
+ */
+#define HAL_CONFIG_XTAL_HINT_FREQ_MHZ CONFIG_XTAL_FREQ
+
+/**
+ * @brief Enable this to use ROM APIs for SPI Flash operations.
+ *        It will save some code size.
+ */
+#define HAL_CONFIG_SPI_FLASH_USE_ROM_API CONFIG_SPI_FLASH_ROM_IMPL
+
 #ifdef __cplusplus
 }
 #endif
--- a/components/hal/sha_hal.c
+++ b/components/hal/sha_hal.c
@@ -6,19 +6,19 @@

 // The HAL layer for SHA

+#include <stdlib.h>
+#include <stdio.h>
 #include "hal/sha_hal.h"
 #include "hal/sha_types.h"
 #include "hal/sha_ll.h"
-#include "soc/soc_caps.h"
-#include <stdlib.h>
-#include <stdio.h>
+#include "soc/soc_caps_full.h"


 #define SHA1_STATE_LEN_WORDS    (160 / 32)
 #define SHA256_STATE_LEN_WORDS  (256 / 32)
 #define SHA512_STATE_LEN_WORDS  (512 / 32)

-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)

 /* Return state size (in words) for a given SHA type */
 inline static size_t state_length(esp_sha_type type)
--- a/components/hal/spi_flash_encrypt_hal_iram.c
+++ b/components/hal/spi_flash_encrypt_hal_iram.c
@@ -12,12 +12,12 @@
 void spi_flash_encryption_hal_enable(void)
 {
    spi_flash_encrypt_ll_enable();
-#if CONFIG_IDF_TARGET_ESP32S2
+#if SOC_IS(ESP32S2)
    spi_flash_encrypt_ll_aes_accelerator_enable();
-#endif //CONFIG_IDF_TARGET_ESP32S2
-#if !CONFIG_IDF_TARGET_ESP32
+#endif //SOC_IS(ESP32S2)
+#if !SOC_IS(ESP32)
    spi_flash_encrypt_ll_type(FLASH_ENCRYPTION_MANU);
-#endif // !CONFIG_IDF_TARGET_ESP32
+#endif // !SOC_IS(ESP32)
 }

 void spi_flash_encryption_hal_disable(void)
@@ -27,9 +27,9 @@ void spi_flash_encryption_hal_disable(void)

 void spi_flash_encryption_hal_prepare(uint32_t address, const uint32_t* buffer, uint32_t size)
 {
-#if !CONFIG_IDF_TARGET_ESP32
+#if !SOC_IS(ESP32)
    spi_flash_encrypt_ll_buffer_length(size);
-#endif // !CONFIG_IDF_TARGET_ESP32
+#endif // !SOC_IS(ESP32)
    spi_flash_encrypt_ll_address_save(address);
    spi_flash_encrypt_ll_plaintext_save(address, buffer, size);
    spi_flash_encrypt_ll_calculate_start();
--- a/components/hal/spi_flash_hal.c
+++ b/components/hal/spi_flash_hal.c
@@ -35,7 +35,7 @@ static uint32_t get_flash_clock_divider(const spi_flash_hal_config_t *cfg)
        HAL_LOGE(TAG, "Target frequency %dMHz higher than src %dMHz.", cfg_freq_mhz, src_freq_mhz);
        abort();
    }
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
+#if SOC_IS(ESP32) || SOC_IS(ESP32S2) || SOC_IS(ESP32C3)
    if (cfg_freq_mhz == 26 || cfg_freq_mhz == 27) {
        best_div = 3;
    } else
--- a/components/hal/spi_flash_hal_iram.c
+++ b/components/hal/spi_flash_hal_iram.c
@@ -3,9 +3,9 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 */
-#include "sdkconfig.h"
-
+#include "hal/config.h"
 #include "hal/spi_flash_hal.h"
+#include "soc/soc_caps.h"

 #if SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
 void spi_flash_hal_setup_auto_suspend_mode(spi_flash_host_inst_t *host);
@@ -15,7 +15,7 @@ void spi_flash_hal_setup_auto_resume_mode(spi_flash_host_inst_t *host);
 #define SPI_FLASH_TSHSL2_SAFE_VAL_NS (30)
 #endif //SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND

-#ifndef CONFIG_SPI_FLASH_ROM_IMPL
+#if !HAL_CONFIG_SPI_FLASH_USE_ROM_API

 #include "spi_flash_hal_common.inc"

@@ -88,7 +88,7 @@ esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_inst_t *host, bool wp)
    return ESP_OK;
 }

-#else // defined CONFIG_SPI_FLASH_ROM_IMPL
+#else

 static inline spi_dev_t *get_spi_dev(spi_flash_host_inst_t *host)
 {
@@ -101,7 +101,7 @@ static inline int get_host_id(spi_flash_host_inst_t* host)
    return spi_flash_ll_hw_get_id(dev);
 }

-#endif // !CONFIG_SPI_FLASH_ROM_IMPL
+#endif // !HAL_CONFIG_SPI_FLASH_USE_ROM_API

 uint32_t spi_flash_hal_check_status(spi_flash_host_inst_t *host)
 {
@@ -115,7 +115,7 @@ uint32_t spi_flash_hal_check_status(spi_flash_host_inst_t *host)
    // Not clear if this is necessary, or only necessary if
    // chip->spi == SPI1. But probably doesn't hurt...
    if ((void*) dev == spi_flash_ll_get_hw(SPI1_HOST)) {
-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
        status &= spi_flash_ll_host_idle(&SPI0);
 #endif
    }
--- a/components/hal/usb_dwc_hal.c
+++ b/components/hal/usb_dwc_hal.c
@@ -8,7 +8,7 @@
 #include <stdint.h>
 #include <string.h> // For memset()
 #include <stdlib.h> // For abort()
-#include "sdkconfig.h"
+#include "soc/soc_caps_full.h"
 #include "soc/chip_revision.h"
 #include "soc/usb_periph.h"
 #include "hal/usb_dwc_hal.h"
@@ -87,7 +87,7 @@ static void set_defaults(usb_dwc_hal_context_t *hal)
    //GAHBCFG register
    usb_dwc_ll_gahbcfg_en_dma_mode(hal->dev);
    int hbstlen = 0;    //Use AHB burst SINGLE by default
-#if CONFIG_IDF_TARGET_ESP32S2 && CONFIG_ESP32S2_REV_MIN_FULL < 100
+#if SOC_IS(ESP32S2)
    /*
    Hardware errata workaround for the ESP32-S2 ECO0 (see ESP32-S2 Errata Document section 4.0 for full details).

@@ -105,7 +105,7 @@ static void set_defaults(usb_dwc_hal_context_t *hal)
    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
        hbstlen = 1;    //Set AHB burst to INCR to workaround hardware errata
    }
-#endif //CONFIG_IDF_TARGET_ESP32S2 && CONFIG_ESP32S2_REV_MIN_FULL < 100
+#endif // SOC_IS(ESP32S2)
    usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, hbstlen);  //Set AHB burst mode
    //GUSBCFG register
    usb_dwc_ll_gusbcfg_dis_hnp_cap(hal->dev);       //Disable HNP
--- a/components/hal/wdt_hal_iram.c
+++ b/components/hal/wdt_hal_iram.c
@@ -8,6 +8,7 @@
 #include <stdbool.h>
 #include "hal/wdt_types.h"
 #include "hal/wdt_hal.h"
+#include "soc/soc_caps_full.h"

 /* ---------------------------- Init and Config ----------------------------- */

@@ -18,7 +19,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
    if (wdt_inst == WDT_MWDT0) {
        hal->mwdt_dev = &TIMERG0;
    }
-#if SOC_TIMER_GROUPS >= 2
+#if SOC_MODULE_ATTR(TIMG, INST_NUM) >= 2
    else if (wdt_inst == WDT_MWDT1) {
        hal->mwdt_dev = &TIMERG1;
    }
@@ -37,7 +38,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
        rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE1);
        rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE2);
        rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE3);
-#ifdef CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
        //Enable or disable level interrupt. Edge interrupt is always disabled.
        rwdt_ll_set_edge_intr(hal->rwdt_dev, false);
        rwdt_ll_set_level_intr(hal->rwdt_dev, enable_intr);
@@ -67,7 +68,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
        mwdt_ll_disable_stage(hal->mwdt_dev, 1);
        mwdt_ll_disable_stage(hal->mwdt_dev, 2);
        mwdt_ll_disable_stage(hal->mwdt_dev, 3);
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if SOC_IS(ESP32) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
        //Enable or disable level interrupt. Edge interrupt is always disabled.
        mwdt_ll_set_edge_intr(hal->mwdt_dev, false);
        mwdt_ll_set_level_intr(hal->mwdt_dev, enable_intr);
--- a/components/soc/README.md
+++ b/components/soc/README.md
@@ -1,14 +1,22 @@
-## `soc` ##
+# The SoC component

-The `soc` component provides hardware description for targets supported by ESP-IDF.
+The `soc` component provides register-level descriptions for targets supported by ESP-IDF.

-    - `xxx_reg.h`   - defines registers related to the hardware
-    - `xxx_struct.h` - hardware description in C `struct`
-    - `xxx_channel.h` - definitions for hardware with multiple channels
-    - `xxx_caps.h`  - features/capabilities of the hardware
-    - `xxx_pins.h`  - pin definitions
-    - `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware
+| File                | Description                                                                                   |
+|---------------------|-----------------------------------------------------------------------------------------------|
+| `xxx_reg.h`/`xx_struct.h` | Defines registers layout of a specific module. These files are automated, and should not be updated manually. <br/> Please note the register names and layout are subject to change between different chip series. |
+| `xxx_pins.h`        | Defines the unchangeable GPIOs used by a specific module. <br/> e.g. if a high speed signal is routed through IO MUX, its corresponding GPIO is not selectable. |
+| `soc_caps.h`        | Describes the differences in capabilities between different chips. <br/> The macros here can also affect cmake build system, Kconfig system, docs system, pytest and CI environment. <br/> **Changes to this file requires extra caution as they are part of the public API.** |
+| `xxx_periph.h`      | This is the portal for each peripheral module at the SoC layer, <br/> containing all relevant register header files and organizing other key information, such as interrupt sources, hardware signal IDs, etc. |
+| `xxx.peripherals.ld` | This is the linker script that defines each module's memory address. |

-Specially, the `xxx_reg.h` and `xxx_struct.h` headers that generated by script are under `register/soc` folder. Please DO NOT **add** other manual coded files under this folder.
+## The SoC Capabilities

-For other soc headers that are used as wrapper, definition, signaling, mapping or manual coded registers, please add them under `include/soc` folder.
+There are two documents describing SoC capabilities, `soc_caps.h` and `soc_caps_full.h`. The former is a public header file, and the information in it is coarse-grained. The latter is a header file for internal developers that contains fine-grained module information. To used the soc capability macros, you should use the macro functions offered by `soc/soc_caps_eval.h`.
+
+| Macro function | Description | Example |
+|----------------|-------------|---------|
+| `SOC_IS` | Checks if the current SoC is a specific one. | `SOC_IS(ESP32)` |
+| `SOC_HAS` | Checks if the current SoC has a specific module. | `SOC_HAS(DAC)` |
+| `SOC_MODULE_ATTR` | Get the attribute of a specific module. | `SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL)` |
+| `SOC_MODULE_SUPPORT` | Checks if the current SoC supports a specific feature. | `SOC_MODULE_SUPPORT(GPTIMER, ETM)` |
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -191,10 +191,6 @@ config SOC_XTAL_SUPPORT_40M
    bool
    default y

-config SOC_XTAL_SUPPORT_AUTO_DETECT
-    bool
-    default y
-
 config SOC_ADC_RTC_CTRL_SUPPORTED
    bool
    default y
@@ -249,11 +245,11 @@ config SOC_ADC_DIGI_MONITOR_NUM

 config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
    int
-    default 2
+    default 2000000

 config SOC_ADC_SAMPLE_FREQ_THRES_LOW
    int
-    default 20
+    default 20000

 config SOC_ADC_RTC_MIN_BITWIDTH
    int
@@ -439,10 +435,6 @@ config SOC_I2S_SUPPORTS_ADC
    bool
    default y

-config SOC_I2S_SUPPORTS_DAC
-    bool
-    default y
-
 config SOC_I2S_SUPPORTS_LCD_CAMERA
    bool
    default y
@@ -691,26 +683,6 @@ config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
    bool
    default y

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 2
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 64
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 4
-
-config SOC_TIMER_GROUP_SUPPORT_APB
-    bool
-    default y
-
 config SOC_LP_TIMER_BIT_WIDTH_LO
    int
    default 32
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -37,6 +37,10 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
 #ifdef __has_include
 #  if __has_include("sdkconfig.h")
 #    include "sdkconfig.h"
@@ -55,10 +59,11 @@
 // Define warning strings here for ECO-ed features to show error when they are used without being
 // defined correctly
 #define SOC_BROWNOUT_RESET_SUPPORTED    "Not determined" // [gen_soc_caps:ignore]
-#define SOC_TWAI_BRP_DIV_SUPPORTED      "Not determined" // [gen_soc_caps:ignore]
 #define SOC_DPORT_WORKAROUND            "Not determined" // [gen_soc_caps:ignore]
 #endif

+#define _SOC_CAPS_TARGET_IS_ESP32 1 // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_CAPS_ECO_VER_MAX        301

@@ -114,7 +119,6 @@
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_26M            1
 #define SOC_XTAL_SUPPORT_40M            1
-#define SOC_XTAL_SUPPORT_AUTO_DETECT    1   // Measure XTAL freq with an internal RC clock

 /*-------------------------- ADC CAPS ----------------------------------------*/
 /*!< SAR ADC Module*/
@@ -135,8 +139,8 @@
 #define SOC_ADC_DIGI_RESULT_BYTES               (2)
 #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
 #define SOC_ADC_DIGI_MONITOR_NUM                (0U) // to reference `IDF_TARGET_SOC_ADC_DIGI_MONITOR_NUM` in document
-#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          (2*1000*1000)
-#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           (20*1000)
+#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          (2000000)
+#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           (20000)

 /*!< RTC */
 #define SOC_ADC_RTC_MIN_BITWIDTH                (9)
@@ -226,7 +230,6 @@
 #define SOC_I2S_PDM_MAX_RX_LINES    (1U)
 #define SOC_I2S_SUPPORTS_ADC_DAC    (1)
 #define SOC_I2S_SUPPORTS_ADC        (1)
-#define SOC_I2S_SUPPORTS_DAC        (1)
 #define SOC_I2S_SUPPORTS_LCD_CAMERA (1)
 #define SOC_I2S_MAX_DATA_WIDTH      (24)

@@ -322,13 +325,6 @@
 // Peripheral supports DIO, DOUT, QIO, or QOUT
 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host)         ({(void)spi_host; 1;})

-/*-------------------------- TIMER GROUP CAPS --------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (2)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (4)
-#define SOC_TIMER_GROUP_SUPPORT_APB       (1)
-
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
@@ -347,7 +343,6 @@
 #define SOC_TWAI_BRP_MIN                2
 #if SOC_CAPS_ECO_VER >= 200
 #  define SOC_TWAI_BRP_MAX              256
-#  define SOC_TWAI_BRP_DIV_SUPPORTED    1
 #else
 #  define SOC_TWAI_BRP_MAX              128
 #endif
--- a/components/soc/esp32/include/soc/soc_caps_full.h
+++ b/components/soc/esp32/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   2 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       64 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         2  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32/timer_periph.c
+++ b/components/soc/esp32/timer_periph.c
@@ -4,32 +4,31 @@
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "soc/soc.h"
 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][2] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-                [1] = "TIMG0T1",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
-                [1] = ETS_TG0_T1_LEVEL_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE,
        },
        [1] = {
-            .module_name = {
-                [0] = "TIMG1T0",
-                [1] = "TIMG1T1",
-            },
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
-                [1] = ETS_TG1_T1_LEVEL_INTR_SOURCE,
-            }
-        }
+            .module_name = "TIMG0T1",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T1_LEVEL_INTR_SOURCE,
+        },
+    },
+    [1] = {
+        [0] = {
+            .module_name = "TIMG1T0",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
+        },
+        [1] = {
+            .module_name = "TIMG1T1",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T1_LEVEL_INTR_SOURCE,
+        },
    }
 };
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -603,26 +603,6 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
    bool
    default y

-config SOC_TIMER_GROUPS
-    int
-    default 1
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 1
-
 config SOC_LP_TIMER_BIT_WIDTH_LO
    int
    default 32
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -16,6 +16,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32C2     1 // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
@@ -268,13 +274,6 @@
 #define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)

-/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (1U)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (1U)
-
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
--- a/components/soc/esp32c2/include/soc/soc_caps_full.h
+++ b/components/soc/esp32c2/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   1 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       54 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         1  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32c2/timer_periph.c
+++ b/components/soc/esp32c2/timer_periph.c
@@ -1,21 +1,17 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[1][1] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE,
        },
    }
 };
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -863,30 +863,6 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
    bool
    default y

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_SUPPORT_APB
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
 config SOC_LP_TIMER_BIT_WIDTH_LO
    int
    default 32
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -16,6 +16,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32C3     1  // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
@@ -363,14 +369,6 @@
 #define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)

-/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_SUPPORT_APB       (1)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
-
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
--- a/components/soc/esp32c3/include/soc/soc_caps_full.h
+++ b/components/soc/esp32c3/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   2 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       54 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         1  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32c3/timer_periph.c
+++ b/components/soc/esp32c3/timer_periph.c
@@ -6,25 +6,19 @@

 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE,
+        },
+    },
+    [1] = {
+        [0] = {
+            .module_name = "TIMG1T0",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
        },
-        [1] = {
-            .module_name = {
-                [0] = "TIMG1T0",
-            },
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
-            }
-        }
    }
 };
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -1303,30 +1303,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
    int
    default 16

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
 config SOC_TIMER_SUPPORT_ETM
    bool
    default y
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -16,6 +16,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32C5     1 // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_ADC_SUPPORTED               1
 #define SOC_ANA_CMPR_SUPPORTED          1
@@ -505,12 +511,6 @@
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 #define SOC_TIMER_SUPPORT_ETM             (1)
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)

--- a/components/soc/esp32c5/include/soc/soc_caps_full.h
+++ b/components/soc/esp32c5/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   2 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       54 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         1  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32c5/timer_periph.c
+++ b/components/soc/esp32c5/timer_periph.c
@@ -6,26 +6,20 @@

 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE,
+        },
+    },
+    [1] = {
+        [0] = {
+            .module_name = "TIMG1T0",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
        },
-        [1] = {
-            .module_name = {
-                [0] = "TIMG1T0",
-            },
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
-            }
-        }
    }
 };

@@ -117,7 +111,7 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = {
    },
 };

-const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
+const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = {
    [0] = {
        [0] = {
            .module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
--- a/components/soc/esp32c5/wdt_periph.c
+++ b/components/soc/esp32c5/wdt_periph.c
@@ -26,7 +26,7 @@ static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
 };

-const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
+const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = {
    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
 };
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -1163,30 +1163,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
    int
    default 16

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
 config SOC_TIMER_SUPPORT_ETM
    bool
    default y
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -16,6 +16,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32C6     1 // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
@@ -454,12 +460,6 @@
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 #define SOC_TIMER_SUPPORT_ETM             (1)
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)

--- a/components/soc/esp32c6/include/soc/soc_caps_full.h
+++ b/components/soc/esp32c6/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   2 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       54 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         1  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32c6/timer_periph.c
+++ b/components/soc/esp32c6/timer_periph.c
@@ -6,26 +6,20 @@

 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE,
+        },
+    },
+    [1] = {
+        [0] = {
+            .module_name = "TIMG1T0",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
        },
-        [1] = {
-            .module_name = {
-                [0] = "TIMG1T0",
-            },
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
-            }
-        }
    }
 };

@@ -117,7 +111,7 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = {
    },
 };

-const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
+const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = {
    [0] = {
        [0] = {
            .module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
--- a/components/soc/esp32c6/wdt_periph.c
+++ b/components/soc/esp32c6/wdt_periph.c
@@ -26,7 +26,7 @@ static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
 };

-const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
+const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = {
    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
 };
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -891,30 +891,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
    int
    default 16

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_SUPPORT_RC_FAST
-    bool
-    default y
-
 config SOC_TIMER_SUPPORT_SLEEP_RETENTION
    bool
    default y
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -16,6 +16,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32C61    1 // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_ADC_SUPPORTED               1
 #define SOC_ANA_CMPR_SUPPORTED          1
@@ -369,12 +375,6 @@
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
 #define SOC_TIMER_SUPPORT_ETM             (1)

--- a/components/soc/esp32c61/include/soc/soc_caps_full.h
+++ b/components/soc/esp32c61/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   2 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       54 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         1  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32c61/timer_periph.c
+++ b/components/soc/esp32c61/timer_periph.c
@@ -6,26 +6,20 @@

 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_INTR_SOURCE,
+        },
+    },
+    [1] = {
+        [0] = {
+            .module_name = "TIMG1T0",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T0_INTR_SOURCE,
        },
-        [1] = {
-            .module_name = {
-                [0] = "TIMG1T0",
-            },
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_INTR_SOURCE,
-            }
-        }
    }
 };

@@ -117,7 +111,7 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = {
    },
 };

-const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
+const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = {
    [0] = {
        [0] = {
            .module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
--- a/components/soc/esp32c61/wdt_periph.c
+++ b/components/soc/esp32c61/wdt_periph.c
@@ -26,7 +26,7 @@ static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
 };

-const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
+const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = {
    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
 };
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -1179,30 +1179,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
    int
    default 16

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
 config SOC_TIMER_SUPPORT_ETM
    bool
    default y
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -16,6 +16,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32H2 1 // [gen_soc_caps:ignore]
+
 #ifdef __has_include
 #  if __has_include("sdkconfig.h")
 #    include "sdkconfig.h"
@@ -472,12 +478,6 @@
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 #define SOC_TIMER_SUPPORT_ETM             (1)
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)

--- a/components/soc/esp32h2/include/soc/soc_caps_full.h
+++ b/components/soc/esp32h2/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   2 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       54 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         1  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32h2/timer_periph.c
+++ b/components/soc/esp32h2/timer_periph.c
@@ -6,26 +6,20 @@

 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE,
+        },
+    },
+    [1] = {
+        [0] = {
+            .module_name = "TIMG1T0",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
        },
-        [1] = {
-            .module_name = {
-                [0] = "TIMG1T0",
-            },
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
-            }
-        }
    }
 };

@@ -117,7 +111,7 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = {
    },
 };

-const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
+const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = {
    [0] = {
        [0] = {
            .module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
--- a/components/soc/esp32h2/wdt_periph.c
+++ b/components/soc/esp32h2/wdt_periph.c
@@ -26,7 +26,7 @@ static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
 };

-const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
+const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = {
    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
 };
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -639,30 +639,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
    int
    default 16

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_SUPPORT_RC_FAST
-    bool
-    default y
-
 config SOC_TIMER_SUPPORT_SLEEP_RETENTION
    bool
    default y
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -16,6 +16,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32H21  1 // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 // #define SOC_ADC_SUPPORTED               1    //TODO: [ESP32H21] IDF-11589, IDF-11592
 // #define SOC_ANA_CMPR_SUPPORTED          1
@@ -436,12 +442,6 @@
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
 // #define SOC_TIMER_SUPPORT_ETM             (1)    //TODO: [ESP32H21] IDF-11576
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)

--- a/components/soc/esp32h21/include/soc/soc_caps_full.h
+++ b/components/soc/esp32h21/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   2 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       54 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         1  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32h21/timer_periph.c
+++ b/components/soc/esp32h21/timer_periph.c
@@ -6,30 +6,23 @@

 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_INTR_SOURCE,
+        },
+    },
+    [1] = {
+        [0] = {
+            .module_name = "TIMG1T0",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T0_INTR_SOURCE,
        },
-        [1] = {
-            .module_name = {
-                [0] = "TIMG1T0",
-            },
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_INTR_SOURCE,
-            }
-        }
    }
 };

-#if SOC_PAU_SUPPORTED && SOC_TIMER_SUPPORT_SLEEP_RETENTION
 /*  Registers in retention context:
 *      TIMG_T0CONFIG_REG
 *      TIMG_T0ALARMLO_REG
@@ -118,7 +111,7 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = {
    },
 };

-const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
+const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = {
    [0] = {
        [0] = {
            .module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
@@ -134,4 +127,3 @@ const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS
        }
    },
 };
-#endif  //SOC_PAU_SUPPORTED && SOC_TIMER_SUPPORT_SLEEP_RETENTION
--- a/components/soc/esp32h21/wdt_periph.c
+++ b/components/soc/esp32h21/wdt_periph.c
@@ -26,7 +26,7 @@ static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
 };

-const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
+const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = {
    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
 };
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -399,30 +399,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
    int
    default 16

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
 config SOC_TIMER_SUPPORT_SLEEP_RETENTION
    bool
    default y
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -24,6 +24,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32H4        1 // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 // #define SOC_ADC_SUPPORTED               1    // TODO: [ESP32H4] IDF-12368 IDF-12370
 // #define SOC_ANA_CMPR_SUPPORTED          1    // TODO: [ESP32H4] IDF-12395 big change!!
@@ -428,12 +434,6 @@
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 // #define SOC_TIMER_SUPPORT_ETM             (1)     // TODO: [ESP32H4] IDF-12355
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)

--- a/components/soc/esp32h4/include/soc/soc_caps_full.h
+++ b/components/soc/esp32h4/include/soc/soc_caps_full.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/soc_caps_eval.h"
+
+/*--------------------------- Timer Group -------------------------------------------*/
+#define _SOC_CAPS_TIMG_INST_NUM                   2 // Number of Timer Group instances
+
+/*--------------------------- GPTIMER ---------------------------------------*/
+#define _SOC_CAPS_GPTIMER_COUNTER_BIT_WIDTH       54 // Bit width of GPTIMER counter
+#define _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG         1  // Number of general purpose timers in each Timer Group
+#define _SOC_CAPS_GPTIMER_TIMERS_TOTAL            (_SOC_CAPS_TIMG_INST_NUM * _SOC_CAPS_GPTIMER_TIMERS_PER_TIMG)
+
+/*--------------------------- Watch Dog ------------------------------------------*/
+#define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
--- a/components/soc/esp32h4/timer_periph.c
+++ b/components/soc/esp32h4/timer_periph.c
@@ -6,30 +6,23 @@

 #include "soc/timer_periph.h"

-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
+const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][1] = {
+    [0] = {
        [0] = {
-            .module_name = {
-                [0] = "TIMG0T0",
-            },
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_INTR_SOURCE,
-            }
+            .module_name = "TIMG0T0",
+            .parent_module = PERIPH_TIMG0_MODULE,
+            .irq_id = ETS_TG0_T0_INTR_SOURCE,
+        },
+    },
+    [1] = {
+        [0] = {
+            .module_name = "TIMG1T0",
+            .parent_module = PERIPH_TIMG1_MODULE,
+            .irq_id = ETS_TG1_T0_INTR_SOURCE,
        },
-        [1] = {
-            .module_name = {
-                [0] = "TIMG1T0",
-            },
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_INTR_SOURCE,
-            }
-        }
    }
 };

-#if SOC_PAU_SUPPORTED && SOC_TIMER_SUPPORT_SLEEP_RETENTION
 /*  Registers in retention context:
 *      TIMG_T0CONFIG_REG
 *      TIMG_T0ALARMLO_REG
@@ -118,7 +111,7 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = {
    },
 };

-const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
+const soc_timg_gptimer_retention_desc_t soc_timg_gptimer_retention_infos[2][1] = {
    [0] = {
        [0] = {
            .module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
@@ -134,4 +127,3 @@ const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS
        }
    },
 };
-#endif  //SOC_PAU_SUPPORTED && SOC_TIMER_SUPPORT_SLEEP_RETENTION
--- a/components/soc/esp32h4/wdt_periph.c
+++ b/components/soc/esp32h4/wdt_periph.c
@@ -29,7 +29,7 @@ static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
 };

-const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
+const tg_reg_ctx_link_t tg_wdt_regs_retention[2] = {
    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
 };
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1563,10 +1563,6 @@ config SOC_SPI_SUPPORT_CLK_RC_FAST
    bool
    default y

-config SOC_SPI_SUPPORT_CLK_SPLL
-    bool
-    default y
-
 config SOC_MSPI_HAS_INDEPENT_IOMUX
    bool
    default y
@@ -1579,10 +1575,6 @@ config SOC_SPI_MAX_PRE_DIVIDER
    int
    default 16

-config SOC_LP_SPI_PERIPH_NUM
-    bool
-    default y
-
 config SOC_LP_SPI_MAXIMUM_BUFFER_SIZE
    int
    default 64
@@ -1651,10 +1643,6 @@ config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED
    bool
    default y

-config SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
-    bool
-    default y
-
 config SOC_SYSTIMER_COUNTER_NUM
    int
    default 2
@@ -1699,30 +1687,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
    int
    default 16

-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 2
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 4
-
 config SOC_TIMER_SUPPORT_ETM
    bool
    default y
@@ -2075,10 +2039,6 @@ config SOC_PM_RETENTION_MODULE_NUM
    int
    default 64

-config SOC_PSRAM_VDD_POWER_MPLL
-    bool
-    default y
-
 config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
    bool
    default y
@@ -2115,10 +2075,6 @@ config SOC_PERIPH_CLK_CTRL_SHARED
    bool
    default y

-config SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT
-    bool
-    default y
-
 config SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
    bool
    default y
@@ -2183,14 +2139,6 @@ config SOC_I3C_MASTER_PERIPH_NUM
    bool
    default y

-config SOC_I3C_MASTER_ADDRESS_TABLE_NUM
-    int
-    default 12
-
-config SOC_I3C_MASTER_COMMAND_TABLE_NUM
-    int
-    default 12
-
 config SOC_LP_CORE_SUPPORT_ETM
    bool
    default y
@@ -2199,10 +2147,6 @@ config SOC_LP_CORE_SUPPORT_LP_ADC
    bool
    default y

-config SOC_LP_CORE_SUPPORT_LP_VAD
-    bool
-    default y
-
 config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
    bool
    default y
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -16,6 +16,12 @@

 #pragma once

+#if __has_include("soc/soc_caps_eval.h")
+#include "soc/soc_caps_eval.h"
+#endif
+
+#define _SOC_CAPS_TARGET_IS_ESP32P4     1 // [gen_soc_caps:ignore]
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_ADC_SUPPORTED               1
 #define SOC_ANA_CMPR_SUPPORTED          1
@@ -227,7 +233,6 @@
 #define SOC_DMA2D_GROUPS                            (1U) // Number of 2D-DMA groups
 #define SOC_DMA2D_TX_CHANNELS_PER_GROUP             (3)  // Number of 2D-DMA TX (OUT) channels in each group
 #define SOC_DMA2D_RX_CHANNELS_PER_GROUP             (2)  // Number of 2D-DMA RX (IN) channels in each group
-// #define SOC_DMA2D_SUPPORT_ETM              (1)  // Support ETM submodule

 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
@@ -571,7 +576,6 @@
 #define SOC_SPI_SUPPORT_OCT                 1
 #define SOC_SPI_SUPPORT_CLK_XTAL            1
 #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
-#define SOC_SPI_SUPPORT_CLK_SPLL            1

 // Peripheral supports DIO, DOUT, QIO, or QOUT
 // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
@@ -582,8 +586,8 @@
 #define SOC_SPI_MAX_PRE_DIVIDER     16

 /*-------------------------- LP SPI CAPS ----------------------------------------*/
-#define SOC_LP_SPI_PERIPH_NUM              1
 #define SOC_LP_SPI_MAXIMUM_BUFFER_SIZE     64
+
 /*-------------------------- SPIRAM CAPS ----------------------------------------*/
 #define SOC_SPIRAM_XIP_SUPPORTED        1

@@ -607,8 +611,6 @@
 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
 #define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED        1

-#define SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT        1
-
 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
 #define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
 #define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
@@ -625,12 +627,6 @@
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  2
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  2
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH 54
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      1
-#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   1
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      4
 #define SOC_TIMER_SUPPORT_ETM             1
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION 1

@@ -764,9 +760,6 @@

 #define SOC_PM_RETENTION_MODULE_NUM         (64)

-/*-------------------------- PSRAM CAPS ----------------------------*/
-#define SOC_PSRAM_VDD_POWER_MPLL    (1)
-
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)

@@ -782,7 +775,6 @@
 #define SOC_PERIPH_CLK_CTRL_SHARED                (1)     /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */

 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
-#define SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT                (1)
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                  (1)
 #define SOC_TSENS_IS_INDEPENDENT_FROM_ADC                    (1)  /*!< Temperature sensor is a separate module, not share regs with ADC */
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM                   (1)
@@ -809,11 +801,8 @@

 /*--------------------------- I3C ---------------------------------*/
 #define SOC_I3C_MASTER_PERIPH_NUM                   (1)
-#define SOC_I3C_MASTER_ADDRESS_TABLE_NUM            (12)
-#define SOC_I3C_MASTER_COMMAND_TABLE_NUM            (12)

 /*------------------------------------- ULP CAPS -------------------------------------*/
 #define SOC_LP_CORE_SUPPORT_ETM                     (1) /*!< LP Core supports ETM */
 #define SOC_LP_CORE_SUPPORT_LP_ADC                  (1) /*!< LP ADC can be accessed from the LP-Core */
-#define SOC_LP_CORE_SUPPORT_LP_VAD                  (1) /*!< LP VAD can be accessed from the LP-Core */
 #define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS   (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
--- a/Show More
+++ b/Show More