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Merge branch 'fix/fix_c3_c2_cache_freeze_soc_caps_issue_v5.2' into 'release/v5.2'

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cache: fixed SOC_CACHE_FREEZE_SUPPORTED not defined on C3 / C2 issue (v5.2)

See merge request espressif/esp-idf!39885
This commit is contained in:
morris
2025-06-26 18:14:20 +08:00
parent 513385b9ec 7a59713121
commit e190f6b594
6 changed files with 64 additions and 2 deletions
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28
components/hal/esp32c2/include/hal/cache_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -149,6 +149,32 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
Cache_Invalidate_Addr(vaddr, size);
}
/**
* @brief Freeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
}
/**
* @brief Unfreeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
Cache_Freeze_ICache_Disable();
}
/**
* @brief Get Cache line size, in bytes
*

28
components/hal/esp32c3/include/hal/cache_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -152,6 +152,32 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
Cache_Invalidate_Addr(vaddr, size);
}
/**
* @brief Freeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
}
/**
* @brief Unfreeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
Cache_Freeze_ICache_Disable();
}
/**
* @brief Get Cache line size, in bytes
*

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
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@@ -203,6 +203,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CACHE_FREEZE_SUPPORTED
bool
default y
config SOC_CPU_CORES_NUM
int
default 1

1
components/soc/esp32c2/include/soc/soc_caps.h
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@@ -95,6 +95,7 @@
/*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
#define SOC_CACHE_FREEZE_SUPPORTED 1
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_CORES_NUM (1U)

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
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@@ -287,6 +287,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CACHE_FREEZE_SUPPORTED
bool
default y
config SOC_CACHE_MEMORY_IBANK_SIZE
hex
default 0x4000

1
components/soc/esp32c3/include/soc/soc_caps.h
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@@ -126,6 +126,7 @@
/*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
#define SOC_CACHE_FREEZE_SUPPORTED 1
#define SOC_CACHE_MEMORY_IBANK_SIZE 0x4000 // has to be same as the definition in ROM component
/*-------------------------- CPU CAPS ----------------------------------------*/