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Merge branch 'fix/esp32p4_eco5_clic' into 'master'

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fix: get rid of the hardware workarounds for the latest ESP32P4 revision

Closes IDF-13409, IDF-13781, and IDF-13782

See merge request espressif/esp-idf!41719
This commit is contained in:
Omar Chebib
2025-09-19 15:00:21 +08:00
parent 0ac9dfbbe0 cea17beaba
commit e1c2ddeab6
3 changed files with 6 additions and 4 deletions
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2
components/esp_rom/esp32p4/esp_rom_caps.h
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@@ -25,6 +25,6 @@
#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions
#define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version
#define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information
#define ESP_ROM_CLIC_INT_TYPE_PATCH (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt is invalid TODO: IDF-13409 #define ESP_ROM_CLIC_INT_TYPE_PATCH (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt (old revisions)
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.

5
components/esp_rom/patches/esp_rom_clic.c
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@@ -1,14 +1,15 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include "sdkconfig.h"
#include "esp_rom_caps.h" #include "esp_rom_caps.h"
#include "soc/clic_reg.h" #include "soc/clic_reg.h"
#include "riscv/interrupt.h" #include "riscv/interrupt.h"
#if ESP_ROM_CLIC_INT_TYPE_PATCH #if ESP_ROM_CLIC_INT_TYPE_PATCH && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
/* Rom api esprv_intc_int_set_type, if the configured interrupt type is INTR_TYPE_EDGE, /* Rom api esprv_intc_int_set_type, if the configured interrupt type is INTR_TYPE_EDGE,
* the actual configured type is still INTR_TYPE_LEVEL. So the patch is to solve this issue. * the actual configured type is still INTR_TYPE_LEVEL. So the patch is to solve this issue.

3
components/riscv/vectors.S
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@@ -278,7 +278,8 @@ hwlp_not_used:
* For example, bit 1 can be set and bit 0 won't, even if the reason is an FPU instruction. */ * For example, bit 1 can be set and bit 0 won't, even if the reason is an FPU instruction. */
andi a1, a0, EXT_ILL_RSN_FPU andi a1, a0, EXT_ILL_RSN_FPU
bnez a1, rtos_save_fpu_coproc bnez a1, rtos_save_fpu_coproc
#if SOC_CPU_HAS_FPU_EXT_ILL_BUG /* The FPU_EXT_ILL bug was fixed on revision 3.0 and higher */
#if SOC_CPU_HAS_FPU_EXT_ILL_BUG && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
/* If the SOC present the hardware EXT_ILL CSR bug, it doesn't support FPU load/store detection /* If the SOC present the hardware EXT_ILL CSR bug, it doesn't support FPU load/store detection
* so we have to check the instruction's opcode (in `mtval` = `t0`) */ * so we have to check the instruction's opcode (in `mtval` = `t0`) */
andi a0, t0, 0b1011111 andi a0, t0, 0b1011111