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fix: add spi_flash.h for s2, s3, c3 targets in cpu_start.c

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update s2, s3, c3 ld files spi_flash_attach to esp_rom_spiflash_attach
This commit is contained in:
Fu Hanxi
2021-01-26 11:54:22 +08:00
parent 119b61451f
commit e4e375f488
6 changed files with 16 additions and 7 deletions
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2
components/esp32c3/ld/esp32c3.project.ld.in
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@ -280,7 +280,7 @@ SECTIONS
. = SIZEOF(.flash.text);
. = ALIGN(0x10000) + 0x20;
_rodata_reserved_start = .;
} > drom0_0_seg
} > default_rodata_seg
/* When modifying the alignment, don't forget to update tls_section_alignment in pxPortInitialiseStack */
.flash.rodata : ALIGN(0x10)

2
components/esp32s3/ld/esp32s3.project.ld.in
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@ -311,7 +311,7 @@ SECTIONS
. = SIZEOF(.flash.text);
. = ALIGN(0x10000) + 0x20;
_rodata_reserved_start = .;
} > drom0_0_seg
} > default_rodata_seg
/* When modifying the alignment, don't forget to update tls_section_alignment in pxPortInitialiseStack */
.flash.rodata : ALIGN(0x10)

2
components/esp_rom/esp32c3/ld/esp32c3.rom.ld
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@ -120,7 +120,7 @@ PROVIDE( esp_rom_spiflash_config_readmode = 0x40000154 );
PROVIDE( esp_rom_spiflash_read_status = 0x40000158 );
PROVIDE( esp_rom_spiflash_read_statushigh = 0x4000015c );
PROVIDE( esp_rom_spiflash_write_status = 0x40000160 );
PROVIDE( spi_flash_attach = 0x40000164 );
PROVIDE( esp_rom_spiflash_attach = 0x40000164 );
PROVIDE( spi_flash_get_chip_size = 0x40000168 );
PROVIDE( spi_flash_guard_set = 0x4000016c );
PROVIDE( spi_flash_guard_get = 0x40000170 );

2
components/esp_rom/esp32s2/ld/esp32s2.rom.ld
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@ -611,7 +611,7 @@ PROVIDE ( SPIEraseArea = 0x40017470 );
PROVIDE ( SPIEraseBlock = 0x4001710c );
PROVIDE ( SPIEraseChip = 0x400170ec );
PROVIDE ( SPIEraseSector = 0x4001716c );
PROVIDE ( spi_flash_attach = 0x40017004 );
PROVIDE ( esp_rom_spiflash_attach = 0x40017004 );
PROVIDE ( spi_flash_boot_attach = 0x40016fc0 );
PROVIDE ( spi_flash_check_suspend_cb = 0x3ffffd58 );
PROVIDE ( SPI_flashchip_data = 0x3ffffd3c );

2
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
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@ -1954,7 +1954,7 @@ PROVIDE ( spi_cache_mode_switch = 0x4004d9f0 );
PROVIDE ( spi_common_set_dummy_output = 0x4004dcac );
PROVIDE ( spi_common_set_flash_cs_timing = 0x4004dbf8 );
PROVIDE ( spi_dummy_len_fix = 0x4004cb30 );
PROVIDE ( spi_flash_attach = 0x4004e100 );
PROVIDE ( esp_rom_spiflash_attach = 0x4004e100 );
PROVIDE ( spi_flash_boot_attach = 0x4004e0a0 );
PROVIDE ( spi_flash_chip_gd_get_io_mode = 0x4004f248 );
PROVIDE ( spi_flash_chip_gd_probe = 0x4004f1d8 );

13
components/esp_system/port/cpu_start.c
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@ -84,11 +84,20 @@
#include "bootloader_mem.h"
#if CONFIG_IDF_TARGET_ESP32
#if CONFIG_APP_BUILD_TYPE_ELF_RAM
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#endif // CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#endif // CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#endif // CONFIG_IDF_TARGET_ESP32S3
#if CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#endif // CONFIG_IDF_TARGET_ESP32C3
#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
#endif
#include "esp_private/startup_internal.h"
#include "esp_private/system_internal.h"