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Merge branch 'feat/support_c5_c61_clkoutput' into 'master'

Browse Source 
feat(esp_hw_support): support clock output feature on esp32c5/esp32c61

Closes IDF-10968 and IDF-10970

See merge request espressif/esp-idf!40801
This commit is contained in:
Wu Zheng Hui
2025-07-30 16:13:52 +08:00
parent b0f22503b4 bf3c79068d
commit e8ef305398
18 changed files with 212 additions and 80 deletions
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10
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@@ -154,9 +154,9 @@ TEST_CASE("GPIO output internal clock one-to-many", "[gpio_output_clock][ignore]
TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[3], test_clk_out_io[0], &clkout_mapping_hdl_7)); // [0]:1 [1]:0 [2]:2
// Stop all
esp_clock_output_stop(clkout_mapping_hdl_2);
esp_clock_output_stop(clkout_mapping_hdl_5);
esp_clock_output_stop(clkout_mapping_hdl_6);
esp_clock_output_stop(clkout_mapping_hdl_7);
TEST_ESP_OK(esp_clock_output_stop(clkout_mapping_hdl_2));
TEST_ESP_OK(esp_clock_output_stop(clkout_mapping_hdl_5));
// clkout_mapping_hdl_6 never been alloc succeed, not need to do stop.
TEST_ESP_OK(esp_clock_output_stop(clkout_mapping_hdl_7));
}
#endif

6
components/hal/esp32c5/clk_tree_hal.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -72,10 +72,10 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
{
abort(); // TODO: IDF-10968
gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
}
void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
{
abort(); // TODO: IDF-10968
gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
}

33
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@@ -603,6 +603,39 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
return REG_READ(RTC_SLOW_CLK_CAL_REG);
}
/*
* Enable/Disable the clock gate for clock output signal source
*/
static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
{
switch (clk_src)
{
case CLKOUT_SIG_PLL_F22M:
PCR.ctrl_clk_out_en.clk22_oen = en;
break;
case CLKOUT_SIG_PLL_F44M:
PCR.ctrl_clk_out_en.clk44_oen = en;
break;
case CLKOUT_SIG_PLL_F40M:
PCR.ctrl_clk_out_en.clk_bb_oen = en;
break;
case CLKOUT_SIG_PLL_F80M:
PCR.ctrl_clk_out_en.clk80_oen = en;
break;
case CLKOUT_SIG_PLL_F160M:
PCR.ctrl_clk_out_en.clk160_oen = en;
break;
case CLKOUT_SIG_PLL_F480M:
PCR.ctrl_clk_out_en.clk_480m_oen = en;
break;
case CLKOUT_SIG_XTAL:
PCR.ctrl_clk_out_en.clk_xtal_oen = en;
break;
default:
break;
}
}
#ifdef __cplusplus
}
#endif

14
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@@ -17,6 +17,7 @@
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/gpio_ext_reg.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
@@ -716,6 +717,19 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num
IO_MUX.gpio[gpio_num].mcu_oe = 1;
}
/**
* @brief Control the pin in the IOMUX
*
* @param bmap write mask of control value
* @param val Control value
* @param shift write mask shift of control value
*/
__attribute__((always_inline))
static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
SET_PERI_REG_BITS(GPIO_EXT_PIN_CTRL_REG, bmap, val, shift);
}
#ifdef __cplusplus
}
#endif

13
components/hal/esp32c61/clk_tree_hal.c
View File

@@ -1,11 +1,12 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/gpio_ll.h"
#include "hal/assert.h"
uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
@@ -65,3 +66,13 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
HAL_ASSERT(freq == SOC_XTAL_FREQ_40M);
return freq;
}
void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
{
gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
}
void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
{
gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
}

30
components/hal/esp32c61/include/hal/clk_tree_ll.h
View File

@@ -570,6 +570,36 @@ static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_f
return REG_READ(RTC_FIX_US_LOW_REG) | ((uint64_t)REG_READ(RTC_FIX_US_HIGH_REG) << 32);
}
/*
* Enable/Disable the clock gate for clock output signal source
*/
static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
{
switch (clk_src)
{
case CLKOUT_SIG_PLL_F22M:
PCR.ctrl_clk_out_en.clk22_oen = en;
break;
case CLKOUT_SIG_PLL_F44M:
PCR.ctrl_clk_out_en.clk44_oen = en;
break;
case CLKOUT_SIG_PLL_F40M:
PCR.ctrl_clk_out_en.clk_bb_oen = en;
break;
case CLKOUT_SIG_PLL_F80M:
PCR.ctrl_clk_out_en.clk80_oen = en;
break;
case CLKOUT_SIG_PLL_F160M:
PCR.ctrl_clk_out_en.clk160_oen = en;
break;
case CLKOUT_SIG_XTAL:
PCR.ctrl_clk_out_en.clk_xtal_oen = en;
break;
default:
break;
}
}
#ifdef __cplusplus
}
#endif

13
components/hal/esp32c61/include/hal/gpio_ll.h
View File

@@ -18,6 +18,7 @@
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_ext_reg.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/pmu_struct.h"
@@ -716,6 +717,18 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num
IO_MUX.gpion[gpio_num].gpion_mcu_oe = 1;
}
/**
* @brief Control the pin in the IOMUX
*
* @param bmap write mask of control value
* @param val Control value
* @param shift write mask shift of control value
*/
__attribute__((always_inline))
static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
SET_PERI_REG_BITS(GPIO_EXT_PIN_CTRL_REG, bmap, val, shift);
}
#ifdef __cplusplus
}
#endif

8
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -603,6 +603,14 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
config SOC_CLOCKOUT_HAS_SOURCE_GATE
bool
default y
config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3

31
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@@ -538,19 +538,24 @@ typedef enum {
} soc_periph_flash_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum { // TODO
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
CLKOUT_SIG_APB = 18, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_INVALID = 0xFF,
typedef enum {
CLKOUT_SIG_INVALID = 0,
CLKOUT_SIG_PLL_F160M = 1, /*!< Divided from PLL_F480M */
CLKOUT_SIG_PLL_F22M = 2, /*!< Divided from PLL_F160M */
CLKOUT_SIG_PLL_F40M = 3, /*!< Divided from PLL_F160M */
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_PLL_F44M = 0xA, /*!< Divided from PLL_F160M */
CLKOUT_SIG_PLL_F480M = 0xB, /*!< From PLL, usually be 480MHz */
CLKOUT_SIG_PLL_F80M = 0xD, /*!< Divided from PLL_F160M */
CLKOUT_SIG_I2S_APB = 0xF, /*!< APB clock for i2s */
CLKOUT_SIG_CPU = 0x10, /*!< CPU clock */
CLKOUT_SIG_AHB = 0x11, /*!< AHB clock */
CLKOUT_SIG_APB = 0x12, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 0x15, /*!< External 32kHz crystal clock */
CLKOUT_SIG_EXT32K = 0x16, /*!< External slow clock input through XTAL_32K_P */
CLKOUT_SIG_RC_FAST = 0x17, /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_RC_32K = 0x18, /*!< Internal slow RC oscillator */
CLKOUT_SIG_RC_SLOW = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
} soc_clkout_sig_id_t;
#ifdef __cplusplus

15
components/soc/esp32c5/include/soc/clkout_channel.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include "esp_assert.h"
#include "soc/soc_caps.h"
#include "soc/gpio_ext_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/gpio_sig_map.h"
@@ -26,13 +27,13 @@ typedef enum clock_out_channel {
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
#define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
#define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? GPIO_EXT_CLK_OUT1 : \
(channel == CLKOUT_CHANNEL_2) ? GPIO_EXT_CLK_OUT2 : \
(channel == CLKOUT_CHANNEL_3) ? GPIO_EXT_CLK_OUT3 : 0)
#define CLKOUT_CHANNEL_SHIFT(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
#define CLKOUT_CHANNEL_SHIFT(channel) ((channel == CLKOUT_CHANNEL_1) ? GPIO_EXT_CLK_OUT1_S : \
(channel == CLKOUT_CHANNEL_2) ? GPIO_EXT_CLK_OUT2_S : \
(channel == CLKOUT_CHANNEL_3) ? GPIO_EXT_CLK_OUT3_S : 0)
ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");

3
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -248,7 +248,8 @@
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// The Clock Out signal is route to the pin by GPIO matrix
// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
/*-------------------------- RTCIO CAPS --------------------------------------*/

12
components/soc/esp32c5/register/soc/pcr_reg.h
View File

@@ -2161,13 +2161,13 @@ extern "C" {
#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S)
#define PCR_CLK160_OEN_V 0x00000001U
#define PCR_CLK160_OEN_S 5
/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1;
* Set 1 to enable 320m clock
/** PCR_CLK_480M_OEN : R/W; bitpos: [6]; default: 1;
* Set 1 to enable 480m clock
*/
#define PCR_CLK_320M_OEN (BIT(6))
#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S)
#define PCR_CLK_320M_OEN_V 0x00000001U
#define PCR_CLK_320M_OEN_S 6
#define PCR_CLK_480M_OEN (BIT(6))
#define PCR_CLK_480M_OEN_M (PCR_CLK_480M_OEN_V << PCR_CLK_480M_OEN_S)
#define PCR_CLK_480M_OEN_V 0x00000001U
#define PCR_CLK_480M_OEN_S 6
/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1;
* Reserved
*/

6
components/soc/esp32c5/register/soc/pcr_struct.h
View File

@@ -1791,10 +1791,10 @@ typedef union {
* Set 1 to enable 160m clock
*/
uint32_t clk160_oen:1;
/** clk_320m_oen : R/W; bitpos: [6]; default: 1;
* Set 1 to enable 320m clock
/** clk_480m_oen : R/W; bitpos: [6]; default: 1;
* Set 1 to enable 480m clock
*/
uint32_t clk_320m_oen:1;
uint32_t clk_480m_oen:1;
/** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1;
* Reserved
*/

8
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -479,6 +479,14 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
config SOC_CLOCKOUT_HAS_SOURCE_GATE
bool
default y
config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3

27
components/soc/esp32c61/include/soc/clk_tree_defs.h
View File

@@ -378,17 +378,22 @@ typedef enum {
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum {
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
CLKOUT_SIG_APB = 18, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_INVALID = 0xFF,
CLKOUT_SIG_INVALID = 0,
CLKOUT_SIG_PLL_F160M = 1, /*!< Divided from PLL_F480M */
CLKOUT_SIG_PLL_F22M = 2, /*!< Divided from PLL_F160M */
CLKOUT_SIG_PLL_F40M = 3, /*!< Divided from PLL_F160M */
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_PLL_F44M = 0xA, /*!< Divided from PLL_F160M */
CLKOUT_SIG_PLL_F80M = 0xD, /*!< Divided from PLL_F160M */
CLKOUT_SIG_I2S_APB = 0xF, /*!< APB clock for i2s */
CLKOUT_SIG_CPU = 0x10, /*!< CPU clock */
CLKOUT_SIG_AHB = 0x11, /*!< AHB clock */
CLKOUT_SIG_APB = 0x12, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 0x15, /*!< External 32kHz crystal clock */
CLKOUT_SIG_EXT32K = 0x16, /*!< External slow clock input through XTAL_32K_P */
CLKOUT_SIG_RC_FAST = 0x17, /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_RC_32K = 0x18, /*!< Internal slow RC oscillator */
CLKOUT_SIG_RC_SLOW = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
} soc_clkout_sig_id_t;
#ifdef __cplusplus

15
components/soc/esp32c61/include/soc/clkout_channel.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include "esp_assert.h"
#include "soc/soc_caps.h"
#include "soc/gpio_ext_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/gpio_sig_map.h"
@@ -26,13 +27,13 @@ typedef enum clock_out_channel {
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
#define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
#define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? GPIO_EXT_CLK_OUT1 : \
(channel == CLKOUT_CHANNEL_2) ? GPIO_EXT_CLK_OUT2 : \
(channel == CLKOUT_CHANNEL_3) ? GPIO_EXT_CLK_OUT3 : 0)
#define CLKOUT_CHANNEL_SHIFT(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
#define CLKOUT_CHANNEL_SHIFT(channel) ((channel == CLKOUT_CHANNEL_1) ? GPIO_EXT_CLK_OUT1_S : \
(channel == CLKOUT_CHANNEL_2) ? GPIO_EXT_CLK_OUT2_S : \
(channel == CLKOUT_CHANNEL_3) ? GPIO_EXT_CLK_OUT3_S : 0)
ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");

3
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -205,7 +205,8 @@
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// The Clock Out signal is route to the pin by GPIO matrix
// \#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
/*-------------------------- RTCIO CAPS --------------------------------------*/

45
components/soc/esp32c61/register/soc/gpio_ext_reg.h
View File

@@ -11,10 +11,11 @@
extern "C" {
#endif
/** GPIO_EXT_PAD_COMP_CONFIG_0_REG register
* PAD Compare configure Register
*/
#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_BASE + 0x58)
#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_EXT_BASE + 0x58)
/** GPIO_EXT_XPD_COMP_0 : R/W; bitpos: [0]; default: 0;
* Pad compare enable bit.
*/
@@ -41,7 +42,7 @@ extern "C" {
/** GPIO_EXT_PAD_COMP_FILTER_0_REG register
* Zero Detect filter Register
*/
#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_BASE + 0x5c)
#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_EXT_BASE + 0x5c)
/** GPIO_EXT_ZERO_DET_FILTER_CNT_0 : R/W; bitpos: [31:0]; default: 0;
* Zero Detect filter cycle length
*/
@@ -53,7 +54,7 @@ extern "C" {
/** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register
* Etm Config register of Channel0
*/
#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_BASE + 0x118)
#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118)
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
@@ -72,7 +73,7 @@ extern "C" {
/** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register
* Etm Config register of Channel1
*/
#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_BASE + 0x11c)
#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c)
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
@@ -91,7 +92,7 @@ extern "C" {
/** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register
* Etm Config register of Channel2
*/
#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_BASE + 0x120)
#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120)
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
@@ -110,7 +111,7 @@ extern "C" {
/** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register
* Etm Config register of Channel3
*/
#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_BASE + 0x124)
#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124)
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
@@ -129,7 +130,7 @@ extern "C" {
/** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register
* Etm Config register of Channel4
*/
#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_BASE + 0x128)
#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128)
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
@@ -148,7 +149,7 @@ extern "C" {
/** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register
* Etm Config register of Channel5
*/
#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_BASE + 0x12c)
#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c)
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
@@ -167,7 +168,7 @@ extern "C" {
/** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register
* Etm Config register of Channel6
*/
#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_BASE + 0x130)
#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130)
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
@@ -186,7 +187,7 @@ extern "C" {
/** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register
* Etm Config register of Channel7
*/
#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_BASE + 0x134)
#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134)
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
@@ -205,7 +206,7 @@ extern "C" {
/** GPIO_EXT_ETM_TASK_P0_CFG_REG register
* Etm Configure Register to decide which GPIO been chosen
*/
#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_BASE + 0x158)
#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158)
/** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
@@ -280,7 +281,7 @@ extern "C" {
/** GPIO_EXT_ETM_TASK_P1_CFG_REG register
* Etm Configure Register to decide which GPIO been chosen
*/
#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c)
/** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
@@ -355,7 +356,7 @@ extern "C" {
/** GPIO_EXT_ETM_TASK_P2_CFG_REG register
* Etm Configure Register to decide which GPIO been chosen
*/
#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_BASE + 0x160)
#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160)
/** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
@@ -430,7 +431,7 @@ extern "C" {
/** GPIO_EXT_ETM_TASK_P3_CFG_REG register
* Etm Configure Register to decide which GPIO been chosen
*/
#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_BASE + 0x164)
#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164)
/** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
@@ -505,7 +506,7 @@ extern "C" {
/** GPIO_EXT_ETM_TASK_P4_CFG_REG register
* Etm Configure Register to decide which GPIO been chosen
*/
#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_BASE + 0x168)
#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168)
/** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
@@ -580,7 +581,7 @@ extern "C" {
/** GPIO_EXT_ETM_TASK_P5_CFG_REG register
* Etm Configure Register to decide which GPIO been chosen
*/
#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x16c)
/** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
@@ -655,7 +656,7 @@ extern "C" {
/** GPIO_EXT_INT_RAW_REG register
* GPIO_EXT interrupt raw register
*/
#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_BASE + 0x1d0)
#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0x1d0)
/** GPIO_EXT_COMP_NEG_0_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt raw
*/
@@ -681,7 +682,7 @@ extern "C" {
/** GPIO_EXT_INT_ST_REG register
* GPIO_EXT interrupt masked register
*/
#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_BASE + 0x1d4)
#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0x1d4)
/** GPIO_EXT_COMP_NEG_0_INT_ST : RO; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt status
*/
@@ -707,7 +708,7 @@ extern "C" {
/** GPIO_EXT_INT_ENA_REG register
* GPIO_EXT interrupt enable register
*/
#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_BASE + 0x1d8)
#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0x1d8)
/** GPIO_EXT_COMP_NEG_0_INT_ENA : R/W; bitpos: [0]; default: 1;
* analog comparator pos edge interrupt enable
*/
@@ -733,7 +734,7 @@ extern "C" {
/** GPIO_EXT_INT_CLR_REG register
* GPIO_EXT interrupt clear register
*/
#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_BASE + 0x1dc)
#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0x1dc)
/** GPIO_EXT_COMP_NEG_0_INT_CLR : WT; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt clear
*/
@@ -759,7 +760,7 @@ extern "C" {
/** GPIO_EXT_PIN_CTRL_REG register
* Clock Output Configuration Register
*/
#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_BASE + 0x1e0)
#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_EXT_BASE + 0x1e0)
/** GPIO_EXT_CLK_OUT1 : R/W; bitpos: [4:0]; default: 0;
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
* CLK_OUT_out1 can be found in peripheral output signals.
@@ -788,7 +789,7 @@ extern "C" {
/** GPIO_EXT_VERSION_REG register
* Version Control Register
*/
#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_BASE + 0x1fc)
#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc)
/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37823120;
* Version control register.
*/