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Merge branch 'refactor/rtc_cal_clk' into 'master'

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refactor(clk): add soc_clk_calibration_clk_src_t for all targets

Closes IDF-11790

See merge request espressif/esp-idf!40737
This commit is contained in:
Song Ruo Jing
2025-07-31 19:49:17 +08:00
parent 6bd8b52ad7 48233e0e7e
commit e94d9cee7a
89 changed files with 1078 additions and 953 deletions
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19
components/esp_hw_support/port/esp32/include/soc/rtc.h
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@@ -89,14 +89,9 @@ typedef struct rtc_cpu_freq_config_s {
uint32_t freq_mhz; //!< CPU clock frequency uint32_t freq_mhz; //!< CPU clock frequency
} rtc_cpu_freq_config_t; } rtc_cpu_freq_config_t;
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256
*/ #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
typedef enum {
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -397,21 +392,21 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cal_clk slow clock to be measured * @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency, * @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out. * Q13.19 fixed point format, or 0 if calibration has timed out.
*/ */
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

2
components/esp_hw_support/port/esp32/rtc_clk_init.c
View File

@@ -150,7 +150,7 @@ static soc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
rtc_clk_8m_enable(true, true); rtc_clk_8m_enable(true, true);
} }
uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES); uint64_t cal_val = rtc_clk_cal_ratio(CLK_CAL_RC_FAST_D256, XTAL_FREQ_EST_CYCLES);
/* cal_val contains period of 8M/256 clock in XTAL clock cycles /* cal_val contains period of 8M/256 clock in XTAL clock cycles
* (shifted by RTC_CLK_CAL_FRACT bits). * (shifted by RTC_CLK_CAL_FRACT bits).
* Xtal frequency will be (cal_val * 8M / 256) / 2^19 * Xtal frequency will be (cal_val * 8M / 256) / 2^19

37
components/esp_hw_support/port/esp32/rtc_time.c
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@@ -30,37 +30,38 @@ static const char *TAG = "rtc_time";
/** /**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count. Max value is 32766. * @param slowclk_cycles number of slow clock cycles to count. Max value is 32766.
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles < 32767); assert(slowclk_cycles < 32767);
/* Enable requested clock (150k clock is always on) */
/* Enable requested clock (rtc slow clock is always on) */
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled(); bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true); rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable(); clk_ll_rc_fast_d256_digi_enable();
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
uint32_t expected_freq; uint32_t expected_freq;
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (cal_clk == RTC_CAL_32K_XTAL || if (cal_clk_sel == CLK_CAL_32K_XTAL ||
(cal_clk == RTC_CAL_RTC_MUX && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K)) { (cal_clk_sel == CLK_CAL_RTC_SLOW && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K)) {
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; /* standard 32k XTAL */ expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; /* standard 32k XTAL */
} else if (cal_clk == RTC_CAL_8MD256 || } else if (cal_clk_sel == CLK_CAL_RC_FAST_D256 ||
(cal_clk == RTC_CAL_RTC_MUX && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256)) { (cal_clk_sel == CLK_CAL_RTC_SLOW && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256)) {
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else { } else {
expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; /* 150k internal oscillator */ expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; /* 150k internal oscillator */
@@ -94,11 +95,11 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable(); clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled); rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
} }
@@ -110,10 +111,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
return REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); return REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
} }
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio; return ratio;
@@ -126,13 +127,13 @@ static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if ((cal_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }
@@ -165,7 +166,7 @@ void rtc_clk_wait_for_slow_cycle(void)
{ {
REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START); REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START);
REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY); REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, RTC_CAL_RTC_MUX); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, CLK_CAL_RTC_SLOW);
/* Request to run calibration for 0 slow clock cycles. /* Request to run calibration for 0 slow clock cycles.
* RDY bit will be set on the nearest slow clock cycle. * RDY bit will be set on the nearest slow clock cycle.
*/ */

25
components/esp_hw_support/port/esp32c2/include/soc/rtc.h
View File

@@ -155,17 +155,10 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256
*/ #define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW
typedef enum { #define RTC_CAL_INTERNAL_OSC _Pragma ("GCC warning \"'RTC_CAL_INTERNAL_OSC' macro is deprecated\"") CLK_CAL_RC_SLOW
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_OSC_SLOW = 2, //!< External 32.768 KHz CLK
// deprecated name
RTC_CAL_EXT_32K __attribute__((deprecated)) = RTC_CAL_32K_OSC_SLOW,
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -409,8 +402,6 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
*/ */
uint32_t rtc_clk_apb_freq_get(void); uint32_t rtc_clk_apb_freq_get(void);
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/** /**
* @brief Measure RTC slow clock's period, based on main XTAL frequency * @brief Measure RTC slow clock's period, based on main XTAL frequency
* *
@@ -424,21 +415,21 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cal_clk slow clock to be measured * @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency, * @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out. * Q13.19 fixed point format, or 0 if calibration has timed out.
*/ */
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

13
components/esp_hw_support/port/esp32c2/rtc_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -154,16 +154,9 @@ static void calibrate_ocode(void)
4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
5. set cpu to old-config. 5. set cpu to old-config.
*/ */
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk = RTC_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256;
}
uint64_t max_delay_time_us = 10000; uint64_t max_delay_time_us = 10000;
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); uint32_t slow_clk_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, 100);
uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
uint64_t cycle0 = rtc_time_get(); uint64_t cycle0 = rtc_time_get();
uint64_t timeout_cycle = cycle0 + max_delay_cycle; uint64_t timeout_cycle = cycle0 + max_delay_cycle;
@@ -259,7 +252,7 @@ uint32_t get_rtc_dbias_by_efuse(uint8_t dbias_scheme_ver, uint32_t dig_dbias)
static void set_rtc_dig_dbias() static void set_rtc_dig_dbias()
{ {
/* /*
1. a reasonable dig_dbias which by scaning pvt to make 120 CPU run successful stored in efuse; 1. a reasonable dig_dbias which by scanning pvt to make 120 CPU run successful stored in efuse;
2. a reasonable rtc_dbias can be calculated by a certion formula. 2. a reasonable rtc_dbias can be calculated by a certion formula.
*/ */
uint32_t rtc_dbias = 31, dig_dbias = 26; uint32_t rtc_dbias = 31, dig_dbias = 26;

44
components/esp_hw_support/port/esp32c2/rtc_time.c
View File

@@ -29,34 +29,32 @@
/** /**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count * @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
/* On ESP32-C2, choosing RTC_CAL_RTC_MUX results in calibration of if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
* the 150k RTC clock regardless of the currently selected SLOW_CLK.
* On the ESP32, it used the currently selected SLOW_CLK.
* The following code emulates ESP32 behavior:
*/
if (cal_clk == RTC_CAL_RTC_MUX) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cal_clk = RTC_CAL_32K_OSC_SLOW; cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256; cal_clk_sel = CLK_CAL_RC_FAST_D256;
} }
} }
/* Enable requested clock (150k clock is always on) */ /* Enable requested clock (150k clock is always on) */
bool dig_ext_clk_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_ext_clk_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_OSC_SLOW && !dig_ext_clk_enabled) { if (cal_clk_sel == CLK_CAL_32K_OSC_SLOW && !dig_ext_clk_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled(); bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true); rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable(); clk_ll_rc_fast_d256_digi_enable();
} }
@@ -74,17 +72,17 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
uint32_t expected_freq; uint32_t expected_freq;
if (cal_clk == RTC_CAL_32K_OSC_SLOW) { if (cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_OSC_SLOW_FREQ_APPROX; expected_freq = SOC_CLK_OSC_SLOW_FREQ_APPROX;
} else if (cal_clk == RTC_CAL_8MD256) { } else if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else { } else {
@@ -112,11 +110,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_ext_clk was originally off and enabled due to calibration, then set back to off state */ /* if dig_ext_clk was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_OSC_SLOW && !dig_ext_clk_enabled) { if (cal_clk_sel == CLK_CAL_32K_OSC_SLOW && !dig_ext_clk_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable(); clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled); rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
} }
@@ -124,10 +122,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
return cal_val; return cal_val;
} }
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio; return ratio;
@@ -140,13 +138,13 @@ static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if ((cal_clk == RTC_CAL_32K_OSC_SLOW) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if ((cal_clk_sel == CLK_CAL_32K_OSC_SLOW) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

23
components/esp_hw_support/port/esp32c3/include/soc/rtc.h
View File

@@ -157,15 +157,10 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256
*/ #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
typedef enum { #define RTC_CAL_INTERNAL_OSC _Pragma ("GCC warning \"'RTC_CAL_INTERNAL_OSC' macro is deprecated\"") CLK_CAL_RC_SLOW
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -437,8 +432,6 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
*/ */
uint32_t rtc_clk_apb_freq_get(void); uint32_t rtc_clk_apb_freq_get(void);
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/** /**
* @brief Measure RTC slow clock's period, based on main XTAL frequency * @brief Measure RTC slow clock's period, based on main XTAL frequency
* *
@@ -452,21 +445,21 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cal_clk slow clock to be measured * @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency, * @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out. * Q13.19 fixed point format, or 0 if calibration has timed out.
*/ */
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

11
components/esp_hw_support/port/esp32c3/rtc_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -190,16 +190,9 @@ static void calibrate_ocode(void)
4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
5. set cpu to old-config. 5. set cpu to old-config.
*/ */
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256;
}
uint64_t max_delay_time_us = 10000; uint64_t max_delay_time_us = 10000;
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); uint32_t slow_clk_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, 100);
uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
uint64_t cycle0 = rtc_time_get(); uint64_t cycle0 = rtc_time_get();
uint64_t timeout_cycle = cycle0 + max_delay_cycle; uint64_t timeout_cycle = cycle0 + max_delay_cycle;

45
components/esp_hw_support/port/esp32c3/rtc_time.c
View File

@@ -29,37 +29,32 @@
/** /**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calibrate
* @param slowclk_cycles number of slow clock cycles to count * @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
/* On ESP32C3, choosing RTC_CAL_RTC_MUX results in calibration of if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
* the 150k RTC clock regardless of the currently selected SLOW_CLK.
* On the ESP32, it used the currently selected SLOW_CLK.
* The following code emulates ESP32 behavior:
*/
if (cal_clk == RTC_CAL_RTC_MUX) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cal_clk = RTC_CAL_32K_XTAL; cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256; cal_clk_sel = CLK_CAL_RC_FAST_D256;
} }
} else if (cal_clk == RTC_CAL_INTERNAL_OSC) {
cal_clk = RTC_CAL_RTC_MUX;
} }
/* Enable requested clock (150k clock is always on) */ /* Enable requested clock (150k clock is always on) */
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled(); bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true); rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable(); clk_ll_rc_fast_d256_digi_enable();
} }
@@ -77,17 +72,17 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
uint32_t expected_freq; uint32_t expected_freq;
if (cal_clk == RTC_CAL_32K_XTAL) { if (cal_clk_sel == CLK_CAL_32K_XTAL) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cal_clk == RTC_CAL_8MD256) { } else if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else { } else {
@@ -115,11 +110,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable(); clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled); rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
} }
@@ -127,10 +122,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
return cal_val; return cal_val;
} }
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio; return ratio;
@@ -143,13 +138,13 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if ((cal_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

22
components/esp_hw_support/port/esp32c5/include/soc/rtc.h
View File

@@ -114,19 +114,11 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
* #define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW
* @note On ESP32C5, the enum values somehow reflects the register field values of PCR_32K_SEL. #define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW
*/ #define RTC_CAL_RC_FAST _Pragma ("GCC warning \"'RTC_CAL_RC_FAST' macro is deprecated\"") CLK_CAL_RC_FAST
typedef enum {
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
RTC_CAL_32K_XTAL = 1, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_32K_OSC_SLOW = 2, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
RTC_CAL_RC_SLOW = 3, //!< Internal 150kHz RC oscillator
RTC_CAL_RC_FAST = 4, //!< Internal 20MHz RC oscillator
RTC_CAL_INVALID_CLK, //!< Clock not available to calibrate
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -352,12 +344,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

11
components/esp_hw_support/port/esp32c5/ocode_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -38,16 +38,9 @@ static void IRAM_ATTR NOINLINE_ATTR calibrate_ocode(void)
4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
5. set cpu to old-config. 5. set cpu to old-config.
*/ */
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk = RTC_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL;
}
uint64_t max_delay_time_us = 10000; uint64_t max_delay_time_us = 10000;
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); uint32_t slow_clk_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, 100);
uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
uint64_t cycle0 = rtc_time_get(); uint64_t cycle0 = rtc_time_get();
uint64_t timeout_cycle = cycle0 + max_delay_cycle; uint64_t timeout_cycle = cycle0 + max_delay_cycle;

60
components/esp_hw_support/port/esp32c5/rtc_time.c
View File

@@ -19,44 +19,46 @@
__attribute__((unused)) static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. #define CLK_CAL_TIMEOUT_THRES(cal_clk_sel, cycles) ((cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10))
/**
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles. * clock cycles.
*
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10))
static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
if (cal_clk == RTC_CAL_RTC_MUX) { if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cal_clk = RTC_CAL_RC_SLOW; cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL; cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk = RTC_CAL_32K_OSC_SLOW; cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
} }
} }
if (cal_clk < 0 || cal_clk >= RTC_CAL_INVALID_CLK) {
ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated");
return 0;
}
/* Enable requested clock (150k clock is always on) */ /* Enable requested clock (150k clock is always on) */
// All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
// Only enable if originally was disabled, and set back to the disable state after calibration is done // Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing // If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) { if (!rc_fast_enabled) {
rtc_clk_8m_enable(true); rtc_clk_8m_enable(true);
} }
@@ -79,8 +81,8 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(PCR_CTRL_32K_CONF_REG, PCR_32K_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf(); clk_ll_rc_fast_tick_conf();
} }
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -88,11 +90,11 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk, slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk_sel, slowclk_cycles));
uint32_t expected_freq; uint32_t expected_freq;
if (cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) { if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cal_clk == RTC_CAL_RC_FAST) { } else if (cal_clk_sel == CLK_CAL_RC_FAST) {
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} else { } else {
expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
@@ -111,7 +113,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/*The Fosc CLK of calibration circuit is divided by a factor, k. /*The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to multiply the frequency of the FOSC by k times.*/ So we need to multiply the frequency of the FOSC by k times.*/
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} }
break; break;
@@ -125,11 +127,11 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
clk_ll_enable_timergroup_rtc_calibration_clock(false); clk_ll_enable_timergroup_rtc_calibration_clock(false);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) { if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable(); rtc_dig_clk8m_disable();
} }
@@ -148,19 +150,19 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
/*The Fosc CLK of calibration circuit is divided by a factor, k. /*The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to divide the calibrate cycles of the FOSC by k to So we need to divide the calibrate cycles of the FOSC by k to
avoid excessive calibration time.*/ avoid excessive calibration time.*/
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} }
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

15
components/esp_hw_support/port/esp32c6/Kconfig.rtc
View File

@@ -12,24 +12,13 @@ choice RTC_CLK_SRC
config RTC_CLK_SRC_EXT_OSC config RTC_CLK_SRC_EXT_OSC
bool "External 32 kHz oscillator at 32K_XP pin" bool "External 32 kHz oscillator at 32K_XP pin"
select ESP_SYSTEM_RTC_EXT_OSC select ESP_SYSTEM_RTC_EXT_OSC
config RTC_CLK_SRC_INT_RC32K
bool "Internal 32 kHz RC oscillator (NOT RECOMMENDED TO USE, READ DOCS FIRST)"
depends on RTC_CLK_SRC_USE_DANGEROUS_RC32K_ALLOWED
help
To be able to select this option, please select `RTC_CLK_SRC_USE_DANGEROUS_RC32K_ALLOWED` first.
This option will be removed in IDF v6.0.
endchoice endchoice
config RTC_CLK_SRC_USE_DANGEROUS_RC32K_ALLOWED
bool "Confirm to use the unrecommended 32 kHz RC oscillator (READ DOCS FIRST)"
help
Internal RC32K clock is unstable at extreme temperatures and is not recommended for use.
config RTC_CLK_CAL_CYCLES config RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration" int "Number of cycles for RTC_SLOW_CLK calibration"
default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
default 1024 if RTC_CLK_SRC_INT_RC default 1024 if RTC_CLK_SRC_INT_RC
range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
range 0 32766 if RTC_CLK_SRC_INT_RC range 0 32766 if RTC_CLK_SRC_INT_RC
help help
When the startup code initializes RTC_SLOW_CLK, it can perform When the startup code initializes RTC_SLOW_CLK, it can perform

26
components/esp_hw_support/port/esp32c6/include/soc/rtc.h
View File

@@ -120,22 +120,12 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
#define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
/** #define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_RC32K _Pragma ("GCC warning \"'RTC_CAL_RC32K' macro is deprecated\"") CLK_CAL_RC32K
* #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
* @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL #define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW
* However, this is not true on ESP32C6. The conversion to register field values is explicitly done in #define RTC_CAL_RC_FAST _Pragma ("GCC warning \"'RTC_CAL_RC_FAST' macro is deprecated\"") CLK_CAL_RC_FAST
* rtc_clk_cal_internal
*/
typedef enum {
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator
RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock
RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -381,12 +371,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

11
components/esp_hw_support/port/esp32c6/ocode_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -37,16 +37,9 @@ static void calibrate_ocode(void)
4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
5. set cpu to old-config. 5. set cpu to old-config.
*/ */
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk = RTC_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL;
}
uint64_t max_delay_time_us = 10000; uint64_t max_delay_time_us = 10000;
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); uint32_t slow_clk_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, 100);
uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
uint64_t cycle0 = rtc_time_get(); uint64_t cycle0 = rtc_time_get();
uint64_t timeout_cycle = cycle0 + max_delay_cycle; uint64_t timeout_cycle = cycle0 + max_delay_cycle;

91
components/esp_hw_support/port/esp32c6/rtc_time.c
View File

@@ -20,31 +20,10 @@
__attribute__((unused)) static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
* Slow clock calibration feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit.
*/
/* On ESP32C6, TIMG_RTC_CALI_CLK_SEL can config to 0, 1, 2, 3
* 0 or 3: calibrate RC_SLOW clock
* 1: calibrate RC_FAST clock
* 2: calibrate 32K clock, which 32k depends on reg_32k_sel: 0: Internal 32 kHz RC oscillator, 1: External 32 kHz XTAL, 2: External 32kHz clock input by lp_pad_gpio0
*/
#define TIMG_RTC_CALI_CLK_SEL_RC_SLOW 0
#define TIMG_RTC_CALI_CLK_SEL_RC_FAST 1
#define TIMG_RTC_CALI_CLK_SEL_32K 2
/** /**
* @brief Clock calibration function used by rtc_clk_cal * @brief Clock frequency calculation function used by rtc_clk_cal
* *
* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * Calculation of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles. * RTC_SLOW_CLK cycles.
* *
@@ -55,42 +34,39 @@ __attribute__((unused)) static const char *TAG = "rtc_time";
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit. * enabled using TIMG_RTC_CALI_START bit.
* *
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count * @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
uint32_t cali_clk_sel = 0; if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
soc_rtc_slow_clk_src_t old_32k_cal_clk_sel = clk_ll_32k_calibration_get_target(); if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
if (cal_clk == RTC_CAL_RTC_MUX) { cal_clk_sel = CLK_CAL_RC_SLOW;
cal_clk = (rtc_cal_sel_t)slow_clk_src; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
cal_clk_sel = CLK_CAL_RC32K;
}
} }
if (cal_clk == RTC_CAL_RC_FAST) {
cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST;
} else if (cal_clk == RTC_CAL_RC_SLOW) {
cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW;
} else {
cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K;
clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk);
}
/* Enable requested clock (150k clock is always on) */ /* Enable requested clock (150k clock is always on) */
// All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
// Only enable if originally was disabled, and set back to the disable state after calibration is done // Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing // If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) { if (!rc_fast_enabled) {
rtc_clk_8m_enable(true); rtc_clk_8m_enable(true);
} }
@@ -101,7 +77,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
bool rc32k_enabled = clk_ll_rc32k_is_enabled(); bool rc32k_enabled = clk_ll_rc32k_is_enabled();
bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
if (cal_clk == RTC_CAL_RC32K) { if (cal_clk_sel == CLK_CAL_RC32K) {
if (!rc32k_enabled) { if (!rc32k_enabled) {
rtc_clk_rc32k_enable(true); rtc_clk_rc32k_enable(true);
} }
@@ -124,8 +100,8 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel); clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf(); clk_ll_rc_fast_tick_conf();
} }
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -134,10 +110,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
uint32_t expected_freq; uint32_t expected_freq;
if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_32K) { if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW || cal_clk_sel == CLK_CAL_RC32K) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) { } else if (cal_clk_sel == CLK_CAL_RC_FAST) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX; expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
@@ -165,7 +141,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
And the 32-divider belongs to REF_TICK module, so we need to enable its clock during And the 32-divider belongs to REF_TICK module, so we need to enable its clock during
calibration. */ calibration. */
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
} }
@@ -180,11 +156,11 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) { if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable(); rtc_dig_clk8m_disable();
} }
@@ -193,7 +169,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
} }
if (cal_clk == RTC_CAL_RC32K) { if (cal_clk_sel == CLK_CAL_RC32K) {
if (!dig_rc32k_enabled) { if (!dig_rc32k_enabled) {
clk_ll_rc32k_digi_disable(); clk_ll_rc32k_digi_disable();
} }
@@ -202,11 +178,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
} }
// Always set back the calibration 32kHz clock selection
if (old_32k_cal_clk_sel != SOC_RTC_SLOW_CLK_SRC_INVALID) {
clk_ll_32k_calibration_set_target(old_32k_cal_clk_sel);
}
return cal_val; return cal_val;
} }
@@ -217,7 +188,7 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
@@ -226,15 +197,15 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
avoid excessive calibration time.*/ avoid excessive calibration time.*/
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
} }
} }
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

22
components/esp_hw_support/port/esp32c61/include/soc/rtc.h
View File

@@ -114,19 +114,11 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
* #define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW
* @note On ESP32C61, the enum values somehow reflects the register field values of PCR_32K_SEL. #define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW
*/ #define RTC_CAL_RC_FAST _Pragma ("GCC warning \"'RTC_CAL_RC_FAST' macro is deprecated\"") CLK_CAL_RC_FAST
typedef enum {
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
RTC_CAL_32K_XTAL = 1, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_32K_OSC_SLOW = 2, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
RTC_CAL_RC_SLOW = 3, //!< Internal 150kHz RC oscillator
RTC_CAL_RC_FAST = 4, //!< Internal 20MHz RC oscillator
RTC_CAL_INVALID_CLK, //!< Clock not available to calibrate
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -350,12 +342,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

11
components/esp_hw_support/port/esp32c61/ocode_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -37,16 +37,9 @@ static void IRAM_ATTR NOINLINE_ATTR calibrate_ocode(void)
4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
5. set cpu to old-config. 5. set cpu to old-config.
*/ */
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk = RTC_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL;
}
uint64_t max_delay_time_us = 10000; uint64_t max_delay_time_us = 10000;
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); uint32_t slow_clk_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, 100);
uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
uint64_t cycle0 = rtc_time_get(); uint64_t cycle0 = rtc_time_get();
uint64_t timeout_cycle = cycle0 + max_delay_cycle; uint64_t timeout_cycle = cycle0 + max_delay_cycle;

60
components/esp_hw_support/port/esp32c61/rtc_time.c
View File

@@ -18,44 +18,46 @@
__attribute__((unused)) static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. #define CLK_CAL_TIMEOUT_THRES(cal_clk_sel, cycles) ((cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10))
/**
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles. * clock cycles.
*
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10))
static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
if (cal_clk == RTC_CAL_RTC_MUX) { if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cal_clk = RTC_CAL_RC_SLOW; cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL; cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk = RTC_CAL_32K_OSC_SLOW; cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
} }
} }
if (cal_clk < 0 || cal_clk >= RTC_CAL_INVALID_CLK) {
ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated");
return 0;
}
/* Enable requested clock (150k clock is always on) */ /* Enable requested clock (150k clock is always on) */
// All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
// Only enable if originally was disabled, and set back to the disable state after calibration is done // Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing // If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) { if (!rc_fast_enabled) {
rtc_clk_8m_enable(true); rtc_clk_8m_enable(true);
} }
@@ -78,8 +80,8 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(PCR_CTRL_32K_CONF_REG, PCR_32K_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf(); clk_ll_rc_fast_tick_conf();
} }
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -87,11 +89,11 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk, slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk_sel, slowclk_cycles));
uint32_t expected_freq; uint32_t expected_freq;
if (cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) { if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cal_clk == RTC_CAL_RC_FAST) { } else if (cal_clk_sel == CLK_CAL_RC_FAST) {
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} else { } else {
expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
@@ -110,7 +112,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/*The Fosc CLK of calibration circuit is divided by a factor, k. /*The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to multiply the frequency of the FOSC by k times.*/ So we need to multiply the frequency of the FOSC by k times.*/
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} }
break; break;
@@ -123,11 +125,11 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) { if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable(); rtc_dig_clk8m_disable();
} }
@@ -146,20 +148,20 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
/*The Fosc CLK of calibration circuit is divided by a factor, k. /*The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to divide the calibrate cycles of the FOSC by k to So we need to divide the calibrate cycles of the FOSC by k to
avoid excessive calibration time.*/ avoid excessive calibration time.*/
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} }
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

25
components/esp_hw_support/port/esp32h2/include/soc/rtc.h
View File

@@ -123,21 +123,12 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW
* #define RTC_CAL_RC32K _Pragma ("GCC warning \"'RTC_CAL_RC32K' macro is deprecated\"") CLK_CAL_RC32K
* @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
* However, this is not true on ESP32H2. The conversion to register field values is explicitly done in #define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW
* rtc_clk_cal_internal #define RTC_CAL_RC_FAST _Pragma ("GCC warning \"'RTC_CAL_RC_FAST' macro is deprecated\"") CLK_CAL_RC_FAST
*/
typedef enum {
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator
RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock
RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpiox, as one type of 32k clock
RTC_CAL_RC_FAST //!< Internal 8MHz RC oscillator
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -379,12 +370,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* 32k XTAL is being calibrated, but the oscillator has not started up (due to * 32k XTAL is being calibrated, but the oscillator has not started up (due to
* incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

91
components/esp_hw_support/port/esp32h2/rtc_time.c
View File

@@ -20,31 +20,10 @@
__attribute__((unused)) static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
* Slow clock calibration feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit.
*/
/* On ESP32H2, TIMG_RTC_CALI_CLK_SEL can config to 0, 1, 2, 3
* 0 or 3: calibrate RC_SLOW clock
* 1: calibrate RC_FAST clock
* 2: calibrate 32K clock, which 32k depends on reg_32k_sel: 0: Internal 32 kHz RC oscillator, 1: External 32 kHz XTAL, 2: External 32kHz clock input by gpio13
*/
#define TIMG_RTC_CALI_CLK_SEL_RC_SLOW 0
#define TIMG_RTC_CALI_CLK_SEL_RC_FAST 1
#define TIMG_RTC_CALI_CLK_SEL_32K 2
/** /**
* @brief Clock calibration function used by rtc_clk_cal * @brief Clock frequency calculation function used by rtc_clk_cal
* *
* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * Calculation of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles. * RTC_SLOW_CLK cycles.
* *
@@ -55,42 +34,39 @@ __attribute__((unused)) static const char *TAG = "rtc_time";
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit. * enabled using TIMG_RTC_CALI_START bit.
* *
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count * @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
uint32_t cali_clk_sel = 0; if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
soc_rtc_slow_clk_src_t old_32k_cal_clk_sel = clk_ll_32k_calibration_get_target(); if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
if (cal_clk == RTC_CAL_RTC_MUX) { cal_clk_sel = CLK_CAL_RC_SLOW;
cal_clk = (rtc_cal_sel_t)slow_clk_src; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
cal_clk_sel = CLK_CAL_RC32K;
}
} }
if (cal_clk == RTC_CAL_RC_FAST) {
cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST;
} else if (cal_clk == RTC_CAL_RC_SLOW) {
cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW;
} else {
cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K;
clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk);
}
/* Enable requested clock (150k clock is always on) */ /* Enable requested clock (150k clock is always on) */
// All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
// Only enable if originally was disabled, and set back to the disable state after calibration is done // Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing // If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) { if (!rc_fast_enabled) {
rtc_clk_8m_enable(true); rtc_clk_8m_enable(true);
} }
@@ -101,7 +77,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
bool rc32k_enabled = clk_ll_rc32k_is_enabled(); bool rc32k_enabled = clk_ll_rc32k_is_enabled();
bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
if (cal_clk == RTC_CAL_RC32K) { if (cal_clk_sel == CLK_CAL_RC32K) {
if (!rc32k_enabled) { if (!rc32k_enabled) {
rtc_clk_rc32k_enable(true); rtc_clk_rc32k_enable(true);
} }
@@ -124,8 +100,8 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel); clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf(); clk_ll_rc_fast_tick_conf();
} }
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -134,10 +110,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
uint32_t expected_freq; uint32_t expected_freq;
if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_32K) { if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW || cal_clk_sel == CLK_CAL_RC32K) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) { } else if (cal_clk_sel == CLK_CAL_RC_FAST) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX; expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
@@ -165,7 +141,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
And the 32-divider belongs to REF_TICK module, so we need to enable its clock during And the 32-divider belongs to REF_TICK module, so we need to enable its clock during
calibration. */ calibration. */
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
} }
@@ -180,11 +156,11 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) { if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable(); rtc_dig_clk8m_disable();
} }
@@ -193,7 +169,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
} }
if (cal_clk == RTC_CAL_RC32K) { if (cal_clk_sel == CLK_CAL_RC32K) {
if (!dig_rc32k_enabled) { if (!dig_rc32k_enabled) {
clk_ll_rc32k_digi_disable(); clk_ll_rc32k_digi_disable();
} }
@@ -202,11 +178,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
} }
// Always set back the calibration 32kHz clock selection
if (old_32k_cal_clk_sel != SOC_RTC_SLOW_CLK_SRC_INVALID) {
clk_ll_32k_calibration_set_target(old_32k_cal_clk_sel);
}
return cal_val; return cal_val;
} }
@@ -217,7 +188,7 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
@@ -226,15 +197,15 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
avoid excessive calibration time.*/ avoid excessive calibration time.*/
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
} }
} }
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

18
components/esp_hw_support/port/esp32h21/include/soc/rtc.h
View File

@@ -105,20 +105,6 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
/**
* @brief Clock source to be calibrated using rtc_clk_cal function
*
* @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL
* However, this is not true on ESP32H21. The conversion to register field values is explicitly done internally
*/
typedef enum {
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
RTC_CAL_RC_SLOW = CLK_CAL_RC_SLOW, //!< Internal 600kHz RC oscillator
RTC_CAL_32K_XTAL = CLK_CAL_32K_XTAL, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_32K_OSC_SLOW = CLK_CAL_32K_OSC_SLOW, //!< External slow clock signal input by gpio11, as one type of 32k clock
RTC_CAL_RC_FAST = CLK_CAL_RC_FAST, //!< Internal 20MHz RC oscillator
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
*/ */
@@ -328,12 +314,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

57
components/esp_hw_support/port/esp32h21/rtc_time.c
View File

@@ -18,31 +18,38 @@
__attribute__((unused)) static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*/
#define RTC_SLOW_CLK_600K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) #define RTC_SLOW_CLK_600K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value #define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) /**
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
bool is_cal_clk_rtc_slow = false;
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
soc_clk_calibration_clk_src_t cali_clk_sel = (soc_clk_calibration_clk_src_t)cal_clk; if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk == RTC_CAL_RTC_MUX) { is_cal_clk_rtc_slow = true;
switch (slow_clk_src) { switch (slow_clk_src) {
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4: case SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4:
cali_clk_sel = CLK_CAL_RC_SLOW; cal_clk_sel = CLK_CAL_RC_SLOW;
break; break;
case SOC_RTC_SLOW_CLK_SRC_XTAL32K: case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
cali_clk_sel = CLK_CAL_32K_XTAL; cal_clk_sel = CLK_CAL_32K_XTAL;
break; break;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
cali_clk_sel = CLK_CAL_32K_OSC_SLOW; cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
break; break;
default: default:
ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated"); ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated");
@@ -55,13 +62,13 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
// Only enable if originally was disabled, and set back to the disable state after calibration is done // Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing // If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) { if (!rc_fast_enabled) {
rtc_clk_8m_enable(true); rtc_clk_8m_enable(true);
} }
@@ -84,8 +91,8 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
/* Prepare calibration */ /* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel); clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cali_clk_sel == CLK_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf(); clk_ll_rc_fast_tick_conf();
} }
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -94,10 +101,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
uint32_t expected_freq; uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW) { if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST) { } else if (cal_clk_sel == CLK_CAL_RC_FAST) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} else { } else {
@@ -118,7 +125,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/* The Fosc CLK of calibration circuit is divided by a factor, k. /* The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to multiply the frequency of the FOSC by k times. */ So we need to multiply the frequency of the FOSC by k times. */
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} }
break; break;
@@ -131,11 +138,11 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) { if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable(); rtc_dig_clk8m_disable();
} }
@@ -144,7 +151,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
} }
if (cal_clk == RTC_CAL_RTC_MUX && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4) { if (is_cal_clk_rtc_slow && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4) {
// calibration was done on RC_SLOW clock, but rtc_slow_clk src is RC_SLOW_D4, so we need to multiply the cal_val by 4 // calibration was done on RC_SLOW clock, but rtc_slow_clk src is RC_SLOW_D4, so we need to multiply the cal_val by 4
cal_val *= 4; cal_val *= 4;
} }
@@ -159,20 +166,20 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
/* The Fosc CLK of calibration circuit is divided by a factor, k. /* The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to divide the calibrate cycles of the FOSC by k to So we need to divide the calibrate cycles of the FOSC by k to
avoid excessive calibration time. */ avoid excessive calibration time. */
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} }
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

18
components/esp_hw_support/port/esp32h4/include/soc/rtc.h
View File

@@ -105,20 +105,6 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
/**
* @brief Clock source to be calibrated using rtc_clk_cal function
*
* @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL
* However, this is not true on ESP32H4. The conversion to register field values is explicitly done internally
*/
typedef enum {
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
RTC_CAL_RC_SLOW = CLK_CAL_RC_SLOW, //!< Internal 600kHz RC oscillator
RTC_CAL_32K_XTAL = CLK_CAL_32K_XTAL, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_32K_OSC_SLOW = CLK_CAL_32K_OSC_SLOW, //!< External slow clock signal input by gpio5, as one type of 32k clock
RTC_CAL_RC_FAST = CLK_CAL_RC_FAST, //!< Internal 20MHz RC oscillator
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
*/ */
@@ -341,12 +327,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

65
components/esp_hw_support/port/esp32h4/rtc_time.c
View File

@@ -19,29 +19,41 @@ static const char *TAG = "rtc_time";
#define RTC_SLOW_CLK_600K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) #define RTC_SLOW_CLK_600K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value #define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
// Calibration can only be performed on relatively slow speed clock signal. Therefore, for high-speed clocks, // Calibration can only be performed on relatively slow speed clock signal. Therefore, for high-speed clocks,
// calibration is performed on their DIV_CLKs. The divider is configurable. We set: // calibration is performed on their DIV_CLKs. The divider is configurable. We set:
#define CLK_CAL_DIV_VAL(cal_clk) \ #define CLK_CAL_DIV_VAL(cal_clk_sel) \
((cal_clk == RTC_CAL_RC_FAST) ? 32 : 1) ((cal_clk_sel == CLK_CAL_RC_FAST) ? 32 : 1)
static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) /**
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
bool is_cal_clk_rtc_slow = false;
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
soc_clk_calibration_clk_src_t cali_clk_sel = (soc_clk_calibration_clk_src_t)cal_clk; if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk == RTC_CAL_RTC_MUX) { is_cal_clk_rtc_slow = true;
switch (slow_clk_src) { switch (slow_clk_src) {
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4: case SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4:
cali_clk_sel = CLK_CAL_RC_SLOW; cal_clk_sel = CLK_CAL_RC_SLOW;
break; break;
case SOC_RTC_SLOW_CLK_SRC_XTAL32K: case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
cali_clk_sel = CLK_CAL_32K_XTAL; cal_clk_sel = CLK_CAL_32K_XTAL;
break; break;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
cali_clk_sel = CLK_CAL_32K_OSC_SLOW; cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
break; break;
default: default:
ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated"); ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated");
@@ -49,18 +61,23 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
} }
if (cal_clk_sel != CLK_CAL_RC_SLOW && cal_clk_sel != CLK_CAL_32K_XTAL && cal_clk_sel != CLK_CAL_32K_OSC_SLOW && cal_clk_sel != CLK_CAL_RC_FAST) {
ESP_EARLY_LOGE(TAG, "calibration not yet supported for this clock");
return 0;
}
/* Enable requested clock (rc_slow clock is always on) */ /* Enable requested clock (rc_slow clock is always on) */
// All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
// Only enable if originally was disabled, and set back to the disable state after calibration is done // Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing // If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) { if (!rc_fast_enabled) {
rtc_clk_8m_enable(true); rtc_clk_8m_enable(true);
} }
@@ -83,19 +100,19 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
/* Prepare calibration */ /* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel); clk_ll_freq_calulation_set_target(cal_clk_sel);
uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cal_clk); uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cal_clk_sel);
clk_ll_calibration_set_divider(clk_cal_divider); clk_ll_freq_calculation_set_divider(clk_cal_divider);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
uint32_t expected_freq; uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW) { if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST) { } else if (cal_clk_sel == CLK_CAL_RC_FAST) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX; expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
} else { } else {
@@ -123,14 +140,14 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
} }
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
clk_ll_calibration_set_divider(1); clk_ll_freq_calculation_set_divider(1);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) { if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable(); rtc_dig_clk8m_disable();
} }
@@ -139,7 +156,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
} }
} }
if (cal_clk == RTC_CAL_RTC_MUX && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4) { if (is_cal_clk_rtc_slow && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4) {
// calibration was done on RC_SLOW clock, but rtc_slow_clk src is RC_SLOW_D4, so we need to multiply the cal_val by 4 // calibration was done on RC_SLOW clock, but rtc_slow_clk src is RC_SLOW_D4, so we need to multiply the cal_val by 4
cal_val *= 4; cal_val *= 4;
} }
@@ -154,14 +171,14 @@ static bool rtc_clk_cal_32k_valid(soc_xtal_freq_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
slowclk_cycles /= (cal_clk == RTC_CAL_RTC_MUX) ? 1 : CLK_CAL_DIV_VAL(cal_clk); slowclk_cycles /= (cal_clk_sel == CLK_CAL_RTC_SLOW) ? 1 : CLK_CAL_DIV_VAL(cal_clk_sel);
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

58
components/esp_hw_support/port/esp32p4/include/soc/rtc.h
View File

@@ -149,27 +149,19 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_MPLL _Pragma ("GCC warning \"'RTC_CAL_MPLL' macro is deprecated\"") CLK_CAL_MPLL
* #define RTC_CAL_SPLL _Pragma ("GCC warning \"'RTC_CAL_SPLL' macro is deprecated\"") CLK_CAL_SPLL
* @note On ESP32P4, the enum values somehow reflects the register field values of HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL. #define RTC_CAL_CPLL _Pragma ("GCC warning \"'RTC_CAL_CPLL' macro is deprecated\"") CLK_CAL_CPLL
*/ #define RTC_CAL_APLL _Pragma ("GCC warning \"'RTC_CAL_APLL' macro is deprecated\"") CLK_CAL_APLL
typedef enum { #define RTC_CAL_SDIO_PLL0 _Pragma ("GCC warning \"'RTC_CAL_SDIO_PLL0' macro is deprecated\"") CLK_CAL_SDIO_PLL0
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK #define RTC_CAL_SDIO_PLL1 _Pragma ("GCC warning \"'RTC_CAL_SDIO_PLL1' macro is deprecated\"") CLK_CAL_SDIO_PLL1
RTC_CAL_MPLL = 0, //!< 500MHz MSPI_PLL_CLK #define RTC_CAL_SDIO_PLL2 _Pragma ("GCC warning \"'RTC_CAL_SDIO_PLL2' macro is deprecated\"") CLK_CAL_SDIO_PLL2
RTC_CAL_SPLL = 1, //!< 480MHz SYS_PLL_CLK #define RTC_CAL_RC_FAST _Pragma ("GCC warning \"'RTC_CAL_RC_FAST' macro is deprecated\"") CLK_CAL_RC_FAST
RTC_CAL_CPLL = 2, //!< 400MHz CPU_PLL_CLK #define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW
RTC_CAL_APLL = 3, //!< AUDIO_PLL_CLK #define RTC_CAL_RC32K _Pragma ("GCC warning \"'RTC_CAL_RC32K' macro is deprecated\"") CLK_CAL_RC32K
RTC_CAL_SDIO_PLL0 = 4, //!< SDIO_PLL0_CLK #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
RTC_CAL_SDIO_PLL1 = 5, //!< SDIO_PLL1_CLK #define RTC_CAL_LP_PLL _Pragma ("GCC warning \"'RTC_CAL_LP_PLL' macro is deprecated\"") CLK_CAL_LP_PLL
RTC_CAL_SDIO_PLL2 = 6, //!< SDIO_PLL2_CLK
RTC_CAL_RC_FAST = 7, //!< Internal 20MHz RC oscillator
RTC_CAL_RC_SLOW = 8, //!< Internal 150kHz RC oscillator
RTC_CAL_RC32K = 9, //!< Internal 32kHz RC oscillator, as one type of 32k clock
RTC_CAL_32K_XTAL = 10, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_LP_PLL = 11, //!< 8MHz LP_PLL_CLK
RTC_CAL_INVALID_CLK, //!< Clock not available to calibrate
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -391,26 +383,6 @@ void rtc_clk_cpu_freq_set_xtal(void);
*/ */
uint32_t rtc_clk_apb_freq_get(void); uint32_t rtc_clk_apb_freq_get(void);
/**
* @brief Clock calibration function used by rtc_clk_cal
*
* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
* Slow clock calibration feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit.
*
* @param cal_clk which clock to calibrate
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/** /**
* @brief Measure RTC slow clock's period, based on main XTAL frequency * @brief Measure RTC slow clock's period, based on main XTAL frequency
* *
@@ -424,12 +396,12 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

102
components/esp_hw_support/port/esp32p4/rtc_time.c
View File

@@ -18,67 +18,69 @@
__attribute__((unused)) static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of clock frequency is performed using a special feature of TIMG0. #define CLK_CAL_TIMEOUT_THRES(cal_clk_sel, cycles) ((cal_clk_sel == CLK_CAL_RC32K || cal_clk_sel == CLK_CAL_32K_XTAL) ? (cycles << 12) : (cycles << 10))
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*/
#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL) ? (cycles << 12) : (cycles << 10)) // Calculation can only be performed on relatively slow speed clock signal. Therefore, for high-speed clocks,
// calculation is performed on their DIV_CLKs. The divider is configurable. We set:
// Calibration can only be performed on relatively slow speed clock signal. Therefore, for high-speed clocks, #define CLK_CAL_DIV_VAL(cal_clk_sel) \
// calibration is performed on their DIV_CLKs. The divider is configurable. We set: ((cal_clk_sel == CLK_CAL_RC_SLOW || cal_clk_sel == CLK_CAL_RC32K || cal_clk_sel == CLK_CAL_32K_XTAL) ? 1 : \
#define CLK_CAL_DIV_VAL(cal_clk) \ (cal_clk_sel == CLK_CAL_LP_PLL) ? 25 : \
((cal_clk == RTC_CAL_RC_SLOW || cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL) ? 1 : \ (cal_clk_sel == CLK_CAL_RC_FAST) ? 50 : \
(cal_clk == RTC_CAL_LP_PLL) ? 25 : \ (cal_clk_sel == CLK_CAL_APLL) ? 200 : \
(cal_clk == RTC_CAL_RC_FAST) ? 50 : \
(cal_clk == RTC_CAL_APLL) ? 200 : \
4000) 4000)
// CLK_CAL_FREQ_APPROX = CLK_FREQ_APPROX / CLK_CAL_DIV_VAL // CLK_CAL_FREQ_APPROX = CLK_FREQ_APPROX / CLK_CAL_DIV_VAL
#define CLK_CAL_FREQ_APPROX(cal_clk) \ #define CLK_CAL_FREQ_APPROX(cal_clk_sel) \
((cal_clk == RTC_CAL_MPLL) ? (CLK_LL_PLL_500M_FREQ_MHZ * MHZ / 4000) : \ ((cal_clk_sel == CLK_CAL_MPLL) ? (CLK_LL_PLL_500M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk == RTC_CAL_SPLL) ? (CLK_LL_PLL_480M_FREQ_MHZ * MHZ / 4000) : \ (cal_clk_sel == CLK_CAL_SPLL) ? (CLK_LL_PLL_480M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk == RTC_CAL_CPLL) ? (CLK_LL_PLL_400M_FREQ_MHZ * MHZ / 4000) : \ (cal_clk_sel == CLK_CAL_CPLL) ? (CLK_LL_PLL_400M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk == RTC_CAL_APLL) ? (105 * MHZ / 200) : \ (cal_clk_sel == CLK_CAL_APLL) ? (105 * MHZ / 200) : \
(cal_clk == RTC_CAL_SDIO_PLL0 || cal_clk == RTC_CAL_SDIO_PLL1 || cal_clk == RTC_CAL_SDIO_PLL2) ? (200 * MHZ / 4000) : \ (cal_clk_sel == CLK_CAL_SDIO_PLL0 || cal_clk_sel == CLK_CAL_SDIO_PLL1 || cal_clk_sel == CLK_CAL_SDIO_PLL2) ? (200 * MHZ / 4000) : \
(cal_clk == RTC_CAL_RC_FAST) ? (SOC_CLK_RC_FAST_FREQ_APPROX / 50) : \ (cal_clk_sel == CLK_CAL_RC_FAST) ? (SOC_CLK_RC_FAST_FREQ_APPROX / 50) : \
(cal_clk == RTC_CAL_RC_SLOW) ? (SOC_CLK_RC_SLOW_FREQ_APPROX) : \ (cal_clk_sel == CLK_CAL_RC_SLOW) ? (SOC_CLK_RC_SLOW_FREQ_APPROX) : \
(cal_clk == RTC_CAL_RC32K) ? (SOC_CLK_RC32K_FREQ_APPROX) : \ (cal_clk_sel == CLK_CAL_RC32K) ? (SOC_CLK_RC32K_FREQ_APPROX) : \
(cal_clk == RTC_CAL_32K_XTAL) ? (SOC_CLK_XTAL32K_FREQ_APPROX) : \ (cal_clk_sel == CLK_CAL_32K_XTAL) ? (SOC_CLK_XTAL32K_FREQ_APPROX) : \
(cal_clk == RTC_CAL_LP_PLL) ? (CLK_LL_PLL_8M_FREQ_MHZ * MHZ / 25) : \ (cal_clk_sel == CLK_CAL_LP_PLL) ? (CLK_LL_PLL_8M_FREQ_MHZ * MHZ / 25) : \
0) 0)
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) /**
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
if (cal_clk == RTC_CAL_RTC_MUX) { if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cal_clk = RTC_CAL_RC_SLOW; cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL; cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
cal_clk = RTC_CAL_RC32K; cal_clk_sel = CLK_CAL_RC32K;
} }
} }
if (cal_clk < 0 || cal_clk >= RTC_CAL_INVALID_CLK) {
ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated");
return 0;
}
/* Enable requested clock (some clocks are always on) */ /* Enable requested clock (some clocks are always on) */
// All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
// Only enable if originally was disabled, and set back to the disable state after calibration is done // Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing // If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) { if (!rc_fast_enabled) {
rtc_clk_8m_enable(true); rtc_clk_8m_enable(true);
} }
@@ -89,7 +91,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
bool rc32k_enabled = clk_ll_rc32k_is_enabled(); bool rc32k_enabled = clk_ll_rc32k_is_enabled();
bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
if (cal_clk == RTC_CAL_RC32K) { if (cal_clk_sel == CLK_CAL_RC32K) {
if (!rc32k_enabled) { if (!rc32k_enabled) {
rtc_clk_rc32k_enable(true); rtc_clk_rc32k_enable(true);
} }
@@ -112,16 +114,16 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(HP_SYS_CLKRST_PERI_CLK_CTRL21_REG, HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cal_clk); uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cal_clk_sel);
REG_SET_FIELD(HP_SYS_CLKRST_PERI_CLK_CTRL21_REG, HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM, clk_cal_divider - 1); clk_ll_freq_calculation_set_divider(clk_cal_divider);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk, slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk_sel, slowclk_cycles));
uint32_t expected_freq = CLK_CAL_FREQ_APPROX(cal_clk); uint32_t expected_freq = CLK_CAL_FREQ_APPROX(cal_clk_sel);
assert(expected_freq); assert(expected_freq);
uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
/* Start calibration */ /* Start calibration */
@@ -143,14 +145,14 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
} }
} }
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL21_REG, HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_M); clk_ll_freq_calculation_set_divider(1);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_RC_FAST) { if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) { if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable(); rtc_dig_clk8m_disable();
} }
@@ -159,7 +161,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
} }
} }
if (cal_clk == RTC_CAL_RC32K) { if (cal_clk_sel == CLK_CAL_RC32K) {
if (!dig_rc32k_enabled) { if (!dig_rc32k_enabled) {
clk_ll_rc32k_digi_disable(); clk_ll_rc32k_digi_disable();
} }
@@ -178,14 +180,14 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
slowclk_cycles /= (cal_clk == RTC_CAL_RTC_MUX) ? 1 : CLK_CAL_DIV_VAL(cal_clk); slowclk_cycles /= (cal_clk_sel == CLK_CAL_RTC_SLOW) ? 1 : CLK_CAL_DIV_VAL(cal_clk_sel);
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

27
components/esp_hw_support/port/esp32s2/include/soc/rtc.h
View File

@@ -159,15 +159,10 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256
*/ #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
typedef enum { #define RTC_CAL_INTERNAL_OSC _Pragma ("GCC warning \"'RTC_CAL_INTERNAL_OSC' macro is deprecated\"") CLK_CAL_RC_SLOW
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -470,8 +465,6 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
*/ */
uint32_t rtc_clk_apb_freq_get(void); uint32_t rtc_clk_apb_freq_get(void);
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, uint32_t cal_mode);
/** /**
* @brief Measure RTC slow clock's period, based on main XTAL frequency * @brief Measure RTC slow clock's period, based on main XTAL frequency
* *
@@ -485,21 +478,21 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cal_clk slow clock to be measured * @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency, * @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out. * Q13.19 fixed point format, or 0 if calibration has timed out.
*/ */
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
@@ -848,10 +841,10 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
/** /**
* Using valid hardware calibration value to calibrate slowclk * Using valid hardware calibration value to calibrate slowclk
* If there is no hardware calibration in process, start hardware calibration and wait for calibration finished * If there is no hardware calibration in process, start hardware calibration and wait for calibration finished
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slowclk_cycles if no hardware calibration in process, use this amount of slow cycles to calibrate slowclk. * @param slowclk_cycles if no hardware calibration in process, use this amount of slow cycles to calibrate slowclk.
*/ */
uint32_t rtc_clk_cal_cycling(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); uint32_t rtc_clk_cal_cycling(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles);
// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- // -------------------------- CLOCK TREE DEFS ALIAS ----------------------------

11
components/esp_hw_support/port/esp32s2/rtc_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -255,16 +255,9 @@ static void calibrate_ocode(void)
4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
5. set cpu to old-config. 5. set cpu to old-config.
*/ */
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256;
}
uint64_t max_delay_time_us = 10000; uint64_t max_delay_time_us = 10000;
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); uint32_t slow_clk_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, 100);
uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
uint64_t cycle0 = rtc_time_get(); uint64_t cycle0 = rtc_time_get();
uint64_t timeout_cycle = cycle0 + max_delay_cycle; uint64_t timeout_cycle = cycle0 + max_delay_cycle;

72
components/esp_hw_support/port/esp32s2/rtc_time.c
View File

@@ -14,11 +14,11 @@
#include "soc/timer_group_reg.h" #include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. /* Calculation of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles. * RTC_SLOW_CLK cycles.
* *
* Slow clock calibration feature has two modes of operation: one-off and cycling. * Slow clock frequency calculation feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
@@ -28,11 +28,11 @@
/** /**
* @brief One-off clock calibration function used by rtc_clk_cal_internal * @brief One-off clock calibration function used by rtc_clk_cal_internal
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count * @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
static uint32_t rtc_clk_cal_internal_oneoff(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) static uint32_t rtc_clk_cal_internal_oneoff(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
/* There may be another calibration process already running during we call this function, /* There may be another calibration process already running during we call this function,
* so we should wait the last process is done. * so we should wait the last process is done.
@@ -48,17 +48,17 @@ static uint32_t rtc_clk_cal_internal_oneoff(rtc_cal_sel_t cal_clk, uint32_t slow
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
uint32_t expected_freq; uint32_t expected_freq;
if (cal_clk == RTC_CAL_32K_XTAL) { if (cal_clk_sel == CLK_CAL_32K_XTAL) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cal_clk == RTC_CAL_8MD256) { } else if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else { } else {
@@ -89,20 +89,19 @@ static uint32_t rtc_clk_cal_internal_oneoff(rtc_cal_sel_t cal_clk, uint32_t slow
/** /**
* @brief Cycling clock calibration function used by rtc_clk_cal_internal * @brief Cycling clock calibration function used by rtc_clk_cal_internal
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count * @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
static uint32_t rtc_clk_cal_internal_cycling(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) static uint32_t rtc_clk_cal_internal_cycling(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
/* Get which slowclk is in calibration and max cali cycles */ /* Get which slowclk is in calibration and max cali cycles */
rtc_cal_sel_t in_calibration_clk; soc_clk_freq_calculation_src_t in_calibration_clk = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL);
in_calibration_clk = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL);
uint32_t cali_slowclk_cycles = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX); uint32_t cali_slowclk_cycles = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX);
/* If no calibration in process or calibration period equal to 0, use slowclk_cycles cycles to calibrate slowclk */ /* If no calibration in process or calibration period equal to 0, use slowclk_cycles cycles to calibrate slowclk */
if (cali_slowclk_cycles == 0 || !GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING) || in_calibration_clk != cal_clk) { if (cali_slowclk_cycles == 0 || !GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING) || in_calibration_clk != cal_clk_sel) {
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
cali_slowclk_cycles = slowclk_cycles; cali_slowclk_cycles = slowclk_cycles;
@@ -133,56 +132,51 @@ static uint32_t rtc_clk_xtal_to_slowclk(uint64_t xtal_cycles, uint32_t slowclk_c
/** /**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count * @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, uint32_t cal_mode) static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles, uint32_t cal_mode)
{ {
/* On ESP32S2, choosing RTC_CAL_RTC_MUX results in calibration of if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
* the 90k RTC clock regardless of the currently selected SLOW_CLK.
* On the ESP32, it used the currently selected SLOW_CLK.
* The following code emulates ESP32 behavior:
*/
if (cal_clk == RTC_CAL_RTC_MUX) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cal_clk = RTC_CAL_32K_XTAL; cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256; cal_clk_sel = CLK_CAL_RC_FAST_D256;
} }
} else if (cal_clk == RTC_CAL_INTERNAL_OSC) {
cal_clk = RTC_CAL_RTC_MUX;
} }
/* Enable requested clock (90k clock is always on) */ /* Enable requested clock (90k clock is always on) */
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled(); bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true); rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable(); clk_ll_rc_fast_d256_digi_enable();
} }
uint32_t cal_val; uint32_t cal_val;
if (cal_mode == RTC_TIME_CAL_ONEOFF_MODE) { if (cal_mode == RTC_TIME_CAL_ONEOFF_MODE) {
cal_val = rtc_clk_cal_internal_oneoff(cal_clk, slowclk_cycles); cal_val = rtc_clk_cal_internal_oneoff(cal_clk_sel, slowclk_cycles);
} else { } else {
cal_val = rtc_clk_cal_internal_cycling(cal_clk, slowclk_cycles); cal_val = rtc_clk_cal_internal_cycling(cal_clk_sel, slowclk_cycles);
} }
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable(); clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled); rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
} }
@@ -190,10 +184,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui
return cal_val; return cal_val;
} }
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio; return ratio;
@@ -206,20 +200,20 @@ static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)rtc_clk_xtal_freq_get(), slowclk_cycles, xtal_cycles)) { if ((cal_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)rtc_clk_xtal_freq_get(), slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }
return rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles); return rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles);
} }
uint32_t rtc_clk_cal_cycling(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_cycling(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_CYCLING_MODE); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles, RTC_TIME_CAL_CYCLING_MODE);
uint32_t period = rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles); uint32_t period = rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles);
return period; return period;
} }

23
components/esp_hw_support/port/esp32s3/include/soc/rtc.h
View File

@@ -161,15 +161,10 @@ typedef struct rtc_cpu_freq_config_s {
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/** #define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
* @brief Clock source to be calibrated using rtc_clk_cal function #define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256
*/ #define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
typedef enum { #define RTC_CAL_INTERNAL_OSC _Pragma ("GCC warning \"'RTC_CAL_INTERNAL_OSC' macro is deprecated\"") CLK_CAL_RC_SLOW
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
} rtc_cal_sel_t;
/** /**
* Initialization parameters for rtc_clk_init * Initialization parameters for rtc_clk_init
@@ -448,8 +443,6 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
*/ */
uint32_t rtc_clk_apb_freq_get(void); uint32_t rtc_clk_apb_freq_get(void);
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/** /**
* @brief Measure RTC slow clock's period, based on main XTAL frequency * @brief Measure RTC slow clock's period, based on main XTAL frequency
* *
@@ -463,21 +456,21 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
* the check fails, then consider this an invalid 32k clock and return 0. This * the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal. * check can filter some jamming signal.
* *
* @param cal_clk clock to be measured * @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format, * @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out * or 0 if calibration has timed out
*/ */
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cal_clk slow clock to be measured * @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average * @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency, * @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out. * Q13.19 fixed point format, or 0 if calibration has timed out.
*/ */
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/** /**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

11
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -283,16 +283,9 @@ static void calibrate_ocode(void)
4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
5. set cpu to old-config. 5. set cpu to old-config.
*/ */
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256;
}
uint64_t max_delay_time_us = 10000; uint64_t max_delay_time_us = 10000;
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); uint32_t slow_clk_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, 100);
uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
uint64_t cycle0 = rtc_time_get(); uint64_t cycle0 = rtc_time_get();
uint64_t timeout_cycle = cycle0 + max_delay_cycle; uint64_t timeout_cycle = cycle0 + max_delay_cycle;

51
components/esp_hw_support/port/esp32s3/rtc_time.c
View File

@@ -14,11 +14,11 @@
#include "soc/timer_group_reg.h" #include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. /* Calculation of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles. * RTC_SLOW_CLK cycles.
* *
* Slow clock calibration feature has two modes of operation: one-off and cycling. * Slow clock frequency calculation feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
@@ -27,38 +27,33 @@
*/ */
/** /**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio * @brief Clock frequency calculation function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cal_clk which clock to calibrate * @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count * @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles * @return number of XTAL clock cycles within the given number of slow clock cycles
*/ */
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
/* On ESP32S3, choosing RTC_CAL_RTC_MUX results in calibration of if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
* the 150k RTC clock regardless of the currently selected SLOW_CLK.
* On the ESP32, it used the currently selected SLOW_CLK.
* The following code emulates ESP32 behavior:
*/
if (cal_clk == RTC_CAL_RTC_MUX) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cal_clk = RTC_CAL_32K_XTAL; cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256; cal_clk_sel = CLK_CAL_RC_FAST_D256;
} }
} else if (cal_clk == RTC_CAL_INTERNAL_OSC) {
cal_clk = RTC_CAL_RTC_MUX;
} }
/* Enable requested clock (150k clock is always on) */ /* Enable requested clock (150k clock is always on) */
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable(); clk_ll_xtal32k_digi_enable();
} }
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled(); bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true); rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable(); clk_ll_rc_fast_d256_digi_enable();
} }
@@ -76,17 +71,17 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
} }
/* Prepare calibration */ /* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */ /* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/ /* Set timeout reg and expect time delay*/
uint32_t expected_freq; uint32_t expected_freq;
if (cal_clk == RTC_CAL_32K_XTAL) { if (cal_clk_sel == CLK_CAL_32K_XTAL) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cal_clk == RTC_CAL_8MD256) { } else if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX; expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else { } else {
@@ -114,11 +109,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable(); clk_ll_xtal32k_digi_disable();
} }
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable(); clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled); rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
} }
@@ -126,10 +121,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
return cal_val; return cal_val;
} }
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio; return ratio;
@@ -142,13 +137,13 @@ static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
} }
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{ {
assert(slowclk_cycles); assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { if ((cal_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0; return 0;
} }

18
components/esp_hw_support/port/esp_clk_tree_common.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -59,7 +59,7 @@ static uint32_t clk_tree_rtc_slow_calibration(uint32_t slowclk_cycles)
{ {
uint32_t cal_val = 0; uint32_t cal_val = 0;
if (slowclk_cycles > 0) { if (slowclk_cycles > 0) {
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, slowclk_cycles); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, slowclk_cycles);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
uint32_t source_approx_freq = clk_hal_lp_slow_get_freq_hz(); uint32_t source_approx_freq = clk_hal_lp_slow_get_freq_hz();
@@ -82,11 +82,11 @@ uint32_t esp_clk_tree_rc_fast_d256_get_freq_hz(esp_clk_tree_src_freq_precision_t
return SOC_CLK_RC_FAST_D256_FREQ_APPROX; return SOC_CLK_RC_FAST_D256_FREQ_APPROX;
case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED: case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
if (!s_calibrated_freq.rc_fast_d256) { if (!s_calibrated_freq.rc_fast_d256) {
s_calibrated_freq.rc_fast_d256 = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, DEFAULT_32K_CLK_CAL_CYCLES)); s_calibrated_freq.rc_fast_d256 = rtc_clk_freq_cal(rtc_clk_cal(CLK_CAL_RC_FAST_D256, DEFAULT_32K_CLK_CAL_CYCLES));
} }
return s_calibrated_freq.rc_fast_d256; return s_calibrated_freq.rc_fast_d256;
case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT: case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
s_calibrated_freq.rc_fast_d256 = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, DEFAULT_32K_CLK_CAL_CYCLES)); s_calibrated_freq.rc_fast_d256 = rtc_clk_freq_cal(rtc_clk_cal(CLK_CAL_RC_FAST_D256, DEFAULT_32K_CLK_CAL_CYCLES));
return s_calibrated_freq.rc_fast_d256; return s_calibrated_freq.rc_fast_d256;
default: default:
return 0; return 0;
@@ -102,11 +102,11 @@ uint32_t esp_clk_tree_xtal32k_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
return SOC_CLK_XTAL32K_FREQ_APPROX; return SOC_CLK_XTAL32K_FREQ_APPROX;
case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED: case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
if (!s_calibrated_freq.xtal32k) { if (!s_calibrated_freq.xtal32k) {
s_calibrated_freq.xtal32k = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_XTAL, DEFAULT_32K_CLK_CAL_CYCLES)); s_calibrated_freq.xtal32k = rtc_clk_freq_cal(rtc_clk_cal(CLK_CAL_32K_XTAL, DEFAULT_32K_CLK_CAL_CYCLES));
} }
return s_calibrated_freq.xtal32k; return s_calibrated_freq.xtal32k;
case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT: case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
s_calibrated_freq.xtal32k = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_XTAL, DEFAULT_32K_CLK_CAL_CYCLES)); s_calibrated_freq.xtal32k = rtc_clk_freq_cal(rtc_clk_cal(CLK_CAL_32K_XTAL, DEFAULT_32K_CLK_CAL_CYCLES));
return s_calibrated_freq.xtal32k; return s_calibrated_freq.xtal32k;
default: default:
return 0; return 0;
@@ -122,11 +122,11 @@ uint32_t esp_clk_tree_osc_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t pre
return SOC_CLK_OSC_SLOW_FREQ_APPROX; return SOC_CLK_OSC_SLOW_FREQ_APPROX;
case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED: case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
if (!s_calibrated_freq.osc_slow) { if (!s_calibrated_freq.osc_slow) {
s_calibrated_freq.osc_slow = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_OSC_SLOW, DEFAULT_32K_CLK_CAL_CYCLES)); s_calibrated_freq.osc_slow = rtc_clk_freq_cal(rtc_clk_cal(CLK_CAL_32K_OSC_SLOW, DEFAULT_32K_CLK_CAL_CYCLES));
} }
return s_calibrated_freq.osc_slow; return s_calibrated_freq.osc_slow;
case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT: case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
s_calibrated_freq.osc_slow = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_OSC_SLOW, DEFAULT_32K_CLK_CAL_CYCLES)); s_calibrated_freq.osc_slow = rtc_clk_freq_cal(rtc_clk_cal(CLK_CAL_32K_OSC_SLOW, DEFAULT_32K_CLK_CAL_CYCLES));
return s_calibrated_freq.osc_slow; return s_calibrated_freq.osc_slow;
default: default:
return 0; return 0;
@@ -161,7 +161,7 @@ uint32_t esp_clk_tree_rc_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
#else #else
// Calibrate directly on the RC_FAST clock requires much more slow clock cycles to get an accurate freq value // Calibrate directly on the RC_FAST clock requires much more slow clock cycles to get an accurate freq value
if (precision != ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED || !s_calibrated_freq.rc_fast) { if (precision != ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED || !s_calibrated_freq.rc_fast) {
s_calibrated_freq.rc_fast = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_RC_FAST, DEFAULT_RC_FAST_CAL_CYCLES)); s_calibrated_freq.rc_fast = rtc_clk_freq_cal(rtc_clk_cal(CLK_CAL_RC_FAST, DEFAULT_RC_FAST_CAL_CYCLES));
} }
return s_calibrated_freq.rc_fast; return s_calibrated_freq.rc_fast;
#endif //SOC_CLK_RC_FAST_D256_SUPPORTED #endif //SOC_CLK_RC_FAST_D256_SUPPORTED

8
components/esp_hw_support/sleep_modes.c
View File

@@ -828,18 +828,18 @@ static SLEEP_FN_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
} else { } else {
// If the external 32 kHz XTAL does not exist, use the internal 150 kHz RC oscillator // If the external 32 kHz XTAL does not exist, use the internal 150 kHz RC oscillator
// as the RTC slow clock source. // as the RTC slow clock source.
s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); s_config.rtc_clk_cal_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, RTC_CLK_SRC_CAL_CYCLES);
esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
} }
#elif CONFIG_RTC_CLK_SRC_INT_RC && CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_RTC_CLK_SRC_INT_RC && CONFIG_IDF_TARGET_ESP32S2
s_config.rtc_clk_cal_period = rtc_clk_cal_cycling(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); s_config.rtc_clk_cal_period = rtc_clk_cal_cycling(CLK_CAL_RTC_SLOW, RTC_CLK_SRC_CAL_CYCLES);
esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
#else #else
#if CONFIG_PM_ENABLE #if CONFIG_PM_ENABLE
if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp) if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp)
#endif #endif
{ {
s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); s_config.rtc_clk_cal_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, RTC_CLK_SRC_CAL_CYCLES);
esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
} }
#endif #endif
@@ -850,7 +850,7 @@ static SLEEP_FN_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp) if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp)
#endif #endif
{ {
s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES); s_config.fast_clk_cal_period = rtc_clk_cal(CLK_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES);
} }
#endif #endif
} }

28
components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
View File

@@ -31,7 +31,7 @@
#define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk) #define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk)
static uint32_t calibrate_one(rtc_cal_sel_t cal_clk, const char* name) static uint32_t calibrate_one(soc_clk_freq_calculation_src_t cal_clk, const char* name)
{ {
const uint32_t cal_count = 1000; const uint32_t cal_count = 1000;
const float factor = (1 << 19) * 1000.0f; const float factor = (1 << 19) * 1000.0f;
@@ -54,13 +54,13 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]")
// By default Kconfig, RTC_SLOW_CLK source is RC_SLOW // By default Kconfig, RTC_SLOW_CLK source is RC_SLOW
soc_rtc_slow_clk_src_t default_rtc_slow_clk_src = rtc_clk_slow_src_get(); soc_rtc_slow_clk_src_t default_rtc_slow_clk_src = rtc_clk_slow_src_get();
CALIBRATE_ONE(RTC_CAL_RTC_MUX); CALIBRATE_ONE(CLK_CAL_RTC_SLOW);
#if SOC_CLK_RC_FAST_D256_SUPPORTED #if SOC_CLK_RC_FAST_D256_SUPPORTED
CALIBRATE_ONE(RTC_CAL_8MD256); CALIBRATE_ONE(CLK_CAL_RC_FAST_D256);
#endif #endif
#if SOC_CLK_XTAL32K_SUPPORTED #if SOC_CLK_XTAL32K_SUPPORTED
uint32_t cal_32k = CALIBRATE_ONE(RTC_CAL_32K_XTAL); uint32_t cal_32k = CALIBRATE_ONE(CLK_CAL_32K_XTAL);
if (cal_32k == 0) { if (cal_32k == 0) {
printf("32K XTAL OSC has not started up\n"); printf("32K XTAL OSC has not started up\n");
} else { } else {
@@ -68,11 +68,11 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]")
rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_XTAL32K); rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
printf("done\n"); printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX); CALIBRATE_ONE(CLK_CAL_RTC_SLOW);
#if SOC_CLK_RC_FAST_D256_SUPPORTED #if SOC_CLK_RC_FAST_D256_SUPPORTED
CALIBRATE_ONE(RTC_CAL_8MD256); CALIBRATE_ONE(CLK_CAL_RC_FAST_D256);
#endif #endif
CALIBRATE_ONE(RTC_CAL_32K_XTAL); CALIBRATE_ONE(CLK_CAL_32K_XTAL);
} }
#endif #endif
@@ -81,16 +81,16 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]")
rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256); rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256);
printf("done\n"); printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX); CALIBRATE_ONE(CLK_CAL_RTC_SLOW);
CALIBRATE_ONE(RTC_CAL_8MD256); CALIBRATE_ONE(CLK_CAL_RC_FAST_D256);
#if SOC_CLK_XTAL32K_SUPPORTED #if SOC_CLK_XTAL32K_SUPPORTED
CALIBRATE_ONE(RTC_CAL_32K_XTAL); CALIBRATE_ONE(CLK_CAL_32K_XTAL);
#endif #endif
#endif #endif
#if SOC_CLK_OSC_SLOW_SUPPORTED #if SOC_CLK_OSC_SLOW_SUPPORTED
rtc_clk_32k_enable_external(); rtc_clk_32k_enable_external();
uint32_t cal_ext_slow_clk = CALIBRATE_ONE(RTC_CAL_32K_OSC_SLOW); uint32_t cal_ext_slow_clk = CALIBRATE_ONE(CLK_CAL_32K_OSC_SLOW);
if (cal_ext_slow_clk == 0) { if (cal_ext_slow_clk == 0) {
printf("EXT CLOCK by PIN has not started up\n"); printf("EXT CLOCK by PIN has not started up\n");
} else { } else {
@@ -98,11 +98,11 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]")
rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW); rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
printf("done\n"); printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX); CALIBRATE_ONE(CLK_CAL_RTC_SLOW);
#if SOC_CLK_RC_FAST_D256_SUPPORTED #if SOC_CLK_RC_FAST_D256_SUPPORTED
CALIBRATE_ONE(RTC_CAL_8MD256); CALIBRATE_ONE(CLK_CAL_RC_FAST_D256);
#endif #endif
CALIBRATE_ONE(RTC_CAL_32K_OSC_SLOW); CALIBRATE_ONE(CLK_CAL_32K_OSC_SLOW);
} }
#endif #endif

4
components/esp_system/port/soc/esp32/clk.c
View File

@@ -78,7 +78,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
if (cal_val == 0) { if (cal_val == 0) {
if (retry_32k_xtal-- > 0) { if (retry_32k_xtal-- > 0) {
continue; continue;
@@ -99,7 +99,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

4
components/esp_system/port/soc/esp32c2/clk.c
View File

@@ -167,7 +167,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
cal_val = rtc_clk_cal(RTC_CAL_32K_OSC_SLOW, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_32K_OSC_SLOW, SLOW_CLK_CAL_CYCLES);
if (cal_val == 0) { if (cal_val == 0) {
if (retry_ext_clk-- > 0) { if (retry_ext_clk-- > 0) {
continue; continue;
@@ -187,7 +187,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

4
components/esp_system/port/soc/esp32c3/clk.c
View File

@@ -163,7 +163,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
if (cal_val == 0) { if (cal_val == 0) {
if (retry_32k_xtal-- > 0) { if (retry_32k_xtal-- > 0) {
continue; continue;
@@ -184,7 +184,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

8
components/esp_system/port/soc/esp32c5/clk.c
View File

@@ -177,13 +177,13 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0. * will time out, returning 0.
*/ */
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
rtc_cal_sel_t cal_sel = 0; soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true); rtc_clk_32k_enable(true);
cal_sel = RTC_CAL_32K_XTAL; cal_sel = CLK_CAL_32K_XTAL;
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable_external(); rtc_clk_32k_enable_external();
cal_sel = RTC_CAL_32K_OSC_SLOW; cal_sel = CLK_CAL_32K_OSC_SLOW;
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
@@ -208,7 +208,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

10
components/esp_system/port/soc/esp32c6/clk.c
View File

@@ -103,8 +103,6 @@ __attribute__((weak)) void esp_clk_init(void)
select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K); select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC) #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW); select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K)
select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC32K);
#else #else
select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW); select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
#endif #endif
@@ -158,13 +156,13 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0. * will time out, returning 0.
*/ */
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
rtc_cal_sel_t cal_sel = 0; soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true); rtc_clk_32k_enable(true);
cal_sel = RTC_CAL_32K_XTAL; cal_sel = CLK_CAL_32K_XTAL;
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable_external(); rtc_clk_32k_enable_external();
cal_sel = RTC_CAL_32K_OSC_SLOW; cal_sel = CLK_CAL_32K_OSC_SLOW;
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
@@ -195,7 +193,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

8
components/esp_system/port/soc/esp32c61/clk.c
View File

@@ -127,13 +127,13 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0. * will time out, returning 0.
*/ */
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
rtc_cal_sel_t cal_sel = 0; soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true); rtc_clk_32k_enable(true);
cal_sel = RTC_CAL_32K_XTAL; cal_sel = CLK_CAL_32K_XTAL;
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable_external(); rtc_clk_32k_enable_external();
cal_sel = RTC_CAL_32K_OSC_SLOW; cal_sel = CLK_CAL_32K_OSC_SLOW;
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
@@ -158,7 +158,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

8
components/esp_system/port/soc/esp32h2/clk.c
View File

@@ -160,13 +160,13 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0. * will time out, returning 0.
*/ */
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
rtc_cal_sel_t cal_sel = 0; soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true); rtc_clk_32k_enable(true);
cal_sel = RTC_CAL_32K_XTAL; cal_sel = CLK_CAL_32K_XTAL;
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable_external(); rtc_clk_32k_enable_external();
cal_sel = RTC_CAL_32K_OSC_SLOW; cal_sel = CLK_CAL_32K_OSC_SLOW;
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
@@ -197,7 +197,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

8
components/esp_system/port/soc/esp32h21/clk.c
View File

@@ -130,13 +130,13 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0. * will time out, returning 0.
*/ */
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
rtc_cal_sel_t cal_sel = 0; soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true); rtc_clk_32k_enable(true);
cal_sel = RTC_CAL_32K_XTAL; cal_sel = CLK_CAL_32K_XTAL;
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable_external(); rtc_clk_32k_enable_external();
cal_sel = RTC_CAL_32K_OSC_SLOW; cal_sel = CLK_CAL_32K_OSC_SLOW;
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
@@ -162,7 +162,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

8
components/esp_system/port/soc/esp32h4/clk.c
View File

@@ -126,13 +126,13 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0. * will time out, returning 0.
*/ */
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
rtc_cal_sel_t cal_sel = 0; soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true); rtc_clk_32k_enable(true);
cal_sel = RTC_CAL_32K_XTAL; cal_sel = CLK_CAL_32K_XTAL;
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable_external(); rtc_clk_32k_enable_external();
cal_sel = RTC_CAL_32K_OSC_SLOW; cal_sel = CLK_CAL_32K_OSC_SLOW;
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
@@ -158,7 +158,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

6
components/esp_system/port/soc/esp32p4/clk.c
View File

@@ -172,10 +172,10 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0. * will time out, returning 0.
*/ */
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
rtc_cal_sel_t cal_sel = 0; soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true); rtc_clk_32k_enable(true);
cal_sel = RTC_CAL_32K_XTAL; cal_sel = CLK_CAL_32K_XTAL;
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
@@ -206,7 +206,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

4
components/esp_system/port/soc/esp32s2/clk.c
View File

@@ -166,7 +166,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
if (cal_val == 0) { if (cal_val == 0) {
if (retry_32k_xtal-- > 0) { if (retry_32k_xtal-- > 0) {
continue; continue;
@@ -187,7 +187,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

4
components/esp_system/port/soc/esp32s3/clk.c
View File

@@ -164,7 +164,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
} }
// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
if (cal_val == 0) { if (cal_val == 0) {
if (retry_32k_xtal-- > 0) { if (retry_32k_xtal-- > 0) {
continue; continue;
@@ -185,7 +185,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.
*/ */
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); cal_val = rtc_clk_cal(CLK_CAL_RTC_SLOW, SLOW_CLK_CAL_CYCLES);
} else { } else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());

2
components/esp_system/xt_wdt.c
View File

@@ -56,7 +56,7 @@ esp_err_t esp_xt_wdt_init(const esp_xt_wdt_config_t *cfg)
if (cfg->auto_backup_clk_enable) { if (cfg->auto_backup_clk_enable) {
/* Estimate frequency of internal RTC oscillator */ /* Estimate frequency of internal RTC oscillator */
uint32_t rtc_clk_frequency_khz = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_INTERNAL_OSC, RTC_CLK_CAL_CYCLES)) / 1000; uint32_t rtc_clk_frequency_khz = rtc_clk_freq_cal(rtc_clk_cal(CLK_CAL_RC_SLOW, RTC_CLK_CAL_CYCLES)) / 1000;
ESP_LOGD(TAG, "Calibrating backup clock from rtc clock with frequency %"PRIu32, rtc_clk_frequency_khz); ESP_LOGD(TAG, "Calibrating backup clock from rtc clock with frequency %"PRIu32, rtc_clk_frequency_khz);
xt_wdt_hal_enable_backup_clk(&s_hal_ctx, rtc_clk_frequency_khz); xt_wdt_hal_enable_backup_clk(&s_hal_ctx, rtc_clk_frequency_khz);

2
components/esp_timer/test_apps/main/test_esp_timer_dfs.c
View File

@@ -109,7 +109,7 @@ static int64_t test_periodic_timer_accuracy_on_dfs(esp_timer_handle_t timer)
{ {
// Calibrate slow clock. // Calibrate slow clock.
#if !CONFIG_ESP_SYSTEM_RTC_EXT_XTAL #if !CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
esp_clk_slowclk_cal_set(rtc_clk_cal(RTC_CAL_RTC_MUX, 8192)); esp_clk_slowclk_cal_set(rtc_clk_cal(CLK_CAL_RTC_SLOW, 8192));
#endif #endif
ESP_ERROR_CHECK(esp_timer_start_periodic(timer, ALARM_PERIOD_MS * 1000)); ESP_ERROR_CHECK(esp_timer_start_periodic(timer, ALARM_PERIOD_MS * 1000));

26
components/hal/esp32/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -13,6 +13,7 @@
#include "soc/rtc_io_reg.h" #include "soc/rtc_io_reg.h"
#include "soc/dport_reg.h" #include "soc/dport_reg.h"
#include "soc/syscon_reg.h" #include "soc/syscon_reg.h"
#include "soc/timer_group_struct.h"
#include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h" #include "soc/regi2c_bbpll.h"
#include "soc/regi2c_apll.h" #include "soc/regi2c_apll.h"
@@ -702,6 +703,29 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so
} }
} }
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RTC_SLOW:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 0;
break;
case CLK_CAL_RC_FAST_D256:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 1;
break;
case CLK_CAL_32K_XTAL:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 2;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *

26
components/hal/esp32c2/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -13,6 +13,7 @@
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h" #include "soc/regi2c_bbpll.h"
#include "soc/timer_group_struct.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "hal/log.h" #include "hal/log.h"
#include "esp32c2/rom/rtc.h" #include "esp32c2/rom/rtc.h"
@@ -386,6 +387,29 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
} }
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 0;
break;
case CLK_CAL_RC_FAST_D256:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 1;
break;
case CLK_CAL_32K_OSC_SLOW:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 2;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *

26
components/hal/esp32c3/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -13,6 +13,7 @@
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h" #include "soc/regi2c_bbpll.h"
#include "soc/timer_group_struct.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "hal/log.h" #include "hal/log.h"
#include "esp32c3/rom/rtc.h" #include "esp32c3/rom/rtc.h"
@@ -494,6 +495,29 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
} }
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 0;
break;
case CLK_CAL_RC_FAST_D256:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 1;
break;
case CLK_CAL_32K_XTAL:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 2;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *

66
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@@ -441,6 +441,55 @@ static inline __attribute__((always_inline)) void clk_ll_soc_root_clk_auto_gatin
} }
} }
/**
* @brief Enable the RTC clock calibration reference XTAL source on timer group0.
* @param enable Enable or disable the XTAL source.
*/
static inline __attribute__((always_inline)) void clk_ll_enable_timergroup_rtc_calibration_clock(bool enable)
{
PCR.timergroup_xtal_conf.tg0_xtal_clk_en = enable;
}
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
switch (clk_sel) {
case CLK_CAL_32K_XTAL:
timg_cali_clk_sel = 1;
break;
case CLK_CAL_32K_OSC_SLOW:
timg_cali_clk_sel = 2;
break;
case CLK_CAL_RC_SLOW:
timg_cali_clk_sel = 3;
break;
case CLK_CAL_RC_FAST:
timg_cali_clk_sel = 4;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
if (timg_cali_clk_sel >= 0) {
PCR.ctrl_32k_conf.clk_32k_sel = timg_cali_clk_sel;
}
}
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *
@@ -549,14 +598,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider
return 1; return 1;
} }
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/** /**
* @brief Set RC_SLOW_CLK divider * @brief Set RC_SLOW_CLK divider
* *
@@ -568,15 +609,6 @@ static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uin
HAL_ASSERT(divider == 1); HAL_ASSERT(divider == 1);
} }
/**
* @brief Enable the RTC clock calibration reference XTAL source on timer group0.
* @param enable enable or disable the XTAL source.
*/
static inline __attribute__((always_inline)) void clk_ll_enable_timergroup_rtc_calibration_clock(bool enable)
{
PCR.timergroup_xtal_conf.tg0_xtal_clk_en = enable;
}
/************************** LP STORAGE REGISTER STORE/LOAD **************************/ /************************** LP STORAGE REGISTER STORE/LOAD **************************/
/** /**
* @brief Store RTC_SLOW_CLK calibration value in RTC storage register * @brief Store RTC_SLOW_CLK calibration value in RTC storage register

71
components/hal/esp32c6/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -14,6 +14,7 @@
#include "soc/pmu_reg.h" #include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h" #include "soc/regi2c_bbpll.h"
#include "soc/timer_group_struct.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "hal/log.h" #include "hal/log.h"
#include "esp32c6/rom/rtc.h" #include "esp32c6/rom/rtc.h"
@@ -577,46 +578,53 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divide
} }
/** /**
* @brief Select the calibration 32kHz clock source for timergroup0 * @brief Select the frequency calculation clock source for timergroup0
* *
* @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK) * @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/ */
static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{ {
switch (in_sel) { int timg_cali_clk_sel = -1;
case SOC_RTC_SLOW_CLK_SRC_RC32K: int clk_32k_sel = -1;
PCR.ctrl_32k_conf.clk_32k_sel = 0;
switch (clk_sel) {
case CLK_CAL_RC32K:
timg_cali_clk_sel = 2;
clk_32k_sel = 0;
break; break;
case SOC_RTC_SLOW_CLK_SRC_XTAL32K: case CLK_CAL_32K_XTAL:
PCR.ctrl_32k_conf.clk_32k_sel = 1; timg_cali_clk_sel = 2;
clk_32k_sel = 1;
break; break;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: case CLK_CAL_32K_OSC_SLOW:
PCR.ctrl_32k_conf.clk_32k_sel = 2; timg_cali_clk_sel = 2;
clk_32k_sel = 2;
break;
case CLK_CAL_RC_SLOW:
timg_cali_clk_sel = 0;
break;
case CLK_CAL_RC_FAST:
timg_cali_clk_sel = 1;
break; break;
default: default:
// Unsupported 32K_SEL mux input // Unsupported CLK_CAL mux input
abort(); abort();
} }
if (timg_cali_clk_sel >= 0) {
TIMERG0.rtccalicfg.rtc_cali_clk_sel = timg_cali_clk_sel;
}
if (clk_32k_sel >= 0) {
PCR.ctrl_32k_conf.clk_32k_sel = clk_32k_sel;
}
} }
/** /**
* @brief Get the calibration 32kHz clock source for timergroup0 * @brief Set the frequency division factor of RC_FAST clock
*
* @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks)
*/ */
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
{ {
uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_tick_conf, fosc_tick_num, REG_FOSC_TICK_NUM); // enable a division of 32 to the fosc clock
switch (clk_sel) {
case 0:
return SOC_RTC_SLOW_CLK_SRC_RC32K;
case 1:
return SOC_RTC_SLOW_CLK_SRC_XTAL32K;
case 2:
return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW;
default:
return SOC_RTC_SLOW_CLK_SRC_INVALID;
}
} }
/** /**
@@ -806,15 +814,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
} }
/*
Set the frequency division factor of ref_tick
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_tick_conf, fosc_tick_num, REG_FOSC_TICK_NUM); // enable a division of 32 to the fosc clock
}
/* /*
* Enable/Disable the clock gate for clock output signal source * Enable/Disable the clock gate for clock output signal source
*/ */

48
components/hal/esp32c61/include/hal/clk_tree_ll.h
View File

@@ -396,6 +396,46 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1; return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
} }
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
switch (clk_sel) {
case CLK_CAL_32K_XTAL:
timg_cali_clk_sel = 1;
break;
case CLK_CAL_32K_OSC_SLOW:
timg_cali_clk_sel = 2;
break;
case CLK_CAL_RC_SLOW:
timg_cali_clk_sel = 3;
break;
case CLK_CAL_RC_FAST:
timg_cali_clk_sel = 4;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
if (timg_cali_clk_sel >= 0) {
PCR.ctrl_32k_conf.clk_32k_sel = timg_cali_clk_sel;
}
}
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *
@@ -504,14 +544,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider
return 1; return 1;
} }
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/** /**
* @brief Set RC_SLOW_CLK divider * @brief Set RC_SLOW_CLK divider
* *

70
components/hal/esp32h2/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -15,6 +15,7 @@
#include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h" #include "soc/regi2c_bbpll.h"
#include "soc/regi2c_pmu.h" #include "soc/regi2c_pmu.h"
#include "soc/timer_group_struct.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "hal/log.h" #include "hal/log.h"
#include "esp32h2/rom/rtc.h" #include "esp32h2/rom/rtc.h"
@@ -458,46 +459,53 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
} }
/** /**
* @brief Select the calibration 32kHz clock source for timergroup0 * @brief Select the frequency calculation clock source for timergroup0
* *
* @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK) * @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/ */
static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{ {
switch (in_sel) { int timg_cali_clk_sel = -1;
case SOC_RTC_SLOW_CLK_SRC_RC32K: int clk_32k_sel = -1;
PCR.ctrl_32k_conf.clk_32k_sel = 0;
switch (clk_sel) {
case CLK_CAL_RC32K:
timg_cali_clk_sel = 2;
clk_32k_sel = 0;
break; break;
case SOC_RTC_SLOW_CLK_SRC_XTAL32K: case CLK_CAL_32K_XTAL:
PCR.ctrl_32k_conf.clk_32k_sel = 1; timg_cali_clk_sel = 2;
clk_32k_sel = 1;
break; break;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: case CLK_CAL_32K_OSC_SLOW:
PCR.ctrl_32k_conf.clk_32k_sel = 2; timg_cali_clk_sel = 2;
clk_32k_sel = 2;
break;
case CLK_CAL_RC_SLOW:
timg_cali_clk_sel = 0;
break;
case CLK_CAL_RC_FAST:
timg_cali_clk_sel = 1;
break; break;
default: default:
// Unsupported 32K_SEL mux input // Unsupported CLK_CAL mux input
abort(); abort();
} }
if (timg_cali_clk_sel >= 0) {
TIMERG0.rtccalicfg.rtc_cali_clk_sel = timg_cali_clk_sel;
}
if (clk_32k_sel >= 0) {
PCR.ctrl_32k_conf.clk_32k_sel = clk_32k_sel;
}
} }
/** /**
* @brief Get the calibration 32kHz clock source for timergroup0 * @brief Set the frequency division factor of RC_FAST clock
*
* @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks)
*/ */
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
{ {
uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_tick_conf, fosc_tick_num, REG_FOSC_TICK_NUM); // enable a division of 32 to the fosc clock
switch (clk_sel) {
case 0:
return SOC_RTC_SLOW_CLK_SRC_RC32K;
case 1:
return SOC_RTC_SLOW_CLK_SRC_XTAL32K;
case 2:
return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW;
default:
return SOC_RTC_SLOW_CLK_SRC_INVALID;
}
} }
/** /**
@@ -742,14 +750,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
return REG_READ(RTC_SLOW_CLK_CAL_REG); return REG_READ(RTC_SLOW_CLK_CAL_REG);
} }
/*
Set the frequency division factor of ref_tick
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_tick_conf, fosc_tick_num, REG_FOSC_TICK_NUM); // enable a division of 32 to the fosc clock
}
/* /*
* Enable/Disable the clock gate for clock output signal source * Enable/Disable the clock gate for clock output signal source
*/ */

22
components/hal/esp32h21/include/hal/clk_tree_ll.h
View File

@@ -411,11 +411,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
} }
/** /**
* @brief Select the calibration clock source for timergroup0 * @brief Select the frequency calculation clock source for timergroup0
* *
* @param clk_sel One of the clock sources in soc_clk_calibration_clk_src_t * @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/ */
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_clk_calibration_clk_src_t clk_sel) static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{ {
int timg_cali_clk_sel = -1; int timg_cali_clk_sel = -1;
int clk_32k_sel = -1; int clk_32k_sel = -1;
@@ -448,6 +448,14 @@ static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(
} }
} }
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_tick_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *
@@ -551,14 +559,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider
return 1; return 1;
} }
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_tick_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/** /**
* @brief Set RC_SLOW_CLK divider. The output from the divider is passed into rtc_slow_clk MUX. * @brief Set RC_SLOW_CLK divider. The output from the divider is passed into rtc_slow_clk MUX.
* *

10
components/hal/esp32h4/include/hal/clk_tree_ll.h
View File

@@ -420,11 +420,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
} }
/** /**
* @brief Select the calibration clock source for timergroup0 * @brief Select the frequency calculation clock source for timergroup0
* *
* @param clk_sel One of the clock sources in soc_clk_calibration_clk_src_t * @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/ */
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_clk_calibration_clk_src_t clk_sel) static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{ {
int timg_cali_clk_sel = -1; int timg_cali_clk_sel = -1;
int timg_secure_clk_sel = -1; int timg_secure_clk_sel = -1;
@@ -501,11 +501,11 @@ static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(
} }
/** /**
* @brief Set a divider for the clock to be calibrated by timergroup0 * @brief Set a divider for the clock to be frequency calculated by timergroup0
* *
* @param divider Divider. PRE_DIV_CNT = divider - 1. * @param divider Divider. PRE_DIV_CNT = divider - 1.
*/ */
static inline __attribute__((always_inline)) void clk_ll_calibration_set_divider(uint32_t divider) static inline __attribute__((always_inline)) void clk_ll_freq_calculation_set_divider(uint32_t divider)
{ {
HAL_ASSERT(divider >= 1); HAL_ASSERT(divider >= 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.timg_cali_clk_conf, timg_secure_clk_div_num, divider - 1); HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.timg_cali_clk_conf, timg_secure_clk_div_num, divider - 1);

67
components/hal/esp32p4/include/hal/clk_tree_ll.h
View File

@@ -725,6 +725,73 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f20m_get_divide
return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_clk_ctrl1, reg_ref_20m_clk_div_num) + 1; return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_clk_ctrl1, reg_ref_20m_clk_div_num) + 1;
} }
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
switch (clk_sel) {
case CLK_CAL_MPLL:
timg_cali_clk_sel = 0;
break;
case CLK_CAL_SPLL:
timg_cali_clk_sel = 1;
break;
case CLK_CAL_CPLL:
timg_cali_clk_sel = 2;
break;
case CLK_CAL_APLL:
timg_cali_clk_sel = 3;
break;
case CLK_CAL_SDIO_PLL0:
timg_cali_clk_sel = 4;
break;
case CLK_CAL_SDIO_PLL1:
timg_cali_clk_sel = 5;
break;
case CLK_CAL_SDIO_PLL2:
timg_cali_clk_sel = 6;
break;
case CLK_CAL_RC_FAST:
timg_cali_clk_sel = 7;
break;
case CLK_CAL_RC_SLOW:
timg_cali_clk_sel = 8;
break;
case CLK_CAL_RC32K:
timg_cali_clk_sel = 9;
break;
case CLK_CAL_32K_XTAL:
timg_cali_clk_sel = 10;
break;
case CLK_CAL_LP_PLL:
timg_cali_clk_sel = 11;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
if (timg_cali_clk_sel >= 0) {
HP_SYS_CLKRST.peri_clk_ctrl21.reg_timergrp0_tgrt_clk_src_sel = timg_cali_clk_sel;
}
}
/**
* @brief Set a divider for the clock to be frequency calculated by timergroup0
*
* @param divider Divider. PRE_DIV_CNT = divider - 1.
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calculation_set_divider(uint32_t divider)
{
HAL_ASSERT(divider >= 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl21, reg_timergrp0_tgrt_clk_div_num, divider - 1);
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *

26
components/hal/esp32s2/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -15,6 +15,7 @@
#include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h" #include "soc/regi2c_bbpll.h"
#include "soc/regi2c_apll.h" #include "soc/regi2c_apll.h"
#include "soc/timer_group_struct.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "esp32s2/rom/rtc.h" #include "esp32s2/rom/rtc.h"
@@ -618,6 +619,29 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so
} }
} }
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 0;
break;
case CLK_CAL_RC_FAST_D256:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 1;
break;
case CLK_CAL_32K_XTAL:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 2;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *

26
components/hal/esp32s3/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -13,6 +13,7 @@
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "hal/regi2c_ctrl.h" #include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h" #include "soc/regi2c_bbpll.h"
#include "soc/timer_group_struct.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "hal/log.h" #include "hal/log.h"
#include "esp32s3/rom/rtc.h" #include "esp32s3/rom/rtc.h"
@@ -494,6 +495,29 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
} }
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 0;
break;
case CLK_CAL_RC_FAST_D256:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 1;
break;
case CLK_CAL_32K_XTAL:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 2;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
}
/** /**
* @brief Select the clock source for RTC_SLOW_CLK * @brief Select the clock source for RTC_SLOW_CLK
* *

12
components/soc/esp32/include/soc/clk_tree_defs.h
View File

@@ -451,8 +451,6 @@ typedef enum {
LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */ LEDC_USE_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////SDMMC/////////////////////////////////////////////////////////////// //////////////////////////////////////////////////SDMMC///////////////////////////////////////////////////////////////
@@ -484,6 +482,16 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF, CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
components/soc/esp32/register/soc/timer_group_struct.h
View File

@@ -347,7 +347,7 @@ typedef union {
*/ */
uint32_t rtc_cali_start_cycling: 1; uint32_t rtc_cali_start_cycling: 1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1; /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtcslowclock. 1:clk_80m. 2:xtal_32k. * 0:rtc_slow_clock. 1:rc_fast_div_clk. 2:xtal_32k.
*/ */
uint32_t rtc_cali_clk_sel: 2; uint32_t rtc_cali_clk_sel: 2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

13
components/soc/esp32c2/include/soc/clk_tree_defs.h
View File

@@ -311,8 +311,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F60M, /*!< Select PLL_F60M as the source clock */ LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F60M, /*!< Select PLL_F60M as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// //////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
@@ -325,6 +323,17 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF, CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
components/soc/esp32c2/register/soc/timer_group_struct.h
View File

@@ -335,7 +335,7 @@ typedef union {
*/ */
uint32_t rtc_cali_start_cycling:1; uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1; /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. * 0:rc_slow_clk. 1:rc_fast_div_clk, 2:32k_osc_slow_clk.
*/ */
uint32_t rtc_cali_clk_sel:2; uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

13
components/soc/esp32c3/include/soc/clk_tree_defs.h
View File

@@ -380,8 +380,6 @@ typedef enum {
LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// //////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
@@ -394,6 +392,17 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF, CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
components/soc/esp32c3/register/soc/timer_group_struct.h
View File

@@ -339,7 +339,7 @@ typedef union {
*/ */
uint32_t rtc_cali_start_cycling: 1; uint32_t rtc_cali_start_cycling: 1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1; /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. * 0:rc_slow_clk. 1:rc_fast_div_clk. 2:xtal_32k.
*/ */
uint32_t rtc_cali_clk_sel: 2; uint32_t rtc_cali_clk_sel: 2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

14
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@@ -500,8 +500,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// //////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
@@ -558,6 +556,18 @@ typedef enum {
CLKOUT_SIG_RC_SLOW = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ CLKOUT_SIG_RC_SLOW = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

15
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@@ -478,8 +478,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// //////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
@@ -516,6 +514,19 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF, CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calculate frequency of RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
components/soc/esp32c6/register/soc/timer_group_struct.h
View File

@@ -339,7 +339,7 @@ typedef union {
*/ */
uint32_t rtc_cali_start_cycling:1; uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. * 0/3:rc_slow_clk. 1:rc_fast_div_clk, 2:32k clock, which 32k depends on PCR.ctrl_32k_conf.clk_32k_sel.
*/ */
uint32_t rtc_cali_clk_sel:2; uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

14
components/soc/esp32c61/include/soc/clk_tree_defs.h
View File

@@ -356,8 +356,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////FLASH/////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
@@ -396,6 +394,18 @@ typedef enum {
CLKOUT_SIG_RC_SLOW = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ CLKOUT_SIG_RC_SLOW = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

15
components/soc/esp32h2/include/soc/clk_tree_defs.h
View File

@@ -472,8 +472,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */ LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// //////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
@@ -525,6 +523,19 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF, CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calculate frequency of RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
components/soc/esp32h2/register/soc/timer_group_struct.h
View File

@@ -339,7 +339,7 @@ typedef union {
*/ */
uint32_t rtc_cali_start_cycling:1; uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. * 0/3:rc_slow_clk. 1:rc_fast_div_clk, 2:32k clock, which 32k depends on PCR.ctrl_32k_conf.clk_32k_sel.
*/ */
uint32_t rtc_cali_clk_sel:2; uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

15
components/soc/esp32h21/include/soc/clk_tree_defs.h
View File

@@ -338,16 +338,17 @@ typedef enum {
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t; } soc_periph_flash_clk_src_t;
////////////////////////////////////////////RTC CALIBRATION/////////////////////////////////////////////////////////// //////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/** /**
* @brief Clock frequency calibration source selection * @brief Clock frequency calculation source selection
*/ */
typedef enum { typedef enum {
CLK_CAL_RC_SLOW = 0, /*!< Select to calibrate RC_SLOW_CLK */ CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */ CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */ CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */ CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
} soc_clk_calibration_clk_src_t; CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }

2
components/soc/esp32h21/register/soc/timer_group_struct.h
View File

@@ -339,7 +339,7 @@ typedef union {
*/ */
uint32_t rtc_cali_start_cycling:1; uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. * 0:rc_slow_clk. 1:rc_fast_clk, 2:32k clk.
*/ */
uint32_t rtc_cali_clk_sel:2; uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

38
components/soc/esp32h4/include/soc/clk_tree_defs.h
View File

@@ -286,27 +286,29 @@ typedef enum {
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t; } soc_periph_flash_clk_src_t;
////////////////////////////////////////////RTC CALIBRATION/////////////////////////////////////////////////////////// //////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/** /**
* @brief Clock frequency calibration source selection * @brief Clock frequency calculation source selection
*/ */
typedef enum { typedef enum {
CLK_CAL_RC_SLOW = 0, /*!< Select to calibrate RC_SLOW_CLK */ CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */ CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */ CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */ CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_CPU, /*!< Select to calibrate CPU_CLK */ CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
CLK_CAL_AHB, /*!< Select to calibrate AHB_CLK */ CLK_CAL_CPU, /*!< Select to calculate frequency of CPU_CLK */
CLK_CAL_APB, /*!< Select to calibrate APB_CLK */ CLK_CAL_AHB, /*!< Select to calculate frequency of AHB_CLK */
CLK_CAL_SEC, /*!< Select to calibrate SEC_CLK */ CLK_CAL_APB, /*!< Select to calculate frequency of APB_CLK */
CLK_CAL_MSPI, /*!< Select to calibrate MSPI_CLK */ CLK_CAL_SEC, /*!< Select to calculate frequency of SEC_CLK */
CLK_CAL_IOMUX, /*!< Select to calibrate IOMUX_CLK */ CLK_CAL_MSPI, /*!< Select to calculate frequency of MSPI_CLK */
CLK_CAL_PARLIO_RX, /*!< Select to calibrate PARLIO_RX_CLK */ CLK_CAL_IOMUX, /*!< Select to calculate frequency of IOMUX_CLK */
CLK_CAL_PARLIO_TX, /*!< Select to calibrate PARLIO_TX_CLK */ CLK_CAL_PARLIO_RX, /*!< Select to calculate frequency of PARLIO_RX_CLK */
CLK_CAL_GPSPI3_MST, /*!< Select to calibrate GPSPI3_MST_CLK */ CLK_CAL_PARLIO_TX, /*!< Select to calculate frequency of PARLIO_TX_CLK */
CLK_CAL_GPSPI2_MST, /*!< Select to calibrate GPSPI2_MST_CLK */ CLK_CAL_GPSPI3_MST, /*!< Select to calculate frequency of GPSPI3_MST_CLK */
CLK_CAL_EXT_IO, /*!< Select to calibrate an external clock from an IO */ CLK_CAL_GPSPI2_MST, /*!< Select to calculate frequency of GPSPI2_MST_CLK */
} soc_clk_calibration_clk_src_t; CLK_CAL_EXT_IO, /*!< Select to calculate frequency of an external clock from an IO */
} soc_clk_freq_calculation_src_t;
/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/** /**

20
components/soc/esp32p4/include/soc/clk_tree_defs.h
View File

@@ -797,6 +797,26 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF, CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_MPLL, /*!< Select to calculate frequency of MPLL_CLK */
CLK_CAL_SPLL, /*!< Select to calculate frequency of SPLL_CLK */
CLK_CAL_CPLL, /*!< Select to calculate frequency of CPLL_CLK */
CLK_CAL_APLL, /*!< Select to calculate frequency of APLL_CLK */
CLK_CAL_SDIO_PLL0, /*!< Select to calculate frequency of SDIO_PLL0_CLK */
CLK_CAL_SDIO_PLL1, /*!< Select to calculate frequency of SDIO_PLL1_CLK */
CLK_CAL_SDIO_PLL2, /*!< Select to calculate frequency of SDIO_PLL2_CLK */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calculate frequency of RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_LP_PLL, /*!< Select to calculate frequency of LP_PLL_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

13
components/soc/esp32s2/include/soc/clk_tree_defs.h
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@@ -438,8 +438,6 @@ typedef enum {
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */ LEDC_USE_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// //////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
@@ -454,6 +452,17 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF, CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
components/soc/esp32s2/register/soc/timer_group_struct.h
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@@ -360,7 +360,7 @@ typedef union {
*/ */
uint32_t rtc_cali_start_cycling: 1; uint32_t rtc_cali_start_cycling: 1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1; /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtcslowclock. 1:clk_80m. 2:xtal_32k. * 0:rc_slow_clk. 1:rc_fast_div_clk. 2:xtal_32k.
*/ */
uint32_t rtc_cali_clk_sel: 2; uint32_t rtc_cali_clk_sel: 2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

13
components/soc/esp32s3/include/soc/clk_tree_defs.h
View File

@@ -469,8 +469,6 @@ typedef enum {
LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t; } soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////SDMMC/////////////////////////////////////////////////////////////// //////////////////////////////////////////////////SDMMC///////////////////////////////////////////////////////////////
@@ -499,6 +497,17 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF, CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t; } soc_clkout_sig_id_t;
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
components/soc/esp32s3/register/soc/timer_group_struct.h
View File

@@ -328,7 +328,7 @@ typedef union {
*/ */
uint32_t rtc_cali_start_cycling: 1; uint32_t rtc_cali_start_cycling: 1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1; /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_80m. 2:xtal_32k. * 0:rc_slow_clk. 1:rc_fast_div_clk. 2:xtal_32k.
*/ */
uint32_t rtc_cali_clk_sel: 2; uint32_t rtc_cali_clk_sel: 2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

11
components/ulp/ulp_common/ulp_common.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -39,14 +39,7 @@ esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us)
REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t), REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t),
SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles); SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles);
#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) #elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); uint32_t slow_clk_period = rtc_clk_cal(CLK_CAL_RTC_SLOW, 100);
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cal_clk = RTC_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cal_clk = RTC_CAL_8MD256;
}
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
uint64_t period_cycles = rtc_time_us_to_slowclk(period_us_64, slow_clk_period); uint64_t period_cycles = rtc_time_us_to_slowclk(period_us_64, slow_clk_period);
REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_1_REG, RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE, ((uint32_t)period_cycles)); REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_1_REG, RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE, ((uint32_t)period_cycles));

2
docs/en/api-reference/system/ulp_instruction_set.rst
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@@ -83,7 +83,7 @@ ULP coprocessor is clocked from ``RTC_FAST_CLK``, which is normally derived from
#include "soc/rtc.h" #include "soc/rtc.h"
// calibrate 8M/256 clock against XTAL, get 8M/256 clock period // calibrate 8M/256 clock against XTAL, get 8M/256 clock period
uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100); uint32_t rtc_8md256_period = rtc_clk_cal(CLK_CAL_RC_FAST_D256, 100);
uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period; uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period;
ULP coprocessor needs certain number of clock cycles to fetch each instruction, plus certain number of cycles to execute it, depending on the instruction. See description of each instruction below for details on the execution time. ULP coprocessor needs certain number of clock cycles to fetch each instruction, plus certain number of cycles to execute it, depending on the instruction. See description of each instruction below for details on the execution time.

2
docs/en/migration-guides/release-6.x/6.0/peripherals.rst
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@@ -62,6 +62,8 @@ LEDC
- :cpp:member:`ledc_channel_config_t::intr_type` has been deprecated. `LEDC_INTR_FADE_END` interrupt enable / disable control is handled by the driver internally. Users can still register a callback for this interrupt by :cpp:func:`ledc_cb_register`. - :cpp:member:`ledc_channel_config_t::intr_type` has been deprecated. `LEDC_INTR_FADE_END` interrupt enable / disable control is handled by the driver internally. Users can still register a callback for this interrupt by :cpp:func:`ledc_cb_register`.
- :cpp:enumerator:`soc_periph_ledc_clk_src_legacy_t::LEDC_USE_RTC8M_CLK` has been removed. Please use ``LEDC_USE_RC_FAST_CLK`` instead.
I2C I2C
--- ---

3
docs/en/migration-guides/release-6.x/6.0/system.rst
View File

@@ -48,7 +48,8 @@ Removed option for compiling bootloader with no optimization level (-O0, `CONFIG
Time Time
---- ----
The deprecated ``{IDF_TARGET_NAME}/rtc.h`` header file has been removed. Please include the replacement ``esp_rtc_time.h`` instead. - The deprecated ``{IDF_TARGET_NAME}/rtc.h`` header file has been removed. Please include the replacement ``esp_rtc_time.h`` instead.
- The deprecated ``RTC_CLK_SRC_INT_RC32K`` menuconfig option has been removed. Internal RC32K clock is unstable at extreme temperatures, please don't use this clock as the RTC slow clock source.
HW-Support HW-Support
---------- ----------

2
docs/zh_CN/api-reference/system/ulp_instruction_set.rst
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@@ -83,7 +83,7 @@ ULP 协处理器的时钟 ``RTC_FAST_CLK`` 通常来自内部的 8 MHz 振荡器
#include "soc/rtc.h" #include "soc/rtc.h"
// calibrate 8M/256 clock against XTAL, get 8M/256 clock period // calibrate 8M/256 clock against XTAL, get 8M/256 clock period
uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100); uint32_t rtc_8md256_period = rtc_clk_cal(CLK_CAL_RC_FAST_D256, 100);
uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period; uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period;
ULP 协处理器在获取每个指令时需要一定的时钟周期，执行时同样需要一定的时钟周期，此周期数取决于具体的指令。下文详细列出了每个指令所需的执行时间信息。 ULP 协处理器在获取每个指令时需要一定的时钟周期，执行时同样需要一定的时钟周期，此周期数取决于具体的指令。下文详细列出了每个指令所需的执行时间信息。

2
docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst
View File

@@ -62,6 +62,8 @@ LEDC
- :cpp:member:`ledc_channel_config_t::intr_type` 已被弃用。`LEDC_INTR_FADE_END` 中断使能/禁用控制由驱动内部处理。用户仍可以通过 :cpp:func:`ledc_cb_register` 注册该中断的回调。 - :cpp:member:`ledc_channel_config_t::intr_type` 已被弃用。`LEDC_INTR_FADE_END` 中断使能/禁用控制由驱动内部处理。用户仍可以通过 :cpp:func:`ledc_cb_register` 注册该中断的回调。
- :cpp:enumerator:`soc_periph_ledc_clk_src_legacy_t::LEDC_USE_RTC8M_CLK` 已被移除。请使用 ``LEDC_USE_RC_FAST_CLK`` 代替。
I2C I2C
--- ---

3
docs/zh_CN/migration-guides/release-6.x/6.0/system.rst
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@@ -48,7 +48,8 @@ Xtensa 特殊寄存器头文件已更新，使用新的命名约定。旧的 ``s
时间管理 时间管理
-------- --------
已弃用的头文件 ``{IDF_TARGET_NAME}/rtc.h`` 已被移除，请改用替代头文件 ``esp_rtc_time.h``。 - 已弃用的头文件 ``{IDF_TARGET_NAME}/rtc.h`` 已被移除，请改用替代头文件 ``esp_rtc_time.h``。
- 已弃用的 ``RTC_CLK_SRC_INT_RC32K`` 配置项已被移除，内部 RC32K 时钟在极端温度下不稳定，请不要使用该时钟作为 RTC 低速时钟的时钟源。
硬件支持 硬件支持
-------- --------