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change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE

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This commit is contained in:
wuzhenghui
2023-11-16 10:26:29 +08:00
parent ff3ca9300a
commit eb45eec5db
14 changed files with 31 additions and 31 deletions
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2
components/soc/esp32/include/soc/Kconfig.soc_caps.in
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@ -255,7 +255,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int int
default 2 default 2
config SOC_CPU_WATCHPOINT_SIZE config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
int int
default 64 default 64

8
components/soc/esp32/include/soc/soc_caps.h
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@ -1,6 +1,6 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -146,9 +146,9 @@
#define SOC_CPU_INTR_NUM 32 #define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FPU 1 #define SOC_CPU_HAS_FPU 1
#define SOC_CPU_BREAKPOINTS_NUM 2 #define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2 #define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes
/*-------------------------- DAC CAPS ----------------------------------------*/ /*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_CHAN_NUM 2 #define SOC_DAC_CHAN_NUM 2

2
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
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@ -195,7 +195,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int int
default 2 default 2
config SOC_CPU_WATCHPOINT_SIZE config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex hex
default 0x80000000 default 0x80000000

8
components/soc/esp32c2/include/soc/soc_caps.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -92,9 +92,9 @@
#define SOC_CPU_INTR_NUM 32 #define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_BREAKPOINTS_NUM 2 #define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2 #define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1

2
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
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@ -283,7 +283,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int int
default 8 default 8
config SOC_CPU_WATCHPOINT_SIZE config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex hex
default 0x80000000 default 0x80000000

8
components/soc/esp32c3/include/soc/soc_caps.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -124,9 +124,9 @@
#define SOC_CPU_INTR_NUM 32 #define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_BREAKPOINTS_NUM 8 #define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8 #define SOC_CPU_WATCHPOINTS_NUM 8
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */ /** The maximum length of a Digital Signature in bits. */

2
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
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@ -339,7 +339,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int int
default 4 default 4
config SOC_CPU_WATCHPOINT_SIZE config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex hex
default 0x80000000 default 0x80000000

6
components/soc/esp32c6/include/soc/soc_caps.h
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@ -138,9 +138,9 @@
#define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller #define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller
#define SOC_CPU_BREAKPOINTS_NUM 4 #define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4 #define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_HAS_PMA 1 #define SOC_CPU_HAS_PMA 1
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1

2
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@ -327,7 +327,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int int
default 4 default 4
config SOC_CPU_WATCHPOINT_SIZE config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex hex
default 0x80000000 default 0x80000000

6
components/soc/esp32h2/include/soc/soc_caps.h
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@ -136,9 +136,9 @@
#define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller #define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller
#define SOC_CPU_BREAKPOINTS_NUM 4 #define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4 #define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_HAS_PMA 1 #define SOC_CPU_HAS_PMA 1
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1

2
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
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@ -295,7 +295,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int int
default 2 default 2
config SOC_CPU_WATCHPOINT_SIZE config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
int int
default 64 default 64

6
components/soc/esp32s2/include/soc/soc_caps.h
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@ -133,9 +133,9 @@
#define SOC_CPU_CORES_NUM (1U) #define SOC_CPU_CORES_NUM (1U)
#define SOC_CPU_INTR_NUM 32 #define SOC_CPU_INTR_NUM 32
#define SOC_CPU_BREAKPOINTS_NUM 2 #define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2 #define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes
/*-------------------------- DAC CAPS ----------------------------------------*/ /*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_CHAN_NUM 2 #define SOC_DAC_CHAN_NUM 2

2
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
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@ -339,7 +339,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int int
default 2 default 2
config SOC_CPU_WATCHPOINT_SIZE config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
int int
default 64 default 64

6
components/soc/esp32s3/include/soc/soc_caps.h
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@ -127,9 +127,9 @@
#define SOC_CPU_INTR_NUM 32 #define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FPU 1 #define SOC_CPU_HAS_FPU 1
#define SOC_CPU_BREAKPOINTS_NUM 2 #define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2 #define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */ /** The maximum length of a Digital Signature in bits. */