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Merge branch 'feature/h4_core_support' into 'master'

Browse Source 
feat(core): bringup dual-core for H4

Closes IDF-12317, IDF-12319, IDF-12484, IDF-12311, and IDF-12293

See merge request espressif/esp-idf!39279
This commit is contained in:
Marius Vikhammer
2025-05-28 14:42:58 +08:00
parent d8f4388926 e527554144
commit eb76e6341d
22 changed files with 184 additions and 98 deletions
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1
Kconfig
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@ -147,7 +147,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
config IDF_TARGET_ESP32H4
bool
default "y" if IDF_TARGET="esp32h4"
select FREERTOS_UNICORE # TODO: [ESP32H4] IDF-12319, need remove
select IDF_TARGET_ARCH_RISCV
select IDF_ENV_FPGA
select IDF_ENV_BRINGUP

4
components/esp_rom/test_apps/rom_impl_components/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

8
components/esp_system/port/arch/riscv/esp_ipc_isr_handler.S
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@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/hp_system_reg.h"
#include "soc/system_reg.h"
/* IPC_ISR handler */
.equ SAVE_REGS, 16 /* count of saving regs: a0 - a7, t0 - t6, ra */
@ -36,10 +36,10 @@ esp_ipc_isr_handler:
/* MIE is cleared, so nested interrupts are disabled */
/* Reset isr interrupt flags */
li a1, HP_SYSTEM_CPU_INT_FROM_CPU_2_REG
li a1, SYSTEM_CPU_INTR_FROM_CPU_2_REG
csrr a0, mhartid # Get CORE_ID
beqz a0, 1f
li a1, HP_SYSTEM_CPU_INT_FROM_CPU_3_REG
li a1, SYSTEM_CPU_INTR_FROM_CPU_3_REG
1:
sw zero, (a1)

7
components/esp_system/port/arch/riscv/esp_ipc_isr_port.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,6 +7,7 @@
#include "soc/soc.h"
#include "soc/system_intr.h"
#include "soc/hp_system_reg.h"
#include "soc/system_reg.h"
#include "esp_intr_alloc.h"
#include "riscv/interrupt.h"
#include "esp_rom_sys.h"
@ -39,9 +40,9 @@ IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
{
if (cpuid == 0) {
// it runs an interrupt on cpu0
REG_WRITE(HP_SYSTEM_CPU_INT_FROM_CPU_2_REG, HP_SYSTEM_CPU_INT_FROM_CPU_2);
REG_WRITE(SYSTEM_CPU_INTR_FROM_CPU_2_REG, SYSTEM_CPU_INTR_FROM_CPU_2);
} else {
// it runs an interrupt on cpu1
REG_WRITE(HP_SYSTEM_CPU_INT_FROM_CPU_3_REG, HP_SYSTEM_CPU_INT_FROM_CPU_3);
REG_WRITE(SYSTEM_CPU_INTR_FROM_CPU_3_REG, SYSTEM_CPU_INTR_FROM_CPU_3);
}
}

7
components/esp_system/port/cpu_start.c
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@ -288,6 +288,7 @@ static void start_other_core(void)
// APP CPU again, as that will clear the breakpoints which may have already
// been set.
cpu_utility_ll_enable_clock_and_reset_app_cpu();
cpu_utility_ll_enable_clock_and_reset_app_cpu_int_matrix();
ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
@ -302,7 +303,7 @@ static void start_other_core(void)
}
}
#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE && !CONFIG_IDF_TARGET_ESP32H4 // TODO IDF-12289
#if CONFIG_IDF_TARGET_ESP32
static void restore_app_mmu_from_pro_mmu(void)
{
@ -356,7 +357,7 @@ void IRAM_ATTR do_multicore_settings(void)
void IRAM_ATTR call_start_cpu0(void)
{
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
soc_reset_reason_t __attribute__((unused)) rst_reas[SOC_CPU_CORES_NUM];
#else
soc_reset_reason_t __attribute__((unused)) rst_reas[1];
#endif
@ -434,7 +435,7 @@ void IRAM_ATTR call_start_cpu0(void)
}
#endif
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE && !CONFIG_IDF_TARGET_ESP32H4 // TODO IDF-12289
// It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
do_multicore_settings();
#endif

3
components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
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@ -56,9 +56,6 @@
#include "portmacro.h"
#include "port_systick.h"
#include "esp_memory_utils.h"
#if CONFIG_IDF_TARGET_ESP32P4
#include "soc/hp_system_reg.h"
#endif
#if SOC_CPU_HAS_HWLOOP
#include "riscv/csr.h"

2
components/freertos/Kconfig
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@ -6,7 +6,7 @@ menu "FreeRTOS"
config FREERTOS_SMP
bool "Run the Amazon SMP FreeRTOS kernel instead (FEATURE UNDER DEVELOPMENT)"
depends on !IDF_TARGET_ESP32P4 #TODO: IDF-8113: Enable P4 support on AMZ SMP
depends on !IDF_TARGET_ESP32P4 && !IDF_TARGET_ESP32H4 #TODO: IDF-8113: Enable P4/H4 support on AMZ SMP
default "n"
help
Amazon has released an SMP version of the FreeRTOS Kernel which can be found via the following link:

4
components/hal/esp32/include/hal/cpu_utility_ll.h
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@ -95,6 +95,10 @@ FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu_int_matrix(void)
{
}
#endif // SOC_CPU_CORES_NUM > 1
#ifdef __cplusplus

56
components/hal/esp32h4/include/cpu_utility_ll.h
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@ -1,56 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#include "soc/lp_aon_reg.h"
#include "soc/lp_aon_struct.h"
#include "soc/pcr_reg.h"
#include "esp_attr.h"
//TODO: [ESP32H4] IDF-12484, need check
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void cpu_utility_ll_reset_cpu(uint32_t cpu_no)
{
if (cpu_no == 0) {
LP_AON.cpucore_cfg.aon_cpu_core0_sw_reset = 1;
} else {
LP_AON.cpucore_cfg.aon_cpu_core1_sw_reset = 1;
}
}
FORCE_INLINE_ATTR uint32_t cpu_utility_ll_wait_mode(void)
{
return REG_GET_BIT(PCR_CPU_WAITI_CONF_REG, PCR_CPU0_WAIT_MODE_FORCE_ON);
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_debug(uint32_t cpu_no)
{
// TODO
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_record(uint32_t cpu_no)
{
// TODO
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
{
if (!REG_GET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN)) {
REG_SET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN);
}
if (REG_GET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_RST_EN)) {
REG_CLR_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_RST_EN);
}
}
#ifdef __cplusplus
}
#endif

54
components/hal/esp32h4/include/hal/cpu_utility_ll.h
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@ -9,9 +9,10 @@
#include "soc/lp_aon_reg.h"
#include "soc/lp_aon_struct.h"
#include "soc/pcr_reg.h"
#include "soc/hp_system_reg.h"
#include "soc/assist_debug_reg.h"
#include "esp_attr.h"
//TODO: [ESP32H4] IDF-12484, need check
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -29,31 +30,62 @@ FORCE_INLINE_ATTR void cpu_utility_ll_reset_cpu(uint32_t cpu_no)
#if SOC_CPU_CORES_NUM > 1 // We only allow stalling/unstalling of other cores
FORCE_INLINE_ATTR void cpu_utility_ll_stall_cpu(uint32_t cpu_no)
{
(void)cpu_no;
abort();
if (cpu_no == 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.cpucore_cfg, aon_cpu_core0_sw_stall, 0x86);
while(!REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE0_RUNSTALLED));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.cpucore_cfg, aon_cpu_core1_sw_stall, 0x86);
while(!REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE1_RUNSTALLED));
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
{
(void)cpu_no;
abort();
if (cpu_no == 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.cpucore_cfg, aon_cpu_core0_sw_stall, 0xFF);
while(REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE0_RUNSTALLED));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.cpucore_cfg, aon_cpu_core1_sw_stall, 0xFF);
while(REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE1_RUNSTALLED));
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_debug(uint32_t cpu_no)
{
(void)cpu_no;
abort();
if (cpu_no == 0) {
REG_SET_BIT(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN);
} else {
REG_SET_BIT(ASSIST_DEBUG_CORE_1_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN);
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_record(uint32_t cpu_no)
{
(void)cpu_no;
abort();
if (cpu_no == 0) {
REG_SET_BIT(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
} else {
REG_SET_BIT(ASSIST_DEBUG_CORE_1_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_RECORDEN);
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
{
abort();
if (!REG_GET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN)) {
REG_SET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN);
}
if (REG_GET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_RST_EN)) {
REG_CLR_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_RST_EN);
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu_int_matrix(void)
{
if (!REG_GET_BIT(PCR_INTMTX_CONF_REG, PCR_INTMTX_CORE1_CLK_EN)) {
REG_SET_BIT(PCR_INTMTX_CONF_REG, PCR_INTMTX_CORE1_CLK_EN);
}
if (REG_GET_BIT(PCR_INTMTX_CONF_REG, PCR_INTMTX_CORE1_RST_EN)) {
REG_CLR_BIT(PCR_INTMTX_CONF_REG, PCR_INTMTX_CORE1_RST_EN);
}
}
#endif // SOC_CPU_CORES_NUM > 1

25
components/hal/esp32h4/include/hal/crosscore_int_ll.h
View File

@ -8,8 +8,6 @@
#include "esp_attr.h"
#include "soc/intpri_reg.h"
//TODO: [ESP32H4] IDF-12303 inherited from verification branch, need check
#ifdef __cplusplus
extern "C" {
#endif
@ -19,7 +17,11 @@ extern "C" {
*/
FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
{
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0);
if (core_id == 0) {
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0);
} else {
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_1_REG, 0);
}
}
@ -30,7 +32,12 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
*/
FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
{
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0);
if (core_id == 0) {
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0);
} else {
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_1_REG, INTPRI_CPU_INTR_FROM_CPU_1);
}
}
@ -44,7 +51,15 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
*/
FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
{
return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG);
uint32_t reg = 0;
if (core_id == 0) {
reg = REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG);
} else {
reg = REG_READ(INTPRI_CPU_INTR_FROM_CPU_1_REG);
}
return reg;
}

4
components/hal/esp32h4/include/hal/mwdt_ll.h
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@ -24,10 +24,8 @@ extern "C" {
#include "esp_assert.h"
#include "hal/misc.h"
//TODO: [ESP32H4] IDF-12293 inherited from verification branch, need check
/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
#define MWDT_LL_DEFAULT_CLK_PRESCALER 20000
#define MWDT_LL_DEFAULT_CLK_PRESCALER 16000
/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
#define TIMG_WDT_WKEY_VALUE 0x50D83AA1

4
components/hal/esp32p4/include/hal/cpu_utility_ll.h
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@ -79,6 +79,10 @@ FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu_int_matrix(void)
{
}
#endif // SOC_CPU_CORES_NUM > 1
FORCE_INLINE_ATTR uint32_t cpu_utility_ll_wait_mode(void)

4
components/hal/esp32s3/include/hal/cpu_utility_ll.h
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@ -94,6 +94,10 @@ FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu_int_matrix(void)
{
}
#endif // SOC_CPU_CORES_NUM > 1
#ifdef __cplusplus

4
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
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@ -39,6 +39,10 @@ config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_WDT_SUPPORTED
bool
default y
config SOC_SPI_FLASH_SUPPORTED
bool
default y

31
components/soc/esp32h4/include/soc/assist_debug_reg.h Normal file
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@ -0,0 +1,31 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/bus_monitor_reg.h"
// Compatible alias
#define DR_REG_ASSIST_DEBUG_BASE DR_REG_BUS_MONITOR_BASE
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG BUS_MONITOR_CORE_0_DEBUG_MODE_REG
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG BUS_MONITOR_CORE_0_SP_MIN_REG
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG BUS_MONITOR_CORE_0_SP_MAX_REG
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG BUS_MONITOR_CORE_0_RCD_EN_REG
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN BUS_MONITOR_CORE_0_RCD_PDEBUGEN
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN BUS_MONITOR_CORE_0_RCD_RECORDEN
#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG BUS_MONITOR_CORE_1_DEBUG_MODE_REG
#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE
#define ASSIST_DEBUG_CORE_1_SP_MIN_REG BUS_MONITOR_CORE_1_SP_MIN_REG
#define ASSIST_DEBUG_CORE_1_SP_MAX_REG BUS_MONITOR_CORE_1_SP_MAX_REG
#define ASSIST_DEBUG_CORE_1_RCD_EN_REG BUS_MONITOR_CORE_1_RCD_EN_REG
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN BUS_MONITOR_CORE_1_RCD_PDEBUGEN
#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN BUS_MONITOR_CORE_1_RCD_RECORDEN

2
components/soc/esp32h4/include/soc/clk_tree_defs.h
View File

@ -247,7 +247,7 @@ typedef enum {
MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MWDT_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL fixed 48MHz as the source clock */
MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 48MHz as the default clock choice */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////

3
components/soc/esp32h4/include/soc/soc_caps.h
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@ -47,7 +47,6 @@
// #define SOC_LP_CORE_SUPPORTED 0
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32H4] IDF-12268
#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12268
// #define SOC_RTC_FAST_MEM_SUPPORTED 0
// #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12313
// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32H4] IDF-12385
// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12402
@ -77,7 +76,7 @@
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32H4] IDF-12445 IDF-12451
// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12285
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32H4] IDF-12310
// #define SOC_WDT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12293
#define SOC_WDT_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32H4] IDF-12388
// #define SOC_SPIRAM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12351

7
components/soc/esp32h4/include/soc/system_reg.h
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@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/hp_system_reg.h"
#include "soc/intpri_reg.h"
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
@ -12,3 +11,9 @@
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG INTPRI_CPU_INTR_FROM_CPU_1_REG
#define SYSTEM_CPU_INTR_FROM_CPU_1 INTPRI_CPU_INTR_FROM_CPU_1
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG INTPRI_CPU_INTR_FROM_CPU_2_REG
#define SYSTEM_CPU_INTR_FROM_CPU_2 INTPRI_CPU_INTR_FROM_CPU_2
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG INTPRI_CPU_INTR_FROM_CPU_3_REG
#define SYSTEM_CPU_INTR_FROM_CPU_3 INTPRI_CPU_INTR_FROM_CPU_3

1
components/soc/esp32h4/register/soc/intpri_reg.h
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@ -5,7 +5,6 @@
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {

37
components/soc/esp32h4/wdt_periph.c Normal file
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@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/wdt_periph.h"
#include "soc/soc_caps.h"
#if SOC_PAU_SUPPORTED
#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG
static const regdma_entries_config_t tg0_wdt_regs_retention[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
};
static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
};
const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
[0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
[1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
};
#endif // SOC_PAU_SUPPORTED

14
components/soc/esp32p4/include/soc/system_reg.h
View File

@ -1,6 +1,18 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/hp_system_reg.h"
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG HP_SYSTEM_CPU_INT_FROM_CPU_0_REG
#define SYSTEM_CPU_INTR_FROM_CPU_0 HP_SYSTEM_CPU_INT_FROM_CPU_0
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG HP_SYSTEM_CPU_INT_FROM_CPU_1_REG
#define SYSTEM_CPU_INTR_FROM_CPU_1 HP_SYSTEM_CPU_INT_FROM_CPU_1
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG HP_SYSTEM_CPU_INT_FROM_CPU_2_REG
#define SYSTEM_CPU_INTR_FROM_CPU_2 HP_SYSTEM_CPU_INT_FROM_CPU_2
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG HP_SYSTEM_CPU_INT_FROM_CPU_3_REG
#define SYSTEM_CPU_INTR_FROM_CPU_3 HP_SYSTEM_CPU_INT_FROM_CPU_3