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feat(soc): add esp32h4 PAU initial support

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This commit is contained in:
wuzhenghui
2025-06-20 20:11:01 +08:00
parent 5d8e56b4c9
commit ee9c1aee81
5 changed files with 111 additions and 3 deletions
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12
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
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@@ -43,6 +43,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED
bool
default y
config SOC_WDT_SUPPORTED
bool
default y
@@ -531,6 +535,14 @@ config SOC_PM_PAU_LINK_NUM
int
default 4
config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
bool
default y
config SOC_PM_RETENTION_MODULE_NUM
int
default 32
config SOC_MODEM_CLOCK_IS_INDEPENDENT
bool
default y

93
components/soc/esp32h4/include/soc/retention_periph_defs.h Normal file
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@@ -0,0 +1,93 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_MIN = 0,
SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */
/* clock module, which includes system and modem */
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2,
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
* TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
SLEEP_RETENTION_MODULE_SYS_PERIPH = 3,
/* Timer Group by target*/
SLEEP_RETENTION_MODULE_TG0_WDT = 4,
SLEEP_RETENTION_MODULE_TG1_WDT = 5,
SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6,
SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7,
/* GDMA by channel */
SLEEP_RETENTION_MODULE_GDMA_CH0 = 8,
SLEEP_RETENTION_MODULE_GDMA_CH1 = 9,
SLEEP_RETENTION_MODULE_GDMA_CH2 = 10,
SLEEP_RETENTION_MODULE_GDMA_CH3 = 11,
SLEEP_RETENTION_MODULE_GDMA_CH4 = 12,
/* MISC Peripherals */
SLEEP_RETENTION_MODULE_ADC = 13,
SLEEP_RETENTION_MODULE_I2C0 = 14,
SLEEP_RETENTION_MODULE_I2C1 = 15,
SLEEP_RETENTION_MODULE_RMT0 = 16,
SLEEP_RETENTION_MODULE_UART0 = 17,
SLEEP_RETENTION_MODULE_UART1 = 18,
SLEEP_RETENTION_MODULE_I2S0 = 19,
SLEEP_RETENTION_MODULE_ETM0 = 20,
SLEEP_RETENTION_MODULE_TEMP_SENSOR = 21,
SLEEP_RETENTION_MODULE_TWAI0 = 22,
SLEEP_RETENTION_MODULE_PARLIO0 = 23,
SLEEP_RETENTION_MODULE_GPSPI2 = 24,
SLEEP_RETENTION_MODULE_LEDC = 25,
SLEEP_RETENTION_MODULE_PCNT0 = 26,
SLEEP_RETENTION_MODULE_MCPWM0 = 27,
/* Modem module, which includes BLE and 802.15.4 */
SLEEP_RETENTION_MODULE_BLE_MAC = 28,
SLEEP_RETENTION_MODULE_BT_BB = 29,
SLEEP_RETENTION_MODULE_802154_MAC = 30,
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
#define is_top_domain_module(m) \
( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \
: ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \
: ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GDMA_CH2) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GDMA_CH3) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GDMA_CH4) ? true \
: ((m) == SLEEP_RETENTION_MODULE_ADC) ? true \
: ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_I2C1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \
: ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \
: ((m) == SLEEP_RETENTION_MODULE_PCNT0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \
: false)
#ifdef __cplusplus
}
#endif

6
components/soc/esp32h4/include/soc/soc_caps.h
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@@ -69,7 +69,7 @@
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32H4] IDF-12295
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12256
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32H4] IDF-12286
// #define SOC_PAU_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32H4] IDF-12274
// #define SOC_LP_AON_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
@@ -531,7 +531,9 @@
// #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
// #define SOC_PM_RETENTION_HAS_CLOCK_BUG (1)
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
#define SOC_PM_RETENTION_MODULE_NUM (32)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) // TODO: [ESP32H4] IDF-12285

2
components/soc/esp32h4/wdt_periph.c
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@@ -7,7 +7,7 @@
#include "soc/wdt_periph.h"
#include "soc/soc_caps.h"
#if SOC_PAU_SUPPORTED
#if SOC_PAU_SUPPORTED && SOC_MWDT_SUPPORT_SLEEP_RETENTION
#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG

1
components/soc/include/soc/regdma.h
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@@ -48,6 +48,7 @@ extern "C" {
#define REGDMA_MODEM_BT_BB_LINK(_pri) ((0x15 << 8) | _pri)
#define REGDMA_MODEM_IEEE802154_LINK(_pri) ((0x16 << 8) | _pri)
#define REGDMA_GDMA_LINK(_pri) ((0x17 << 8) | _pri)
#define REGDMA_AHB_DMA_LINK(_pri) ((0x17 << 8) | _pri)
#define REGDMA_I2C_LINK(_pri) ((0x18 << 8) | _pri)
#define REGDMA_RMT_LINK(_pri) ((0x19 << 8) | _pri)
#define REGDMA_TG0_WDT_LINK(_pri) ((0x1A << 8) | _pri)