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Merge branch 'feature/support_esp32s3_728_gpio_driver' into 'master'

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gpio: update gpio driver to support esp32s3

Closes IDF-3224 and IDF-3273

See merge request espressif/esp-idf!13942
This commit is contained in:
Michael (XIAO Xufeng)
2021-06-28 09:49:01 +00:00
parent 574fd8b68f 78c67d2384
commit fc2905384c
10 changed files with 512 additions and 388 deletions
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99
components/driver/test/test_gpio.c
View File

@@ -30,6 +30,8 @@
#define TEST_GPIO_OUTPUT_PIN 23 #define TEST_GPIO_OUTPUT_PIN 23
#define TEST_GPIO_INPUT_ONLY_PIN 34 #define TEST_GPIO_INPUT_ONLY_PIN 34
#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_34 #define TEST_GPIO_OUTPUT_MAX GPIO_NUM_34
#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 2
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 4
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
// ESP32_S2 DEVKIC uses IO19 and IO20 as USB functions, so it is necessary to avoid using IO19, otherwise GPIO io pull up/down function cannot pass // ESP32_S2 DEVKIC uses IO19 and IO20 as USB functions, so it is necessary to avoid using IO19, otherwise GPIO io pull up/down function cannot pass
// Also the first version of ESP32-S2-Saola has pullup issue on GPIO18, which is tied to 3V3 on the // Also the first version of ESP32-S2-Saola has pullup issue on GPIO18, which is tied to 3V3 on the
@@ -39,20 +41,32 @@
#define TEST_GPIO_OUTPUT_PIN 12 #define TEST_GPIO_OUTPUT_PIN 12
#define TEST_GPIO_INPUT_ONLY_PIN 46 #define TEST_GPIO_INPUT_ONLY_PIN 46
#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_46 #define TEST_GPIO_OUTPUT_MAX GPIO_NUM_46
#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 17
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 1
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
// IO19 and IO20 are connected as USB functions and should be avoided for testing // IO19 and IO20 are connected as USB functions.
#define TEST_GPIO_EXT_OUT_IO 17 // default output GPIO #define TEST_GPIO_EXT_OUT_IO 17 // default output GPIO
#define TEST_GPIO_EXT_IN_IO 21 // default input GPIO #define TEST_GPIO_EXT_IN_IO 21 // default input GPIO
#define TEST_GPIO_OUTPUT_PIN 12 #define TEST_GPIO_OUTPUT_PIN 12
#define TEST_GPIO_INPUT_ONLY_PIN 46
#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX #define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX
#define TEST_GPIO_USB_DM_IO 19 // USB D- GPIO
#define TEST_GPIO_USB_DP_IO 20 // USB D+ GPIO
#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 17
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 1
#elif CONFIG_IDF_TARGET_ESP32C3 #elif CONFIG_IDF_TARGET_ESP32C3
#define TEST_GPIO_EXT_OUT_IO 2 // default output GPIO #define TEST_GPIO_EXT_OUT_IO 2 // default output GPIO
#define TEST_GPIO_EXT_IN_IO 3 // default input GPIO #define TEST_GPIO_EXT_IN_IO 3 // default input GPIO
#define TEST_GPIO_OUTPUT_PIN 1 #define TEST_GPIO_OUTPUT_PIN 1
#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_21 #define TEST_GPIO_OUTPUT_MAX GPIO_NUM_21
#define TEST_GPIO_USB_DM_IO 18 // USB D- GPIO
#define TEST_GPIO_USB_DP_IO 19 // USB D+ GPIO
#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 10
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN 1
#endif #endif
// If there is any input-only pin, enable input-only pin part of some tests.
#define SOC_HAS_INPUT_ONLY_PIN (CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2)
// define public test io on all boards(esp32, esp32s2, esp32s3, esp32c3) // define public test io on all boards(esp32, esp32s2, esp32s3, esp32c3)
#define TEST_IO_9 GPIO_NUM_9 #define TEST_IO_9 GPIO_NUM_9
#define TEST_IO_10 GPIO_NUM_10 #define TEST_IO_10 GPIO_NUM_10
@@ -82,16 +96,16 @@ static gpio_config_t init_io(gpio_num_t num)
return io_conf; return io_conf;
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
//No runners
// edge interrupt event // edge interrupt event
static void gpio_isr_edge_handler(void* arg) __attribute__((unused)) static void gpio_isr_edge_handler(void *arg)
{ {
uint32_t gpio_num = (uint32_t) arg; uint32_t gpio_num = (uint32_t) arg;
esp_rom_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num)); esp_rom_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num));
edge_intr_times++; edge_intr_times++;
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
//No runners
// level interrupt event with "gpio_intr_disable" // level interrupt event with "gpio_intr_disable"
static void gpio_isr_level_handler(void *arg) static void gpio_isr_level_handler(void *arg)
{ {
@@ -172,7 +186,7 @@ static void drive_capability_set_get(gpio_num_t num, gpio_drive_cap_t capability
TEST_CASE("GPIO config parameters test", "[gpio]") TEST_CASE("GPIO config parameters test", "[gpio]")
{ {
//error param test //error param test
//ESP32 test 41 bit, ESP32-S2 test 48 bit, ESP32-S3 test 49 bit //ESP32 test 41 bit, ESP32-S2 test 48 bit, ESP32-S3 test 50 bit
gpio_config_t io_config = { 0 }; gpio_config_t io_config = { 0 };
io_config.intr_type = GPIO_INTR_DISABLE; io_config.intr_type = GPIO_INTR_DISABLE;
io_config.pin_bit_mask = ((uint64_t)1 << (GPIO_NUM_MAX + 1)); io_config.pin_bit_mask = ((uint64_t)1 << (GPIO_NUM_MAX + 1));
@@ -182,22 +196,22 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
io_config.pin_bit_mask = 0; io_config.pin_bit_mask = 0;
TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG); TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
//ESP32 test 40 bit, ESP32-S2 test 47 bit, ESP32-S3 test 48 bit //ESP32 test 40 bit, ESP32-S2 test 47 bit, ESP32-S3 test 49 bit
io_config.pin_bit_mask = ((uint64_t)1 << GPIO_NUM_MAX); io_config.pin_bit_mask = ((uint64_t)1 << GPIO_NUM_MAX);
TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG); TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_OUTPUT_PIN); io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_OUTPUT_PIN);
TEST_ESP_OK(gpio_config(&io_config)); TEST_ESP_OK(gpio_config(&io_config));
//This IO is just used for input, C3 doesn't have input only pin. //This IO is just used for input, C3 and S3 doesn't have input only pin.
#if !CONFIG_IDF_TARGET_ESP32C3 #if SOC_HAS_INPUT_ONLY_PIN
io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN); io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN);
io_config.mode = GPIO_MODE_INPUT; io_config.mode = GPIO_MODE_INPUT;
TEST_ESP_OK(gpio_config(&io_config)); TEST_ESP_OK(gpio_config(&io_config));
io_config.mode = GPIO_MODE_OUTPUT; io_config.mode = GPIO_MODE_OUTPUT;
// The pin is input only, once set as output should log something // The pin is input only, once set as output should log something
TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG); TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
#endif //!CONFIG_IDF_TARGET_ESP32C3 #endif // SOC_HAS_INPUT_ONLY_PIN
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
@@ -395,9 +409,9 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) #endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
// ESP32 Connect GPIO18 with GPIO19, ESP32-S2 Connect GPIO17 with GPIO21, // ESP32 Connect GPIO18 with GPIO19, ESP32-S2 Connect GPIO17 with GPIO21,
// ESP32-S3 Connect GPIO19 with GPIO20, ESP32C3 Connect GPIO2 with GPIO3 // ESP32-S3 Connect GPIO17 with GPIO21, ESP32C3 Connect GPIO2 with GPIO3
// use multimeter to test the voltage, so it is ignored in CI // use multimeter to test the voltage, so it is ignored in CI
TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]") TEST_CASE("GPIO set gpio output level test", "[gpio][ignore][UT_T1_GPIO]")
{ {
gpio_config_t io_conf; gpio_config_t io_conf;
io_conf.intr_type = GPIO_INTR_DISABLE; io_conf.intr_type = GPIO_INTR_DISABLE;
@@ -419,30 +433,30 @@ TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
// tested voltage is around 3.3v // tested voltage is around 3.3v
TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(TEST_GPIO_EXT_IN_IO), 1, "get level error! the level should be high!"); TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(TEST_GPIO_EXT_IN_IO), 1, "get level error! the level should be high!");
//This IO is just used for input, C3 doesn't have input only pin. //This IO is just used for input, C3 and S3 doesn't have input only pin.
#if !CONFIG_IDF_TARGET_ESP32C3 #if SOC_HAS_INPUT_ONLY_PIN
io_conf.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN); io_conf.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN);
io_conf.mode = GPIO_MODE_OUTPUT; io_conf.mode = GPIO_MODE_OUTPUT;
gpio_config(&io_conf); gpio_config(&io_conf);
TEST_ASSERT(gpio_config(&io_conf) == ESP_ERR_INVALID_ARG); TEST_ASSERT(gpio_config(&io_conf) == ESP_ERR_INVALID_ARG);
#endif //!CONFIG_IDF_TARGET_ESP32C3 #endif // SOC_HAS_INPUT_ONLY_PIN
} }
// gpio17 connects to 3.3v pin, gpio19 connects to the GND pin // TEST_GPIO_INPUT_LEVEL_HIGH_PIN connects to 3.3v pin, TEST_GPIO_INPUT_LEVEL_LOW_PIN connects to the GND pin
// use multimeter to test the voltage, so it is ignored in CI // use multimeter to test the voltage, so it is ignored in CI
TEST_CASE("GPIO get input level test", "[gpio][ignore]") TEST_CASE("GPIO get input level test", "[gpio][ignore]")
{ {
gpio_num_t num = 17; gpio_num_t num1 = TEST_GPIO_INPUT_LEVEL_HIGH_PIN;
int level = gpio_get_level(num); int level1 = gpio_get_level(num1);
printf("gpio17's level is: %d\n", level); printf("TEST_GPIO_INPUT_LEVEL_HIGH_PIN's level is: %d\n", level1);
TEST_ASSERT_EQUAL_INT_MESSAGE(level, 1, "get level error! the level should be high!"); TEST_ASSERT_EQUAL_INT_MESSAGE(level1, 1, "get level error! the level should be high!");
gpio_num_t num2 = 19; gpio_num_t num2 = TEST_GPIO_INPUT_LEVEL_LOW_PIN;
int level2 = gpio_get_level(num2); int level2 = gpio_get_level(num2);
printf("gpio19's level is: %d\n", level2); printf("TEST_GPIO_INPUT_LEVEL_LOW_PIN's level is: %d\n", level2);
TEST_ASSERT_EQUAL_INT_MESSAGE(level2, 0, "get level error! the level should be low!"); TEST_ASSERT_EQUAL_INT_MESSAGE(level2, 0, "get level error! the level should be low!");
printf("the memory get: %d\n", esp_get_free_heap_size()); printf("the memory get: %d\n", esp_get_free_heap_size());
//when case finish, get the result from multimeter, the pin17 is 3.3v, the pin19 is 0.00v //when case finish, get the result from multimeter, the TEST_GPIO_INPUT_LEVEL_HIGH_PIN is 3.3v, the TEST_GPIO_INPUT_LEVEL_LOW_PIN is 0.00v
} }
TEST_CASE("GPIO io pull up/down function", "[gpio]") TEST_CASE("GPIO io pull up/down function", "[gpio]")
@@ -472,7 +486,7 @@ TEST_CASE("GPIO io pull up/down function", "[gpio]")
//No runners //No runners
TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]") TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
{ {
//ESP32 connect io18 and io19, ESP32-S2 connect io17 and io21, ESP32-S3 connect io19 and io20, ESP32C3 Connect GPIO2 with GPIO3 //ESP32 connect io18 and io19, ESP32-S2 connect io17 and io21, ESP32-S3 connect io17 and io21, ESP32C3 Connect GPIO2 with GPIO3
gpio_config_t output_io = init_io(TEST_GPIO_EXT_OUT_IO); gpio_config_t output_io = init_io(TEST_GPIO_EXT_OUT_IO);
gpio_config_t input_io = init_io(TEST_GPIO_EXT_IN_IO); gpio_config_t input_io = init_io(TEST_GPIO_EXT_IN_IO);
gpio_config(&output_io); gpio_config(&output_io);
@@ -668,7 +682,6 @@ TEST_CASE("GPIO drive capability test", "[gpio][ignore]")
} }
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
void gpio_enable_task(void *param) void gpio_enable_task(void *param)
{ {
int gpio_num = (int)param; int gpio_num = (int)param;
@@ -717,7 +730,6 @@ TEST_CASE("GPIO Enable/Disable interrupt on multiple cores", "[gpio][ignore]")
gpio_uninstall_isr_service(); gpio_uninstall_isr_service();
TEST_ASSERT(edge_intr_times == 2); TEST_ASSERT(edge_intr_times == 2);
} }
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
#endif //!CONFIG_FREERTOS_UNICORE #endif //!CONFIG_FREERTOS_UNICORE
typedef struct { typedef struct {
@@ -790,3 +802,38 @@ TEST_CASE("GPIO ISR service test", "[gpio][ignore]")
gpio_uninstall_isr_service(); gpio_uninstall_isr_service();
TEST_ASSERT((io9_param.isr_cnt == 1) && (io10_param.isr_cnt == 1)); TEST_ASSERT((io9_param.isr_cnt == 1) && (io10_param.isr_cnt == 1));
} }
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
TEST_CASE("GPIO input and output of USB pins test", "[gpio]")
{
const int test_pins[] = {TEST_GPIO_USB_DP_IO, TEST_GPIO_USB_DM_IO};
gpio_config_t io_conf = {
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_INPUT_OUTPUT,
.pin_bit_mask = (BIT64(test_pins[0]) | BIT64(test_pins[1])),
.pull_down_en = 0,
.pull_up_en = 0,
};
gpio_config(&io_conf);
for (int i = 0; i < sizeof(test_pins) / sizeof(int); i++) {
int pin = test_pins[i];
// test pin
gpio_set_level(pin, 0);
// tested voltage is around 0v
TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 0, "get level error! the level should be low!");
vTaskDelay(1000 / portTICK_RATE_MS);
gpio_set_level(pin, 1);
// tested voltage is around 3.3v
TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 1, "get level error! the level should be high!");
vTaskDelay(1000 / portTICK_RATE_MS);
gpio_set_level(pin, 0);
// tested voltage is around 0v
TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 0, "get level error! the level should be low!");
vTaskDelay(1000 / portTICK_RATE_MS);
gpio_set_level(pin, 1);
// tested voltage is around 3.3v
TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 1, "get level error! the level should be high!");
}
}
#endif //CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3

6
components/driver/test/test_sigmadelta.c
View File

@@ -41,7 +41,7 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
int8_t duty = 0; int8_t duty = 0;
int inc = 1; int inc = 1;
for (int i = 0; i < 1000; i++) { for (int i = 0; i < 1000; i++) {
sigmadelta_set_duty(0, duty); sigmadelta_set_duty(sigmadelta_cfg.channel, duty);
vTaskDelay(10 / portTICK_PERIOD_MS); vTaskDelay(10 / portTICK_PERIOD_MS);
duty += inc; duty += inc;
@@ -52,7 +52,7 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
TEST_ESP_OK(sigmadelta_set_prescale(0, 200)); TEST_ESP_OK(sigmadelta_set_prescale(0, 200));
for (int i = 0; i < 1000; i++) { for (int i = 0; i < 1000; i++) {
sigmadelta_set_duty(0, duty); sigmadelta_set_duty(sigmadelta_cfg.channel, duty);
vTaskDelay(10 / portTICK_PERIOD_MS); vTaskDelay(10 / portTICK_PERIOD_MS);
duty += inc; duty += inc;
@@ -61,6 +61,6 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
} }
} }
TEST_ESP_OK(sigmadelta_set_pin(0, 5)); TEST_ESP_OK(sigmadelta_set_pin(sigmadelta_cfg.channel, 5));
vTaskDelay(3000 / portTICK_PERIOD_MS); vTaskDelay(3000 / portTICK_PERIOD_MS);
} }

178
components/driver/test/test_spi_master.c
View File

@@ -32,6 +32,9 @@
const static char TAG[] = "test_spi"; const static char TAG[] = "test_spi";
// There is no input-only pin on esp32c3 and esp32s3
#define TEST_SOC_HAS_INPUT_ONLY_PINS (!DISABLED_FOR_TARGETS(ESP32C3, ESP32S3))
static void check_spi_pre_n_for(int clk, int pre, int n) static void check_spi_pre_n_for(int clk, int pre, int n)
{ {
esp_err_t ret; esp_err_t ret;
@@ -96,7 +99,8 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
TEST_ASSERT(ret == ESP_OK); TEST_ASSERT(ret == ESP_OK);
} }
static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) { static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma)
{
spi_bus_config_t buscfg = { spi_bus_config_t buscfg = {
.mosi_io_num = PIN_NUM_MOSI, .mosi_io_num = PIN_NUM_MOSI,
.miso_io_num = PIN_NUM_MOSI, .miso_io_num = PIN_NUM_MOSI,
@@ -125,7 +129,8 @@ static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) {
return handle; return handle;
} }
static int spi_test(spi_device_handle_t handle, int num_bytes) { static int spi_test(spi_device_handle_t handle, int num_bytes)
{
esp_err_t ret; esp_err_t ret;
int x; int x;
bool success = true; bool success = true;
@@ -155,24 +160,34 @@ static int spi_test(spi_device_handle_t handle, int num_bytes) {
printf("Huh? Sendbuf corrupted at byte %d\n", x); printf("Huh? Sendbuf corrupted at byte %d\n", x);
TEST_ASSERT(0); TEST_ASSERT(0);
} }
if (sendbuf[x]!=recvbuf[x]) break; if (sendbuf[x] != recvbuf[x]) {
break;
}
} }
if (x != num_bytes) { if (x != num_bytes) {
int from = x - 16; int from = x - 16;
if (from<0) from=0; if (from < 0) {
from = 0;
}
success = false; success = false;
printf("Error at %d! Sent vs recved: (starting from %d)\n", x, from); printf("Error at %d! Sent vs recved: (starting from %d)\n", x, from);
for (int i = 0; i < 32; i++) { for (int i = 0; i < 32; i++) {
if (i+from<num_bytes) printf("%02X ", sendbuf[from+i]); if (i + from < num_bytes) {
printf("%02X ", sendbuf[from + i]);
}
} }
printf("\n"); printf("\n");
for (int i = 0; i < 32; i++) { for (int i = 0; i < 32; i++) {
if (i+from<num_bytes) printf("%02X ", recvbuf[from+i]); if (i + from < num_bytes) {
printf("%02X ", recvbuf[from + i]);
}
} }
printf("\n"); printf("\n");
} }
if (success) printf("Success!\n"); if (success) {
printf("Success!\n");
}
free(sendbuf); free(sendbuf);
free(recvbuf); free(recvbuf);
return success; return success;
@@ -223,7 +238,8 @@ TEST_CASE("SPI Master test", "[spi]")
} }
TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") { TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]")
{
esp_err_t ret; esp_err_t ret;
bool success = true; bool success = true;
spi_device_interface_config_t devcfg = { spi_device_interface_config_t devcfg = {
@@ -266,7 +282,7 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") {
TEST_ASSERT(success); TEST_ASSERT(success);
} }
#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored. #if TEST_SOC_HAS_INPUT_ONLY_PINS //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
static esp_err_t test_master_pins(int mosi, int miso, int sclk, int cs) static esp_err_t test_master_pins(int mosi, int miso, int sclk, int cs)
{ {
esp_err_t ret; esp_err_t ret;
@@ -328,8 +344,8 @@ TEST_CASE("spi placed on input-only pins", "[spi]")
TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, INPUT_ONLY_PIN)); TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, INPUT_ONLY_PIN));
} }
//There is no input-only pin on esp32c3, so this test could be ignored. //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
#endif //#if !DISABLED_FOR_TARGETS(ESP32C3) #endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS
TEST_CASE("spi bus setting with different pin configs", "[spi]") TEST_CASE("spi bus setting with different pin configs", "[spi]")
{ {
@@ -339,8 +355,10 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 6 iomux output pins..."); ESP_LOGI(TAG, "test 6 iomux output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD; flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
@@ -348,8 +366,10 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 4 iomux output pins..."); ESP_LOGI(TAG, "test 4 iomux output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL; flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
@@ -358,8 +378,10 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 6 output pins..."); ESP_LOGI(TAG, "test 6 output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD | SPICOMMON_BUSFLAG_GPIO_PINS; flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD | SPICOMMON_BUSFLAG_GPIO_PINS;
//swap MOSI and MISO //swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
@@ -368,113 +390,147 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 4 output pins..."); ESP_LOGI(TAG, "test 4 output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS; flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
//swap MOSI and MISO //swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored. #if TEST_SOC_HAS_INPUT_ONLY_PINS //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin..."); ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS; flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin..."); ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS; flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS;
cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin..."); ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS; flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin..."); ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS; flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS;
cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
#endif //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
#endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS
ESP_LOGI(TAG, "check native flag for 6 output pins..."); ESP_LOGI(TAG, "check native flag for 6 output pins...");
flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS; flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
//swap MOSI and MISO //swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check native flag for 4 output pins..."); ESP_LOGI(TAG, "check native flag for 4 output pins...");
flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS; flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
//swap MOSI and MISO //swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored. #if TEST_SOC_HAS_INPUT_ONLY_PINS //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin..."); ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS; flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin..."); ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS; flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
#endif //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
#endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS
ESP_LOGI(TAG, "check sclk flag..."); ESP_LOGI(TAG, "check sclk flag...");
flags_expected = SPICOMMON_BUSFLAG_SCLK; flags_expected = SPICOMMON_BUSFLAG_SCLK;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check mosi flag..."); ESP_LOGI(TAG, "check mosi flag...");
flags_expected = SPICOMMON_BUSFLAG_MOSI; flags_expected = SPICOMMON_BUSFLAG_MOSI;
cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = -1, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check miso flag..."); ESP_LOGI(TAG, "check miso flag...");
flags_expected = SPICOMMON_BUSFLAG_MISO; flags_expected = SPICOMMON_BUSFLAG_MISO;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check quad flag..."); ESP_LOGI(TAG, "check quad flag...");
flags_expected = SPICOMMON_BUSFLAG_QUAD; flags_expected = SPICOMMON_BUSFLAG_QUAD;
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1, cfg = (spi_bus_config_t) {
.max_transfer_sz = 8, .flags = flags_expected}; .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected
};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
} }
@@ -730,7 +786,9 @@ static uint8_t bitswap(uint8_t in)
uint8_t out = 0; uint8_t out = 0;
for (int i = 0; i < 8; i++) { for (int i = 0; i < 8; i++) {
out = out >> 1; out = out >> 1;
if (in&0x80) out |= 0x80; if (in & 0x80) {
out |= 0x80;
}
in = in << 1; in = in << 1;
} }
return out; return out;
@@ -748,7 +806,9 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
devcfg.clock_speed_hz = 1 * 1000 * 1000; devcfg.clock_speed_hz = 1 * 1000 * 1000;
if (lsb_first) devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST; if (lsb_first) {
devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST;
}
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi));
//connecting pins to two peripherals breaks the output, fix it. //connecting pins to two peripherals breaks the output, fix it.
@@ -830,7 +890,9 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
cmd_got = cmd_got >> (16 - cmd_bits); cmd_got = cmd_got >> (16 - cmd_bits);
swap_ptr = (uint8_t *)&addr_got; swap_ptr = (uint8_t *)&addr_got;
for (int j = 0; j < 8; j++) swap_ptr[j] = bitswap(swap_ptr[j]); for (int j = 0; j < 8; j++) {
swap_ptr[j] = bitswap(swap_ptr[j]);
}
addr_got = addr_got >> (64 - addr_bits); addr_got = addr_got >> (64 - addr_bits);
} }
@@ -1085,7 +1147,9 @@ static void sorted_array_insert(uint32_t* array, int* size, uint32_t item)
{ {
int pos; int pos;
for (pos = *size; pos > 0; pos--) { for (pos = *size; pos > 0; pos--) {
if (array[pos-1] < item) break; if (array[pos - 1] < item) {
break;
}
array[pos] = array[pos - 1]; array[pos] = array[pos - 1];
} }
array[pos] = item; array[pos] = item;

4
components/hal/esp32s3/include/hal/gpio_ll.h
View File

@@ -26,6 +26,7 @@
#include "soc/gpio_periph.h" #include "soc/gpio_periph.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h" #include "soc/rtc_io_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#include "hal/gpio_types.h" #include "hal/gpio_types.h"
#ifdef __cplusplus #ifdef __cplusplus
@@ -399,6 +400,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
*/ */
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{ {
if (pin_name == IO_MUX_GPIO19_REG || pin_name == IO_MUX_GPIO20_REG) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(pin_name, func); PIN_FUNC_SELECT(pin_name, func);
} }

5
components/hal/include/hal/gpio_types.h
View File

@@ -78,6 +78,7 @@ typedef enum {
#define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */ #define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */
#if CONFIG_IDF_TARGET_ESP32S3 #if CONFIG_IDF_TARGET_ESP32S3
#define GPIO_SEL_47 ((uint64_t)(((uint64_t)1)<<47)) /*!< Pin 47 selected */ #define GPIO_SEL_47 ((uint64_t)(((uint64_t)1)<<47)) /*!< Pin 47 selected */
#define GPIO_SEL_48 ((uint64_t)(((uint64_t)1)<<48)) /*!< Pin 48 selected */
#endif #endif
#endif #endif
@@ -129,6 +130,7 @@ typedef enum {
#define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG #define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG
#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG #define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG
#define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG #define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG
#define GPIO_PIN_REG_48 IO_MUX_GPIO48_REG
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
typedef enum { typedef enum {
@@ -269,8 +271,9 @@ typedef enum {
GPIO_NUM_43 = 43, /*!< GPIO43, input and output */ GPIO_NUM_43 = 43, /*!< GPIO43, input and output */
GPIO_NUM_44 = 44, /*!< GPIO44, input and output */ GPIO_NUM_44 = 44, /*!< GPIO44, input and output */
GPIO_NUM_45 = 45, /*!< GPIO45, input and output */ GPIO_NUM_45 = 45, /*!< GPIO45, input and output */
GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */ GPIO_NUM_46 = 46, /*!< GPIO46, input and output */
GPIO_NUM_47 = 47, /*!< GPIO47, input and output */ GPIO_NUM_47 = 47, /*!< GPIO47, input and output */
GPIO_NUM_48 = 48, /*!< GPIO48, input and output */
GPIO_NUM_MAX, GPIO_NUM_MAX,
/** @endcond */ /** @endcond */
} gpio_num_t; } gpio_num_t;

1
components/soc/esp32s3/gpio_periph.c
View File

@@ -63,6 +63,7 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO45_REG, IO_MUX_GPIO45_REG,
IO_MUX_GPIO46_REG, IO_MUX_GPIO46_REG,
IO_MUX_GPIO47_REG, IO_MUX_GPIO47_REG,
IO_MUX_GPIO48_REG,
}; };
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = { const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {

10
components/soc/esp32s3/include/soc/gpio_caps.h
View File

@@ -20,17 +20,17 @@ extern "C" {
// ESP32-S3 has 1 GPIO peripheral // ESP32-S3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1) #define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (48) #define SOC_GPIO_PIN_COUNT (49)
// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. // On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S3 // Force hold is a new function of ESP32-S3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~47 except from 22~25 are valid // 0~48 except from 22~25 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) #define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// GPIO 46 is input only // No GPIO is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46)) #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
#ifdef __cplusplus #ifdef __cplusplus

1
components/soc/esp32s3/rtc_io_periph.c
View File

@@ -63,6 +63,7 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-1,//GPIO45 -1,//GPIO45
-1,//GPIO46 -1,//GPIO46
-1,//GPIO47 -1,//GPIO47
-1,//GPIO48
}; };
//Reg,Mux,Fun,IE,Up,Down,Rtc_number //Reg,Mux,Fun,IE,Up,Down,Rtc_number

10
docs/en/api-reference/peripherals/gpio.rst
View File

@@ -6,7 +6,7 @@ Overview
.. only:: esp32 .. only:: esp32
The {IDF_TARGET_NAME} chip features 40 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal. The {IDF_TARGET_NAME} chip features 34 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.
- Note that GPIO6-11 are usually used for SPI flash. - Note that GPIO6-11 are usually used for SPI flash.
- GPIO34-39 can only be set as input mode and do not have software pullup or pulldown functions. - GPIO34-39 can only be set as input mode and do not have software pullup or pulldown functions.
@@ -26,6 +26,14 @@ Overview
- Note that GPIO 18 and 19 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers. - Note that GPIO 18 and 19 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
- {IDF_TARGET_NAME} doesn't have separate "RTC GPIO" support. However, GPIO0-5 keep the rtc feature, which can be used for power-management and analog subsystem. - {IDF_TARGET_NAME} doesn't have separate "RTC GPIO" support. However, GPIO0-5 keep the rtc feature, which can be used for power-management and analog subsystem.
.. only:: esp32s3
The {IDF_TARGET_NAME} chip features 45 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.
- Note that GPIO26-32 are usually used for SPI flash.
- Note that GPIO 19 and 20 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
- Note that when using SPI eight-line mode, GPIO33~37 are connected to IO4~IO7 and DQS. On ESP32-S3R8 / ESP32-S3R8V board GPIO33~37 are not recommended for other uses.
.. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED .. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
There is also separate "RTC GPIO" support, which functions when GPIOs are routed to the "RTC" low-power and analog subsystem. These pin functions can be used when: There is also separate "RTC GPIO" support, which functions when GPIOs are routed to the "RTC" low-power and analog subsystem. These pin functions can be used when:

10
docs/en/api-reference/peripherals/sigmadelta.rst
View File

@@ -1,6 +1,8 @@
Sigma-delta Modulation Sigma-delta Modulation
====================== ======================
{IDF_TARGET_SIGMA_DELTA_MODULATION_CHANNEL_NUM:default="8", esp32c3="4"}
Introduction Introduction
------------ ------------
@@ -9,13 +11,7 @@ Introduction
Functionality Overview Functionality Overview
---------------------- ----------------------
.. only:: esp32 or esp32s2 There are {IDF_TARGET_SIGMA_DELTA_MODULATION_CHANNEL_NUM} independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
There are eight independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
.. only:: esp32c3
There are four independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
Selected channel should be set up by providing configuration parameters in :cpp:type:`sigmadelta_config_t` and then applying this configuration with :cpp:func:`sigmadelta_config`. Selected channel should be set up by providing configuration parameters in :cpp:type:`sigmadelta_config_t` and then applying this configuration with :cpp:func:`sigmadelta_config`.