forked from espressif/arduino-esp32
update idf libs, disable WDT on S2, use malloc for PSRAM
This commit is contained in:
me-no-dev
@ -20,6 +20,7 @@
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#define CONFIG_BOOTLOADER_SPI_WP_PIN 7
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#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
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#define CONFIG_BOOTLOADER_WDT_ENABLE 1
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#define CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE 1
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#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
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#define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1
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#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10
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@ -93,9 +94,12 @@
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#define CONFIG_SPIRAM_SIZE -1
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#define CONFIG_DEFAULT_PSRAM_CLK_IO 30
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#define CONFIG_DEFAULT_PSRAM_CS_IO 26
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#define CONFIG_SPIRAM_SPEED_40M 1
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#define CONFIG_SPIRAM_SPEED_80M 1
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#define CONFIG_SPIRAM 1
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#define CONFIG_SPIRAM_USE_CAPS_ALLOC 1
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#define CONFIG_SPIRAM_USE_MALLOC 1
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#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 4096
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#define CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP 1
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#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
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#define CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM 0x0
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#define CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO 1
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#define CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES 2
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@ -119,11 +123,10 @@
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#define CONFIG_ESP_CONSOLE_UART_RX_GPIO 44
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#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200
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#define CONFIG_ESP_INT_WDT 1
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#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300
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#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 1000
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#define CONFIG_ESP_TASK_WDT 1
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#define CONFIG_ESP_TASK_WDT_PANIC 1
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#define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5
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#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
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#define CONFIG_ETH_ENABLED 1
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@ -144,9 +147,9 @@
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#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
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#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 16
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#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
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#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
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#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
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#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
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#define CONFIG_ESP32_WIFI_STATIC_TX_BUFFER 1
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#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 0
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#define CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM 16
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#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
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#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
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#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
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@ -262,6 +265,8 @@
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#define CONFIG_MBEDTLS_AES_USE_INTERRUPT 1
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#define CONFIG_MBEDTLS_HARDWARE_GCM 1
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#define CONFIG_MBEDTLS_HAVE_TIME 1
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#define CONFIG_MBEDTLS_ECDSA_DETERMINISTIC 1
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#define CONFIG_MBEDTLS_SHA512_C 1
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#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1
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#define CONFIG_MBEDTLS_TLS_SERVER 1
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#define CONFIG_MBEDTLS_TLS_CLIENT 1
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@ -312,6 +317,7 @@
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#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1
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#define CONFIG_MDNS_MAX_SERVICES 10
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#define CONFIG_MDNS_TASK_PRIORITY 1
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#define CONFIG_MDNS_TASK_STACK_SIZE 4096
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#define CONFIG_MDNS_TASK_AFFINITY_CPU0 1
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#define CONFIG_MDNS_TASK_AFFINITY 0x0
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#define CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS 2000
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@ -422,7 +428,6 @@
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#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
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#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
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#define CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT
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#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
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#define CONFIG_TASK_WDT_PANIC CONFIG_ESP_TASK_WDT_PANIC
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#define CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S
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#define CONFIG_TCPIP_RECVMBOX_SIZE CONFIG_LWIP_TCPIP_RECVMBOX_SIZE
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@ -64,6 +64,7 @@ typedef enum {
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ESP_SLEEP_WAKEUP_ULP, //!< Wakeup caused by ULP program
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ESP_SLEEP_WAKEUP_GPIO, //!< Wakeup caused by GPIO (light sleep only)
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ESP_SLEEP_WAKEUP_UART, //!< Wakeup caused by UART (light sleep only)
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ESP_SLEEP_WAKEUP_WIFI, //!< Wakeup caused by WIFI (light sleep only)
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} esp_sleep_source_t;
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/* Leave this type define for compatibility */
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@ -239,6 +240,13 @@ esp_err_t esp_sleep_enable_uart_wakeup(int uart_num);
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*/
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uint64_t esp_sleep_get_ext1_wakeup_status(void);
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/**
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* @brief Enable wakeup by WiFi MAC
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* @return
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* - ESP_OK on success
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*/
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esp_err_t esp_sleep_enable_wifi_wakeup(void);
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/**
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* @brief Set power down mode for an RTC power domain in sleep mode
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*
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@ -349,7 +357,6 @@ esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void);
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*/
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void esp_default_wake_deep_sleep(void);
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#ifdef __cplusplus
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}
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#endif
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@ -109,6 +109,38 @@ void esp_pm_impl_dump_stats(FILE* out);
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*/
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void esp_pm_impl_waiti(void);
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#if CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief Callback function type for peripherals to skip light sleep.
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*
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*/
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typedef bool (* skip_light_sleep_cb_t)(void);
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/**
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* @brief Register peripherals skip light sleep callback
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*
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* This function allows you to register a callback that gets the result
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* that if light sleep should be skipped by peripherals.
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* @param cb function to get the result
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* @return
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* - ESP_OK on success
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* - ESP_ERR_NO_MEM if no more callback slots are available
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*/
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esp_err_t esp_pm_register_skip_light_sleep_callback(skip_light_sleep_cb_t cb);
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/**
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* @brief Unregisterperipherals skip light sleep callback
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*
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* This function allows you to unregister a callback which was previously
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* registered using esp_register_skip_light_sleep_callback.
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* @param cb function to get the result
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* @return
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* - ESP_OK on success
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* - ESP_ERR_INVALID_STATE if the given callback hasn't been registered before
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*/
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esp_err_t esp_pm_unregister_skip_light_sleep_callback(skip_light_sleep_cb_t cb);
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#endif
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#ifdef CONFIG_PM_PROFILING
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#define WITH_PROFILING
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#endif
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@ -73,6 +73,30 @@ struct esp_eth_mac_s {
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*/
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esp_err_t (*deinit)(esp_eth_mac_t *mac);
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/**
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* @brief Start Ethernet MAC
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*
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* @param[in] mac: Ethernet MAC instance
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*
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* @return
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* - ESP_OK: start Ethernet MAC successfully
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* - ESP_FAIL: start Ethernet MAC failed because some other error occurred
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*
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*/
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esp_err_t (*start)(esp_eth_mac_t *mac);
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/**
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* @brief Stop Ethernet MAC
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*
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* @param[in] mac: Ethernet MAC instance
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*
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* @return
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* - ESP_OK: stop Ethernet MAC successfully
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* - ESP_FAIL: stop Ethernet MAC failed because some error occurred
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*
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*/
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esp_err_t (*stop)(esp_eth_mac_t *mac);
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/**
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* @brief Transmit packet from Ethernet MAC
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*
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@ -511,6 +511,20 @@ bool esp_http_client_is_complete_data_received(esp_http_client_handle_t client);
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int esp_http_client_read_response(esp_http_client_handle_t client, char *buffer, int len);
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/**
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* @brief Get URL from client
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*
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* @param[in] client The esp_http_client handle
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* @param[inout] url The buffer to store URL
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* @param[in] len The buffer length
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*
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* @return
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* - ESP_OK
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* - ESP_FAIL
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*/
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esp_err_t esp_http_client_get_url(esp_http_client_handle_t client, char *url, const int len);
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#ifdef __cplusplus
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}
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#endif
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@ -162,7 +162,7 @@ esp_err_t esp_https_ota_finish(esp_https_ota_handle_t https_ota_handle);
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esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, esp_app_desc_t *new_app_info);
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/*
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/**
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* @brief This function returns OTA image data read so far.
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*
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* @note This API should be called only if `esp_https_ota_perform()` has been called atleast once or
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@ -402,6 +402,22 @@ esp_err_t esp_netif_set_old_ip_info(esp_netif_t *esp_netif, const esp_netif_ip_i
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*/
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int esp_netif_get_netif_impl_index(esp_netif_t *esp_netif);
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/**
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* @brief Get net interface name from network stack implementation
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*
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* @note This name could be used in `setsockopt()` to bind socket with appropriate interface
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*
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* @param[in] esp_netif Handle to esp-netif instance
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* @param[out] name Interface name as specified in underlying TCP/IP stack. Note that the
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* actual name will be copied to the specified buffer, which must be allocated to hold
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* maximum interface name size (6 characters for lwIP)
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*
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* @return
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* - ESP_OK
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* - ESP_ERR_ESP_NETIF_INVALID_PARAMS
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*/
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esp_err_t esp_netif_get_netif_impl_name(esp_netif_t *esp_netif, char* name);
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/**
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* @}
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*/
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@ -648,6 +664,17 @@ esp_err_t esp_netif_get_ip6_linklocal(esp_netif_t *esp_netif, esp_ip6_addr_t *if
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*/
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esp_err_t esp_netif_get_ip6_global(esp_netif_t *esp_netif, esp_ip6_addr_t *if_ip6);
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/**
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* @brief Get all IPv6 addresses of the specified interface
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*
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* @param[in] esp_netif Handle to esp-netif instance
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* @param[out] if_ip6 Array of IPv6 addresses will be copied to the argument
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*
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* @return
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* number of returned IPv6 addresses
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*/
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int esp_netif_get_all_ip6(esp_netif_t *esp_netif, esp_ip6_addr_t if_ip6[]);
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/**
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* @brief Sets IPv4 address to the specified octets
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*
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@ -414,6 +414,17 @@ esp_err_t esp_wifi_internal_get_negotiated_channel(wifi_interface_t ifx, uint8_t
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*/
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esp_err_t esp_wifi_internal_get_negotiated_bandwidth(wifi_interface_t ifx, uint8_t aid, uint8_t *bw);
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#if CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief Check if WiFi TSF is active
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*
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* @return
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* - true: Active
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* - false: Not active
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*/
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bool esp_wifi_internal_is_tsf_active(void);
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#endif
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#ifdef __cplusplus
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}
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#endif
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@ -57,6 +57,7 @@ typedef enum {
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WIFI_AUTH_WPA_WPA2_PSK, /**< authenticate mode : WPA_WPA2_PSK */
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WIFI_AUTH_WPA2_ENTERPRISE, /**< authenticate mode : WPA2_ENTERPRISE */
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WIFI_AUTH_WPA3_PSK, /**< authenticate mode : WPA3_PSK */
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WIFI_AUTH_WPA2_WPA3_PSK, /**< authenticate mode : WPA2_WPA3_PSK */
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WIFI_AUTH_MAX
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} wifi_auth_mode_t;
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@ -235,13 +235,14 @@ typedef QueueHandle_t SemaphoreHandle_t;
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*
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* void vATask( void * pvParameters )
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* {
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* // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
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* // Semaphore cannot be used before a call to xSemaphoreCreateBinary() or
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* // xSemaphoreCreateBinaryStatic().
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* // The semaphore's data structures will be placed in the xSemaphoreBuffer
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* // variable, the address of which is passed into the function. The
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* // function's parameter is not NULL, so the function will not attempt any
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* // dynamic memory allocation, and therefore the function will not return
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* // return NULL.
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* xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
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* xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer );
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*
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* // Rest of task code goes here.
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* }
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@ -71,23 +71,23 @@
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#define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES 565
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#endif
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_4BIT
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_4BIT 12200
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT 12200
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#endif
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_4BIT
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_4BIT 12200
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT 12200
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#endif
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_1BIT
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_1BIT 4000
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT 4000
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#endif
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_1BIT
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_1BIT 4000
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT 4000
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#endif
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_SPI
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_TOHOST_SPI 1000
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI 1000
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#endif
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_SPI
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_MBSEC_FRHOST_SPI 1000
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#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI
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#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI 1000
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#endif
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//time to perform the task selection plus context switch (from task)
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@ -400,7 +400,11 @@
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*
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* Comment this macro to disable deterministic ECDSA.
|
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*/
|
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#ifdef CONFIG_MBEDTLS_ECDSA_DETERMINISTIC
|
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#define MBEDTLS_ECDSA_DETERMINISTIC
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#else
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#undef MBEDTLS_ECDSA_DETERMINISTIC
|
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#endif
|
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|
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/**
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* \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
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@ -1692,17 +1696,19 @@
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/**
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* \def MBEDTLS_HKDF_C
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*
|
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* Disable the HKDF algorithm (RFC 5869).
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* Enable the HKDF algorithm (RFC 5869).
|
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*
|
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* Module: library/hkdf.c
|
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* Caller:
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*
|
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* Requires: MBEDTLS_MD_C
|
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*
|
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* This module adds support for the Hashed Message Authentication Code
|
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* This module enables support for the Hashed Message Authentication Code
|
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* (HMAC)-based key derivation function (HKDF).
|
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*/
|
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#ifdef MBEDTLS_HKDF_C
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#ifdef CONFIG_MBEDTLS_HKDF_C
|
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#define MBEDTLS_HKDF_C
|
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#else
|
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#undef MBEDTLS_HKDF_C
|
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#endif
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|
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@ -2026,7 +2032,11 @@
|
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*
|
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* This module adds support for SHA-384 and SHA-512.
|
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*/
|
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#ifdef CONFIG_MBEDTLS_SHA512_C
|
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#define MBEDTLS_SHA512_C
|
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#else
|
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#undef MBEDTLS_SHA512_C
|
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#endif
|
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|
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/**
|
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* \def MBEDTLS_SSL_CACHE_C
|
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@ -2368,6 +2378,62 @@
|
||||
*/
|
||||
#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE
|
||||
|
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/**
|
||||
* \def MBEDTLS_THREADING_C
|
||||
*
|
||||
* Enable the threading abstraction layer.
|
||||
* By default mbed TLS assumes it is used in a non-threaded environment or that
|
||||
* contexts are not shared between threads. If you do intend to use contexts
|
||||
* between threads, you will need to enable this layer to prevent race
|
||||
* conditions. See also our Knowledge Base article about threading:
|
||||
* https://tls.mbed.org/kb/development/thread-safety-and-multi-threading
|
||||
*
|
||||
* Module: library/threading.c
|
||||
*
|
||||
* This allows different threading implementations (self-implemented or
|
||||
* provided).
|
||||
*
|
||||
* You will have to enable either MBEDTLS_THREADING_ALT or
|
||||
* MBEDTLS_THREADING_PTHREAD.
|
||||
*
|
||||
* Enable this layer to allow use of mutexes within mbed TLS
|
||||
*/
|
||||
#ifdef CONFIG_MBEDTLS_THREADING_C
|
||||
#define MBEDTLS_THREADING_C
|
||||
#else
|
||||
#undef MBEDTLS_THREADING_C
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def MBEDTLS_THREADING_ALT
|
||||
*
|
||||
* Provide your own alternate threading implementation.
|
||||
*
|
||||
* Requires: MBEDTLS_THREADING_C
|
||||
*
|
||||
* Uncomment this to allow your own alternate threading implementation.
|
||||
*/
|
||||
#ifdef CONFIG_MBEDTLS_THREADING_ALT
|
||||
#define MBEDTLS_THREADING_ALT
|
||||
#else
|
||||
#undef MBEDTLS_THREADING_ALT
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def MBEDTLS_THREADING_PTHREAD
|
||||
*
|
||||
* Enable the pthread wrapper layer for the threading layer.
|
||||
*
|
||||
* Requires: MBEDTLS_THREADING_C
|
||||
*
|
||||
* Uncomment this to enable pthread mutexes.
|
||||
*/
|
||||
#ifdef CONFIG_MBEDTLS_THREADING_PTHREAD
|
||||
#define MBEDTLS_THREADING_PTHREAD
|
||||
#else
|
||||
#undef MBEDTLS_THREADING_PTHREAD
|
||||
#endif
|
||||
|
||||
/* \} name SECTION: Module configuration options */
|
||||
|
||||
#if defined(TARGET_LIKE_MBED)
|
||||
|
||||
@ -28,4 +28,4 @@
|
||||
|
||||
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
|
||||
|
||||
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)
|
||||
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (2)
|
||||
@ -700,7 +700,7 @@ void rtc_sleep_set_wakeup_time(uint64_t t);
|
||||
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only)
|
||||
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
|
||||
#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only)
|
||||
#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only)
|
||||
#define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI wakeup (light sleep only)
|
||||
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
|
||||
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
|
||||
#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup
|
||||
|
||||
@ -21,9 +21,11 @@
|
||||
#include "soc/usb_reg.h"
|
||||
#include "soc/usb_types.h"
|
||||
#include "soc/usb_struct.h"
|
||||
#include "soc/usb_wrap_reg.h"
|
||||
#include "soc/usb_wrap_struct.h"
|
||||
|
||||
/**
|
||||
* @brief A pin decriptor for init
|
||||
* @brief A pin descriptor for init
|
||||
*/
|
||||
typedef struct {
|
||||
const int pin;
|
||||
|
||||
@ -14,9 +14,14 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
/* GPIOs used to connect an external USB PHY */
|
||||
#define USBPHY_VP_NUM 33
|
||||
#define USBPHY_VM_NUM 34
|
||||
#define USBPHY_RCV_NUM 35
|
||||
#define USBPHY_OEN_NUM 36
|
||||
#define USBPHY_VPO_NUM 37
|
||||
#define USBPHY_VMO_NUM 38
|
||||
|
||||
/* GPIOs corresponding to the pads of the internal USB PHY */
|
||||
#define USBPHY_DP_NUM 20
|
||||
#define USBPHY_DM_NUM 19
|
||||
|
||||
@ -0,0 +1,254 @@
|
||||
/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** USB_WRAP_OTG_CONF_REG register
|
||||
* PAD/DFIFO/PHY configuration register.
|
||||
*/
|
||||
#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
|
||||
/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
|
||||
* This bit is used to enable the software override of srp session end signal.1'b0:
|
||||
* the signal is controlled by the chip input.1'b1: the signal is controlled by the
|
||||
* software.
|
||||
*/
|
||||
#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0))
|
||||
#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S)
|
||||
#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001
|
||||
#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0
|
||||
/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0;
|
||||
* Software override value of srp session end signal.
|
||||
*/
|
||||
#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1))
|
||||
#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S)
|
||||
#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001
|
||||
#define USB_WRAP_SRP_SESSEND_VALUE_S 1
|
||||
/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0;
|
||||
* Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY
|
||||
*/
|
||||
#define USB_WRAP_PHY_SEL (BIT(2))
|
||||
#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S)
|
||||
#define USB_WRAP_PHY_SEL_V 0x00000001
|
||||
#define USB_WRAP_PHY_SEL_S 2
|
||||
/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0;
|
||||
* Force the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
#define USB_WRAP_DFIFO_FORCE_PD (BIT(3))
|
||||
#define USB_WRAP_DFIFO_FORCE_PD_M (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S)
|
||||
#define USB_WRAP_DFIFO_FORCE_PD_V 0x00000001
|
||||
#define USB_WRAP_DFIFO_FORCE_PD_S 3
|
||||
/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0;
|
||||
* Bypass Debounce filters for avalid.
|
||||
*/
|
||||
#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4))
|
||||
#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S)
|
||||
#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001
|
||||
#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4
|
||||
/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0;
|
||||
* Enable software to control USB D+ D- exchange
|
||||
*/
|
||||
#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5))
|
||||
#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S)
|
||||
#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001
|
||||
#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5
|
||||
/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0;
|
||||
* USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-.
|
||||
*/
|
||||
#define USB_WRAP_EXCHG_PINS (BIT(6))
|
||||
#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S)
|
||||
#define USB_WRAP_EXCHG_PINS_V 0x00000001
|
||||
#define USB_WRAP_EXCHG_PINS_S 6
|
||||
/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0;
|
||||
* Control single-end input high threshold.
|
||||
*/
|
||||
#define USB_WRAP_VREFH 0x00000003
|
||||
#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S)
|
||||
#define USB_WRAP_VREFH_V 0x00000003
|
||||
#define USB_WRAP_VREFH_S 7
|
||||
/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0;
|
||||
* Control single-end input low threshold.
|
||||
*/
|
||||
#define USB_WRAP_VREFL 0x00000003
|
||||
#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S)
|
||||
#define USB_WRAP_VREFL_V 0x00000003
|
||||
#define USB_WRAP_VREFL_S 9
|
||||
/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0;
|
||||
* Enable software to control input threshold.
|
||||
*/
|
||||
#define USB_WRAP_VREF_OVERRIDE (BIT(11))
|
||||
#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S)
|
||||
#define USB_WRAP_VREF_OVERRIDE_V 0x00000001
|
||||
#define USB_WRAP_VREF_OVERRIDE_S 11
|
||||
/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0;
|
||||
* Enable software to control USB pad in pullup or pulldown mode.
|
||||
*/
|
||||
#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12))
|
||||
#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S)
|
||||
#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001
|
||||
#define USB_WRAP_PAD_PULL_OVERRIDE_S 12
|
||||
/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0;
|
||||
* Control USB D+ pullup.
|
||||
*/
|
||||
#define USB_WRAP_DP_PULLUP (BIT(13))
|
||||
#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S)
|
||||
#define USB_WRAP_DP_PULLUP_V 0x00000001
|
||||
#define USB_WRAP_DP_PULLUP_S 13
|
||||
/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0;
|
||||
* Control USB D+ pulldown.
|
||||
*/
|
||||
#define USB_WRAP_DP_PULLDOWN (BIT(14))
|
||||
#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S)
|
||||
#define USB_WRAP_DP_PULLDOWN_V 0x00000001
|
||||
#define USB_WRAP_DP_PULLDOWN_S 14
|
||||
/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0;
|
||||
* Control USB D+ pullup.
|
||||
*/
|
||||
#define USB_WRAP_DM_PULLUP (BIT(15))
|
||||
#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S)
|
||||
#define USB_WRAP_DM_PULLUP_V 0x00000001
|
||||
#define USB_WRAP_DM_PULLUP_S 15
|
||||
/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0;
|
||||
* Control USB D+ pulldown.
|
||||
*/
|
||||
#define USB_WRAP_DM_PULLDOWN (BIT(16))
|
||||
#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S)
|
||||
#define USB_WRAP_DM_PULLDOWN_V 0x00000001
|
||||
#define USB_WRAP_DM_PULLDOWN_S 16
|
||||
/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0;
|
||||
* Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K.
|
||||
*/
|
||||
#define USB_WRAP_PULLUP_VALUE (BIT(17))
|
||||
#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S)
|
||||
#define USB_WRAP_PULLUP_VALUE_V 0x00000001
|
||||
#define USB_WRAP_PULLUP_VALUE_S 17
|
||||
/** USB_WRAP_PAD_ENABLE : R/W; bitpos: [18]; default: 0;
|
||||
* Enable USB pad function.
|
||||
*/
|
||||
#define USB_WRAP_PAD_ENABLE (BIT(18))
|
||||
#define USB_WRAP_PAD_ENABLE_M (USB_WRAP_PAD_ENABLE_V << USB_WRAP_PAD_ENABLE_S)
|
||||
#define USB_WRAP_PAD_ENABLE_V 0x00000001
|
||||
#define USB_WRAP_PAD_ENABLE_S 18
|
||||
/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 1;
|
||||
* Force AHB clock always on.
|
||||
*/
|
||||
#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19))
|
||||
#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S)
|
||||
#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001
|
||||
#define USB_WRAP_AHB_CLK_FORCE_ON_S 19
|
||||
/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1;
|
||||
* Force PHY clock always on.
|
||||
*/
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20))
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S)
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_S 20
|
||||
/** USB_WRAP_PHY_TX_EDGE_SEL : R/W; bitpos: [21]; default: 0;
|
||||
* Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
|
||||
*/
|
||||
#define USB_WRAP_PHY_TX_EDGE_SEL (BIT(21))
|
||||
#define USB_WRAP_PHY_TX_EDGE_SEL_M (USB_WRAP_PHY_TX_EDGE_SEL_V << USB_WRAP_PHY_TX_EDGE_SEL_S)
|
||||
#define USB_WRAP_PHY_TX_EDGE_SEL_V 0x00000001
|
||||
#define USB_WRAP_PHY_TX_EDGE_SEL_S 21
|
||||
/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0;
|
||||
* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
#define USB_WRAP_DFIFO_FORCE_PU (BIT(22))
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_M (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S)
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_V 0x00000001
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_S 22
|
||||
/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Disable auto clock gating of CSR registers.
|
||||
*/
|
||||
#define USB_WRAP_CLK_EN (BIT(31))
|
||||
#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S)
|
||||
#define USB_WRAP_CLK_EN_V 0x00000001
|
||||
#define USB_WRAP_CLK_EN_S 31
|
||||
|
||||
/** USB_WRAP_TEST_CONF_REG register
|
||||
* TEST relative configuration registers.
|
||||
*/
|
||||
#define USB_WRAP_TEST_CONF_REG (DR_REG_USB_WRAP_BASE + 0x4)
|
||||
/** USB_WRAP_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
|
||||
* Enable to test the USB pad.
|
||||
*/
|
||||
#define USB_WRAP_TEST_ENABLE (BIT(0))
|
||||
#define USB_WRAP_TEST_ENABLE_M (USB_WRAP_TEST_ENABLE_V << USB_WRAP_TEST_ENABLE_S)
|
||||
#define USB_WRAP_TEST_ENABLE_V 0x00000001
|
||||
#define USB_WRAP_TEST_ENABLE_S 0
|
||||
/** USB_WRAP_TEST_USB_WRAP_OE : R/W; bitpos: [1]; default: 0;
|
||||
* USB pad oen in test.
|
||||
*/
|
||||
#define USB_WRAP_TEST_USB_WRAP_OE (BIT(1))
|
||||
#define USB_WRAP_TEST_USB_WRAP_OE_M (USB_WRAP_TEST_USB_WRAP_OE_V << USB_WRAP_TEST_USB_WRAP_OE_S)
|
||||
#define USB_WRAP_TEST_USB_WRAP_OE_V 0x00000001
|
||||
#define USB_WRAP_TEST_USB_WRAP_OE_S 1
|
||||
/** USB_WRAP_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
|
||||
* USB D+ tx value in test.
|
||||
*/
|
||||
#define USB_WRAP_TEST_TX_DP (BIT(2))
|
||||
#define USB_WRAP_TEST_TX_DP_M (USB_WRAP_TEST_TX_DP_V << USB_WRAP_TEST_TX_DP_S)
|
||||
#define USB_WRAP_TEST_TX_DP_V 0x00000001
|
||||
#define USB_WRAP_TEST_TX_DP_S 2
|
||||
/** USB_WRAP_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
|
||||
* USB D- tx value in test.
|
||||
*/
|
||||
#define USB_WRAP_TEST_TX_DM (BIT(3))
|
||||
#define USB_WRAP_TEST_TX_DM_M (USB_WRAP_TEST_TX_DM_V << USB_WRAP_TEST_TX_DM_S)
|
||||
#define USB_WRAP_TEST_TX_DM_V 0x00000001
|
||||
#define USB_WRAP_TEST_TX_DM_S 3
|
||||
/** USB_WRAP_TEST_RX_RCV : RO; bitpos: [4]; default: 0;
|
||||
* USB differential rx value in test.
|
||||
*/
|
||||
#define USB_WRAP_TEST_RX_RCV (BIT(4))
|
||||
#define USB_WRAP_TEST_RX_RCV_M (USB_WRAP_TEST_RX_RCV_V << USB_WRAP_TEST_RX_RCV_S)
|
||||
#define USB_WRAP_TEST_RX_RCV_V 0x00000001
|
||||
#define USB_WRAP_TEST_RX_RCV_S 4
|
||||
/** USB_WRAP_TEST_RX_DP : RO; bitpos: [5]; default: 0;
|
||||
* USB D+ rx value in test.
|
||||
*/
|
||||
#define USB_WRAP_TEST_RX_DP (BIT(5))
|
||||
#define USB_WRAP_TEST_RX_DP_M (USB_WRAP_TEST_RX_DP_V << USB_WRAP_TEST_RX_DP_S)
|
||||
#define USB_WRAP_TEST_RX_DP_V 0x00000001
|
||||
#define USB_WRAP_TEST_RX_DP_S 5
|
||||
/** USB_WRAP_TEST_RX_DM : RO; bitpos: [6]; default: 0;
|
||||
* USB D- rx value in test.
|
||||
*/
|
||||
#define USB_WRAP_TEST_RX_DM (BIT(6))
|
||||
#define USB_WRAP_TEST_RX_DM_M (USB_WRAP_TEST_RX_DM_V << USB_WRAP_TEST_RX_DM_S)
|
||||
#define USB_WRAP_TEST_RX_DM_V 0x00000001
|
||||
#define USB_WRAP_TEST_RX_DM_S 6
|
||||
|
||||
/** USB_WRAP_DATE_REG register
|
||||
* Version register.
|
||||
*/
|
||||
#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc)
|
||||
/** USB_WRAP_DATE : R/W; bitpos: [31:0]; default: 419631616;
|
||||
* data register.
|
||||
*/
|
||||
#define USB_WRAP_DATE 0xFFFFFFFF
|
||||
#define USB_WRAP_DATE_M (USB_WRAP_DATE_V << USB_WRAP_DATE_S)
|
||||
#define USB_WRAP_DATE_V 0xFFFFFFFF
|
||||
#define USB_WRAP_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -0,0 +1,443 @@
|
||||
/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Control/Status registers */
|
||||
/** Type of otg_conf register
|
||||
* PAD/DFIFO/PHY configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** srp_sessend_override : R/W; bitpos: [0]; default: 0;
|
||||
* This bit is used to enable the software override of srp session end signal.1'b0:
|
||||
* the signal is controlled by the chip input.1'b1: the signal is controlled by the
|
||||
* software.
|
||||
*/
|
||||
uint32_t srp_sessend_override:1;
|
||||
/** srp_sessend_value : R/W; bitpos: [1]; default: 0;
|
||||
* Software override value of srp session end signal.
|
||||
*/
|
||||
uint32_t srp_sessend_value:1;
|
||||
/** phy_sel : R/W; bitpos: [2]; default: 0;
|
||||
* Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY
|
||||
*/
|
||||
uint32_t phy_sel:1;
|
||||
/** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
|
||||
* Force the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
uint32_t dfifo_force_pd:1;
|
||||
/** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
|
||||
* Bypass Debounce filters for avalid.
|
||||
*/
|
||||
uint32_t dbnce_fltr_bypass:1;
|
||||
/** exchg_pins_override : R/W; bitpos: [5]; default: 0;
|
||||
* Enable software to control USB D+ D- exchange
|
||||
*/
|
||||
uint32_t exchg_pins_override:1;
|
||||
/** exchg_pins : R/W; bitpos: [6]; default: 0;
|
||||
* USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-.
|
||||
*/
|
||||
uint32_t exchg_pins:1;
|
||||
/** vrefh : R/W; bitpos: [8:7]; default: 0;
|
||||
* Control single-end input high threshold.
|
||||
*/
|
||||
uint32_t vrefh:2;
|
||||
/** vrefl : R/W; bitpos: [10:9]; default: 0;
|
||||
* Control single-end input low threshold.
|
||||
*/
|
||||
uint32_t vrefl:2;
|
||||
/** vref_override : R/W; bitpos: [11]; default: 0;
|
||||
* Enable software to control input threshold.
|
||||
*/
|
||||
uint32_t vref_override:1;
|
||||
/** pad_pull_override : R/W; bitpos: [12]; default: 0;
|
||||
* Enable software to control USB pad in pullup or pulldown mode.
|
||||
*/
|
||||
uint32_t pad_pull_override:1;
|
||||
/** dp_pullup : R/W; bitpos: [13]; default: 0;
|
||||
* Control USB D+ pullup.
|
||||
*/
|
||||
uint32_t dp_pullup:1;
|
||||
/** dp_pulldown : R/W; bitpos: [14]; default: 0;
|
||||
* Control USB D+ pulldown.
|
||||
*/
|
||||
uint32_t dp_pulldown:1;
|
||||
/** dm_pullup : R/W; bitpos: [15]; default: 0;
|
||||
* Control USB D+ pullup.
|
||||
*/
|
||||
uint32_t dm_pullup:1;
|
||||
/** dm_pulldown : R/W; bitpos: [16]; default: 0;
|
||||
* Control USB D+ pulldown.
|
||||
*/
|
||||
uint32_t dm_pulldown:1;
|
||||
/** pullup_value : R/W; bitpos: [17]; default: 0;
|
||||
* Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K.
|
||||
*/
|
||||
uint32_t pullup_value:1;
|
||||
/** pad_enable : R/W; bitpos: [18]; default: 0;
|
||||
* Enable USB pad function.
|
||||
*/
|
||||
uint32_t pad_enable:1;
|
||||
/** ahb_clk_force_on : R/W; bitpos: [19]; default: 1;
|
||||
* Force AHB clock always on.
|
||||
*/
|
||||
uint32_t ahb_clk_force_on:1;
|
||||
/** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
|
||||
* Force PHY clock always on.
|
||||
*/
|
||||
uint32_t phy_clk_force_on:1;
|
||||
/** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
|
||||
* Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
|
||||
*/
|
||||
uint32_t phy_tx_edge_sel:1;
|
||||
/** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
|
||||
* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
uint32_t dfifo_force_pu:1;
|
||||
uint32_t reserved_23:8;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Disable auto clock gating of CSR registers.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_otg_conf_reg_t;
|
||||
|
||||
/** Type of test_conf register
|
||||
* TEST relative configuration registers.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** test_enable : R/W; bitpos: [0]; default: 0;
|
||||
* Enable to test the USB pad.
|
||||
*/
|
||||
uint32_t test_enable:1;
|
||||
/** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
|
||||
* USB pad oen in test.
|
||||
*/
|
||||
uint32_t test_usb_wrap_oe:1;
|
||||
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
|
||||
* USB D+ tx value in test.
|
||||
*/
|
||||
uint32_t test_tx_dp:1;
|
||||
/** test_tx_dm : R/W; bitpos: [3]; default: 0;
|
||||
* USB D- tx value in test.
|
||||
*/
|
||||
uint32_t test_tx_dm:1;
|
||||
/** test_rx_rcv : RO; bitpos: [4]; default: 0;
|
||||
* USB differential rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_rcv:1;
|
||||
/** test_rx_dp : RO; bitpos: [5]; default: 0;
|
||||
* USB D+ rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_dp:1;
|
||||
/** test_rx_dm : RO; bitpos: [6]; default: 0;
|
||||
* USB D- rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_dm:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_test_conf_reg_t;
|
||||
|
||||
|
||||
/** Status registers */
|
||||
/** Type of date register
|
||||
* Version register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 419631616;
|
||||
* data register.
|
||||
*/
|
||||
uint32_t date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile usb_wrap_otg_conf_reg_t otg_conf;
|
||||
volatile usb_wrap_test_conf_reg_t test_conf;
|
||||
uint32_t reserved_008;
|
||||
uint32_t reserved_00c;
|
||||
uint32_t reserved_010;
|
||||
uint32_t reserved_014;
|
||||
uint32_t reserved_018;
|
||||
uint32_t reserved_01c;
|
||||
uint32_t reserved_020;
|
||||
uint32_t reserved_024;
|
||||
uint32_t reserved_028;
|
||||
uint32_t reserved_02c;
|
||||
uint32_t reserved_030;
|
||||
uint32_t reserved_034;
|
||||
uint32_t reserved_038;
|
||||
uint32_t reserved_03c;
|
||||
uint32_t reserved_040;
|
||||
uint32_t reserved_044;
|
||||
uint32_t reserved_048;
|
||||
uint32_t reserved_04c;
|
||||
uint32_t reserved_050;
|
||||
uint32_t reserved_054;
|
||||
uint32_t reserved_058;
|
||||
uint32_t reserved_05c;
|
||||
uint32_t reserved_060;
|
||||
uint32_t reserved_064;
|
||||
uint32_t reserved_068;
|
||||
uint32_t reserved_06c;
|
||||
uint32_t reserved_070;
|
||||
uint32_t reserved_074;
|
||||
uint32_t reserved_078;
|
||||
uint32_t reserved_07c;
|
||||
uint32_t reserved_080;
|
||||
uint32_t reserved_084;
|
||||
uint32_t reserved_088;
|
||||
uint32_t reserved_08c;
|
||||
uint32_t reserved_090;
|
||||
uint32_t reserved_094;
|
||||
uint32_t reserved_098;
|
||||
uint32_t reserved_09c;
|
||||
uint32_t reserved_0a0;
|
||||
uint32_t reserved_0a4;
|
||||
uint32_t reserved_0a8;
|
||||
uint32_t reserved_0ac;
|
||||
uint32_t reserved_0b0;
|
||||
uint32_t reserved_0b4;
|
||||
uint32_t reserved_0b8;
|
||||
uint32_t reserved_0bc;
|
||||
uint32_t reserved_0c0;
|
||||
uint32_t reserved_0c4;
|
||||
uint32_t reserved_0c8;
|
||||
uint32_t reserved_0cc;
|
||||
uint32_t reserved_0d0;
|
||||
uint32_t reserved_0d4;
|
||||
uint32_t reserved_0d8;
|
||||
uint32_t reserved_0dc;
|
||||
uint32_t reserved_0e0;
|
||||
uint32_t reserved_0e4;
|
||||
uint32_t reserved_0e8;
|
||||
uint32_t reserved_0ec;
|
||||
uint32_t reserved_0f0;
|
||||
uint32_t reserved_0f4;
|
||||
uint32_t reserved_0f8;
|
||||
uint32_t reserved_0fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
volatile usb_wrap_date_reg_t date;
|
||||
} usb_wrap_dev_t;
|
||||
|
||||
_Static_assert(sizeof(usb_wrap_dev_t)==0x400, "Invalid USB_WRAP size");
|
||||
|
||||
extern usb_wrap_dev_t USB_WRAP;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -240,8 +240,8 @@ void adc_hal_arbiter_config(adc_arbiter_t *config);
|
||||
* @param channel adc channel number.
|
||||
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
|
||||
* false: Use IO external voltage as calibration voltage.
|
||||
* @param force_cal true: Do not use the results that have already been verified, and perform the verification again. It will take a long time.
|
||||
* false: Use the result of the last calibration.
|
||||
* @param force_cal true: Do not use the results that have already been verified, and perform the verification again. It will take a long time(~40us).
|
||||
* false: Use the result of the last calibration. Return immediately.
|
||||
*
|
||||
* @return
|
||||
* - The calibration result (initial data) to ADC, use `adc_hal_set_calibration_param` to set.
|
||||
|
||||
@ -15,46 +15,28 @@
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "esp32s2/rom/gpio.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
#include "soc/usb_periph.h"
|
||||
|
||||
void gpio_pad_input_enable(uint32_t pin);
|
||||
|
||||
static inline void usb_ll_init(bool external_phy)
|
||||
static inline void usb_ll_int_phy_enable(void)
|
||||
{
|
||||
REG_SET_BIT(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN);
|
||||
REG_CLR_BIT(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST);
|
||||
|
||||
if (external_phy) {
|
||||
REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(18)); //set usb_pad_enable
|
||||
REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(2)); // set reg_phy_sel (external phy)
|
||||
gpio_output_set_high(0x10, 0, 0x1E, 0xE);
|
||||
} else {
|
||||
REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(18)); //set usb_pad_enable
|
||||
REG_CLR_BIT(DR_REG_USB_WRAP_BASE, BIT(2)); // clear reg_phy_sel (internal phy)
|
||||
//drive strength needs to be 3 for full speed
|
||||
REG_SET_FIELD(GPIO_PIN19_REG, GPIO_PIN19_PAD_DRIVER, 3);
|
||||
REG_SET_FIELD(GPIO_PIN20_REG, GPIO_PIN20_PAD_DRIVER, 3);
|
||||
}
|
||||
|
||||
int i = 0;
|
||||
while (usb_periph_iopins[i].pin != -1) {
|
||||
if ((external_phy) || (usb_periph_iopins[i].ext_phy_only == 0)) {
|
||||
gpio_pad_select_gpio(usb_periph_iopins[i].pin);
|
||||
if (usb_periph_iopins[i].is_output) {
|
||||
gpio_matrix_out(usb_periph_iopins[i].pin, usb_periph_iopins[i].func, false, false);
|
||||
} else {
|
||||
gpio_matrix_in(usb_periph_iopins[i].pin, usb_periph_iopins[i].func, false);
|
||||
gpio_pad_input_enable(usb_periph_iopins[i].pin);
|
||||
}
|
||||
gpio_pad_unhold(usb_periph_iopins[i].pin);
|
||||
}
|
||||
i++;
|
||||
}
|
||||
REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(12)); //pull override
|
||||
REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(13)); //dp pullup
|
||||
REG_CLR_BIT(DR_REG_USB_WRAP_BASE, BIT(14)); //dp pulldwn
|
||||
REG_CLR_BIT(DR_REG_USB_WRAP_BASE, BIT(15)); //dm pullup
|
||||
REG_CLR_BIT(DR_REG_USB_WRAP_BASE, BIT(16)); //dm pulldown
|
||||
USB_WRAP.otg_conf.pad_enable = 1;
|
||||
USB_WRAP.otg_conf.phy_sel = 0;
|
||||
}
|
||||
|
||||
static inline void usb_ll_ext_phy_enable(void)
|
||||
{
|
||||
USB_WRAP.otg_conf.pad_enable = 1;
|
||||
USB_WRAP.otg_conf.phy_sel = 1;
|
||||
}
|
||||
|
||||
static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
|
||||
{
|
||||
usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
|
||||
conf.pad_pull_override = 1;
|
||||
conf.dp_pullup = dp_pu;
|
||||
conf.dp_pulldown = dp_pd;
|
||||
conf.dm_pullup = dm_pu;
|
||||
conf.dm_pulldown = dp_pd;
|
||||
USB_WRAP.otg_conf = conf;
|
||||
}
|
||||
|
||||
@ -27,4 +27,4 @@ PROVIDE ( I2C1 = 0x3f427000 );
|
||||
PROVIDE ( CAN = 0x3f42B000 );
|
||||
PROVIDE ( APB_SARADC = 0x3f440000 );
|
||||
PROVIDE ( USB0 = 0x60080000 );
|
||||
PROVIDE ( ToBeCleanedUpBelow = 0x00000000 );
|
||||
PROVIDE ( USB_WRAP = 0x3f439000 );
|
||||
|
||||
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@ -53,7 +53,7 @@ CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y
|
||||
# CONFIG_BOOTLOADER_FACTORY_RESET is not set
|
||||
# CONFIG_BOOTLOADER_APP_TEST is not set
|
||||
CONFIG_BOOTLOADER_WDT_ENABLE=y
|
||||
# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set
|
||||
CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE=y
|
||||
CONFIG_BOOTLOADER_WDT_TIME_MS=9000
|
||||
# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set
|
||||
CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y
|
||||
@ -136,6 +136,7 @@ CONFIG_ARDUINO_EVENT_RUNNING_CORE=1
|
||||
CONFIG_ARDUINO_UDP_RUN_CORE1=y
|
||||
# CONFIG_ARDUINO_UDP_RUN_NO_AFFINITY is not set
|
||||
CONFIG_ARDUINO_UDP_RUNNING_CORE=1
|
||||
# CONFIG_ARDUINO_ISR_IRAM is not set
|
||||
# CONFIG_DISABLE_HAL_LOCKS is not set
|
||||
|
||||
#
|
||||
@ -307,16 +308,18 @@ CONFIG_DEFAULT_PSRAM_CS_IO=26
|
||||
# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
|
||||
# CONFIG_SPIRAM_RODATA is not set
|
||||
# CONFIG_SPIRAM_USE_AHB_DBUS3 is not set
|
||||
# CONFIG_SPIRAM_SPEED_80M is not set
|
||||
CONFIG_SPIRAM_SPEED_40M=y
|
||||
CONFIG_SPIRAM_SPEED_80M=y
|
||||
# CONFIG_SPIRAM_SPEED_40M is not set
|
||||
# CONFIG_SPIRAM_SPEED_26M is not set
|
||||
# CONFIG_SPIRAM_SPEED_20M is not set
|
||||
CONFIG_SPIRAM=y
|
||||
# CONFIG_SPIRAM_BOOT_INIT is not set
|
||||
# CONFIG_SPIRAM_USE_MEMMAP is not set
|
||||
CONFIG_SPIRAM_USE_CAPS_ALLOC=y
|
||||
# CONFIG_SPIRAM_USE_MALLOC is not set
|
||||
# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
|
||||
# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
|
||||
CONFIG_SPIRAM_USE_MALLOC=y
|
||||
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=4096
|
||||
CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y
|
||||
CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
|
||||
# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
|
||||
# end of SPI RAM config
|
||||
|
||||
@ -373,11 +376,11 @@ CONFIG_ESP_CONSOLE_UART_TX_GPIO=43
|
||||
CONFIG_ESP_CONSOLE_UART_RX_GPIO=44
|
||||
CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
|
||||
CONFIG_ESP_INT_WDT=y
|
||||
CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
|
||||
CONFIG_ESP_INT_WDT_TIMEOUT_MS=1000
|
||||
CONFIG_ESP_TASK_WDT=y
|
||||
CONFIG_ESP_TASK_WDT_PANIC=y
|
||||
CONFIG_ESP_TASK_WDT_TIMEOUT_S=5
|
||||
CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
|
||||
# CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 is not set
|
||||
CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
|
||||
CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
|
||||
# end of Common ESP-related
|
||||
@ -465,10 +468,9 @@ CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
|
||||
#
|
||||
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=16
|
||||
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
|
||||
# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
|
||||
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
|
||||
CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
|
||||
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32
|
||||
CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
|
||||
CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
|
||||
CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
|
||||
# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
|
||||
CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
|
||||
CONFIG_ESP32_WIFI_TX_BA_WIN=6
|
||||
@ -696,6 +698,7 @@ CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
|
||||
CONFIG_LWIP_TCP_OVERSIZE_MSS=y
|
||||
# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
|
||||
# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
|
||||
# CONFIG_LWIP_WND_SCALE is not set
|
||||
# end of TCP
|
||||
|
||||
#
|
||||
@ -749,6 +752,7 @@ CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
|
||||
# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set
|
||||
CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384
|
||||
# CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN is not set
|
||||
# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set
|
||||
# CONFIG_MBEDTLS_DEBUG is not set
|
||||
|
||||
#
|
||||
@ -770,6 +774,8 @@ CONFIG_MBEDTLS_HARDWARE_GCM=y
|
||||
# CONFIG_MBEDTLS_HARDWARE_SHA is not set
|
||||
CONFIG_MBEDTLS_HAVE_TIME=y
|
||||
# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
|
||||
CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
|
||||
CONFIG_MBEDTLS_SHA512_C=y
|
||||
CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
|
||||
# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set
|
||||
# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set
|
||||
@ -850,6 +856,8 @@ CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y
|
||||
CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
|
||||
# CONFIG_MBEDTLS_POLY1305_C is not set
|
||||
# CONFIG_MBEDTLS_CHACHA20_C is not set
|
||||
# CONFIG_MBEDTLS_HKDF_C is not set
|
||||
# CONFIG_MBEDTLS_THREADING_C is not set
|
||||
# CONFIG_MBEDTLS_SECURITY_RISKS is not set
|
||||
# end of mbedTLS
|
||||
|
||||
@ -858,6 +866,7 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
|
||||
#
|
||||
CONFIG_MDNS_MAX_SERVICES=10
|
||||
CONFIG_MDNS_TASK_PRIORITY=1
|
||||
CONFIG_MDNS_TASK_STACK_SIZE=4096
|
||||
# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
|
||||
CONFIG_MDNS_TASK_AFFINITY_CPU0=y
|
||||
CONFIG_MDNS_TASK_AFFINITY=0x0
|
||||
@ -1102,11 +1111,11 @@ CONFIG_CONSOLE_UART_TX_GPIO=43
|
||||
CONFIG_CONSOLE_UART_RX_GPIO=44
|
||||
CONFIG_CONSOLE_UART_BAUDRATE=115200
|
||||
CONFIG_INT_WDT=y
|
||||
CONFIG_INT_WDT_TIMEOUT_MS=300
|
||||
CONFIG_INT_WDT_TIMEOUT_MS=1000
|
||||
CONFIG_TASK_WDT=y
|
||||
CONFIG_TASK_WDT_PANIC=y
|
||||
CONFIG_TASK_WDT_TIMEOUT_S=5
|
||||
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
|
||||
# CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 is not set
|
||||
# CONFIG_EVENT_LOOP_PROFILING is not set
|
||||
CONFIG_POST_EVENTS_FROM_ISR=y
|
||||
CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
|
||||
|
||||
Reference in New Issue
Block a user