forked from espressif/esp-idf
fix(psram): fixecd wrong ap density check
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@@ -267,17 +267,33 @@ static void s_config_psram_clock(bool init_state)
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#endif //#if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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/**
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* For certain wafer version and 8MB case, we consider it as 4MB mode as it uses 2T mode
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* For mrj069000aa, this wafer version and 8MB case, we consider it as 4MB mode as it uses 2T mode
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*/
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bool s_check_aps3204_2tmode(void)
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static bool s_check_mrj069000aa_2tmode(uint32_t eid_47_16)
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{
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bool is_2t = false;
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ESP_EARLY_LOGD(TAG, "(eid_47_16 >> 5) & 0xfffff: 0x%"PRIx32, (eid_47_16 >> 5) & 0xfffff);
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if (((eid_47_16 >> 5) & 0xfffff) == 0x8a445) {
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is_2t = true;
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}
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return is_2t;
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}
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static bool s_check_2tmode(void)
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{
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uint64_t full_eid = 0;
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psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_QUAD_EID_BITS_NUM);
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bool is_2t = false;
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uint32_t eid_47_16 = __builtin_bswap32((full_eid >> 16) & UINT32_MAX);
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ESP_EARLY_LOGD(TAG, "full_eid: 0x%" PRIx64", eid_47_16: 0x%"PRIx32", (eid_47_16 >> 5) & 0xfffff: 0x%"PRIx32, full_eid, eid_47_16, (eid_47_16 >> 5) & 0xfffff);
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if (((eid_47_16 >> 5) & 0xfffff) == 0x8a445) {
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ESP_EARLY_LOGD(TAG, "full_eid: 0x%" PRIx64", eid_47_16: 0x%"PRIx32", (eid_47_16 >> 25) & 0x1: 0x%"PRIx32, full_eid, eid_47_16, (eid_47_16 >> 25) & 0x1);
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//EID[41]: 0 for 2t mode; 1 for non-2t mode
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if (((eid_47_16 >> 25) & 0x1) == 0) {
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is_2t = true;
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}
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if (s_check_mrj069000aa_2tmode(eid_47_16)) {
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is_2t = true;
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}
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@@ -328,10 +344,11 @@ esp_err_t esp_psram_impl_enable(void)
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* that are 16MB or 32MB to be interpreted as QEMU PSRAM devices */
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eid == PSRAM_QUAD_QEMU_16MB_ID ? PSRAM_SIZE_16MB :
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eid == PSRAM_QUAD_QEMU_32MB_ID ? PSRAM_SIZE_32MB : 0;
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}
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if ((s_psram_size == PSRAM_SIZE_8MB) && s_check_aps3204_2tmode()) {
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s_psram_size = PSRAM_SIZE_4MB;
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if ((s_psram_size == PSRAM_SIZE_8MB) && s_check_2tmode()) {
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//2t mode is only valid for EID[47:45] == 0x10 chips
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s_psram_size = s_psram_size / 2;
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}
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}
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//SPI1: send psram reset command
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