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feat(gdma): can read interrupt raw status

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This commit is contained in:
morris
2023-11-15 16:33:48 +08:00
parent 2f72b3578a
commit 05e6ccbba7
15 changed files with 106 additions and 49 deletions
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5
components/esp_hw_support/dma/gdma.c
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@@ -803,7 +803,8 @@ void gdma_default_rx_isr(void *args)
bool normal_eof = false;
// clear pending interrupt event first
uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX);
// reading the raw interrupt status because we also want to know the EOF status, even if the EOF interrupt is not enabled
uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, true);
gdma_hal_clear_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, intr_status);
// prepare data for different events
@@ -852,7 +853,7 @@ void gdma_default_tx_isr(void *args)
int pair_id = pair->pair_id;
bool need_yield = false;
// clear pending interrupt event
uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX);
uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, false);
gdma_hal_clear_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, intr_status);
if ((intr_status & GDMA_LL_EVENT_TX_EOF) && tx_chan->cbs.on_trans_eof) {

16
components/hal/esp32c2/include/hal/gdma_ll.h
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@@ -89,9 +89,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
if (raw) {
return dev->intr[channel].raw.val & GDMA_LL_RX_EVENT_MASK;
} else {
return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
}
}
/**
@@ -303,9 +307,13 @@ static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t c
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
if (raw) {
return dev->intr[channel].raw.val & GDMA_LL_TX_EVENT_MASK;
} else {
return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
}
}
/**

16
components/hal/esp32c3/include/hal/gdma_ll.h
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@@ -89,9 +89,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
if (raw) {
return dev->intr[channel].raw.val & GDMA_LL_RX_EVENT_MASK;
} else {
return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
}
}
/**
@@ -303,9 +307,13 @@ static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t c
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
if (raw) {
return dev->intr[channel].raw.val & GDMA_LL_TX_EVENT_MASK;
} else {
return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
}
}
/**

16
components/hal/esp32c6/include/hal/gdma_ll.h
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@@ -125,9 +125,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->in_intr[channel].st.val;
if (raw) {
return dev->in_intr[channel].raw.val;
} else {
return dev->in_intr[channel].st.val;
}
}
/**
@@ -349,9 +353,13 @@ static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel,
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->out_intr[channel].st.val;
if (raw) {
return dev->out_intr[channel].raw.val;
} else {
return dev->out_intr[channel].st.val;
}
}
/**

16
components/hal/esp32h2/include/hal/gdma_ll.h
View File

@@ -125,9 +125,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->in_intr[channel].st.val;
if (raw) {
return dev->in_intr[channel].raw.val;
} else {
return dev->in_intr[channel].st.val;
}
}
/**
@@ -349,9 +353,13 @@ static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel,
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->out_intr[channel].st.val;
if (raw) {
return dev->out_intr[channel].raw.val;
} else {
return dev->out_intr[channel].st.val;
}
}
/**

20
components/hal/esp32p4/include/hal/ahb_dma_ll.h
View File

@@ -62,9 +62,13 @@ static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev)
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel)
static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->in_intr[channel].st.val;
if (raw) {
return dev->in_intr[channel].raw.val;
} else {
return dev->in_intr[channel].st.val;
}
}
/**
@@ -286,9 +290,13 @@ static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel)
static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->out_intr[channel].st.val;
if (raw) {
return dev->out_intr[channel].raw.val;
} else {
return dev->out_intr[channel].st.val;
}
}
/**
@@ -552,7 +560,7 @@ static inline void ahb_dma_ll_tx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t c
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, TX channel
*/
static inline void ahb_dma_ll_tx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
{
dev->out_crc[channel].crc_en_addr.tx_crc_en_addr_chn = crc_bit;
dev->out_crc[channel].crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask;
@@ -613,7 +621,7 @@ static inline void ahb_dma_ll_rx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t c
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, RX channel
*/
static inline void ahb_dma_ll_rx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
{
dev->in_crc[channel].crc_en_addr.rx_crc_en_addr_chn = crc_bit;
dev->in_crc[channel].crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;

20
components/hal/esp32p4/include/hal/axi_dma_ll.h
View File

@@ -64,9 +64,13 @@ static inline void axi_dma_ll_reset_fsm(axi_dma_dev_t *dev)
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t axi_dma_ll_rx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel)
static inline uint32_t axi_dma_ll_rx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->in[channel].intr.st.val;
if (raw) {
return dev->in[channel].intr.raw.val;
} else {
return dev->in[channel].intr.st.val;
}
}
/**
@@ -260,9 +264,13 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t axi_dma_ll_tx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel)
static inline uint32_t axi_dma_ll_tx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->out[channel].intr.st.val;
if (raw) {
return dev->out[channel].intr.raw.val;
} else {
return dev->out[channel].intr.st.val;
}
}
/**
@@ -498,7 +506,7 @@ static inline void axi_dma_ll_tx_crc_latch_config(axi_dma_dev_t *dev, uint32_t c
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, TX channel
*/
static inline void axi_dma_ll_tx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
{
dev->out[channel].crc.tx_crc_en_addr.tx_crc_en_addr_chn = crc_bit;
dev->out[channel].crc.tx_crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask;
@@ -559,7 +567,7 @@ static inline void axi_dma_ll_rx_crc_latch_config(axi_dma_dev_t *dev, uint32_t c
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, RX channel
*/
static inline void axi_dma_ll_rx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
{
dev->in[channel].crc.rx_crc_en_addr.rx_crc_en_addr_chn = crc_bit;
dev->in[channel].crc.rx_crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;

16
components/hal/esp32s3/include/hal/gdma_ll.h
View File

@@ -102,9 +102,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->channel[channel].in.int_st.val;
if (raw) {
return dev->channel[channel].in.int_raw.val;
} else {
return dev->channel[channel].in.int_st.val;
}
}
/**
@@ -366,9 +370,13 @@ static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t c
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
return dev->channel[channel].out.int_st.val;
if (raw) {
return dev->channel[channel].out.int_raw.val;
} else {
return dev->channel[channel].out.int_st.val;
}
}
/**

6
components/hal/gdma_hal_ahb_v1.c
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@@ -131,12 +131,12 @@ void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_
}
}
uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
return gdma_ll_rx_get_interrupt_status(hal->dev, chan_id);
return gdma_ll_rx_get_interrupt_status(hal->dev, chan_id, raw);
} else {
return gdma_ll_tx_get_interrupt_status(hal->dev, chan_id);
return gdma_ll_tx_get_interrupt_status(hal->dev, chan_id, raw);
}
}

6
components/hal/gdma_hal_ahb_v2.c
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@@ -120,12 +120,12 @@ void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_
}
}
uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
return ahb_dma_ll_rx_get_interrupt_status(hal->ahb_dma_dev, chan_id);
return ahb_dma_ll_rx_get_interrupt_status(hal->ahb_dma_dev, chan_id, raw);
} else {
return ahb_dma_ll_tx_get_interrupt_status(hal->ahb_dma_dev, chan_id);
return ahb_dma_ll_tx_get_interrupt_status(hal->ahb_dma_dev, chan_id, raw);
}
}

6
components/hal/gdma_hal_axi.c
View File

@@ -120,12 +120,12 @@ void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_
}
}
uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw)
{
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
return axi_dma_ll_rx_get_interrupt_status(hal->axi_dma_dev, chan_id);
return axi_dma_ll_rx_get_interrupt_status(hal->axi_dma_dev, chan_id, raw);
} else {
return axi_dma_ll_tx_get_interrupt_status(hal->axi_dma_dev, chan_id);
return axi_dma_ll_tx_get_interrupt_status(hal->axi_dma_dev, chan_id, raw);
}
}

4
components/hal/gdma_hal_top.c
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@@ -75,9 +75,9 @@ void gdma_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_dire
hal->clear_intr(hal, chan_id, dir, intr_event_mask);
}
uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw)
{
return hal->read_intr_status(hal, chan_id, dir);
return hal->read_intr_status(hal, chan_id, dir, raw);
}
uint32_t gdma_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)

4
components/hal/include/hal/gdma_hal.h
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@@ -85,7 +85,7 @@ struct gdma_hal_context_t {
uint32_t (*get_intr_status_reg)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); // Get the interrupt status register address
void (*enable_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis); /// Enable the channel interrupt
void (*clear_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask); /// Clear the channel interrupt
uint32_t (*read_intr_status)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Read the channel interrupt status
uint32_t (*read_intr_status)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw); /// Read the channel interrupt status
uint32_t (*get_eof_desc_addr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success); /// Get the address of the descriptor with success/error EOF flag set
#if SOC_GDMA_SUPPORT_CRC
void (*clear_crc)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Clear the CRC interim results
@@ -122,7 +122,7 @@ void gdma_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_dire
uint32_t gdma_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw);
uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success);

2
components/hal/include/hal/gdma_hal_ahb.h
View File

@@ -36,7 +36,7 @@ void gdma_ahb_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel
void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask);
uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw);
uint32_t gdma_ahb_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);

2
components/hal/include/hal/gdma_hal_axi.h
View File

@@ -36,7 +36,7 @@ void gdma_axi_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel
void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask);
uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw);
uint32_t gdma_axi_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);