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reset_reasons: EFUSE_RST is treated as POWERON_RST

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ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.
This commit is contained in:
KonstantinKondrashov
2021-08-11 12:20:17 +05:00
parent 0fc7bd6a37
commit 0a71dce1ef
5 changed files with 15 additions and 3 deletions
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6
components/bootloader_support/src/esp_image_format.c
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@@ -259,7 +259,11 @@ esp_err_t bootloader_load_image(const esp_partition_pos_t *part, esp_image_metad
#if CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS #if CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS
mode = ESP_IMAGE_LOAD_NO_VALIDATE; mode = ESP_IMAGE_LOAD_NO_VALIDATE;
#elif CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON #elif CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON
if (rtc_get_reset_reason(0) == POWERON_RESET) { if (rtc_get_reset_reason(0) == POWERON_RESET
#if SOC_EFUSE_HAS_EFUSE_RST_BUG
|| rtc_get_reset_reason(0) == EFUSE_RESET
#endif
) {
mode = ESP_IMAGE_LOAD_NO_VALIDATE; mode = ESP_IMAGE_LOAD_NO_VALIDATE;
} }
#endif // CONFIG_BOOTLOADER_SKIP_... #endif // CONFIG_BOOTLOADER_SKIP_...

1
components/esp_rom/include/esp32s2/rom/rtc.h
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@@ -94,6 +94,7 @@ typedef enum {
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/ TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/ SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/ GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
} RESET_REASON; } RESET_REASON;
typedef enum { typedef enum {

6
components/esp_system/port/soc/esp32c3/clk.c
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@@ -77,7 +77,11 @@ static const char *TAG = "clk";
rtc_config_t cfg = RTC_CONFIG_DEFAULT(); rtc_config_t cfg = RTC_CONFIG_DEFAULT();
RESET_REASON rst_reas; RESET_REASON rst_reas;
rst_reas = rtc_get_reset_reason(0); rst_reas = rtc_get_reset_reason(0);
if (rst_reas == POWERON_RESET) { if (rst_reas == POWERON_RESET
#if SOC_EFUSE_HAS_EFUSE_RST_BUG
|| rst_reas == EFUSE_RESET
#endif
) {
cfg.cali_ocode = 1; cfg.cali_ocode = 1;
} }
rtc_init(cfg); rtc_init(cfg);

3
components/esp_system/port/soc/esp32c3/reset_reason.c
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@@ -25,6 +25,9 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
{ {
switch (rtc_reset_reason) { switch (rtc_reset_reason) {
case POWERON_RESET: case POWERON_RESET:
#if SOC_EFUSE_HAS_EFUSE_RST_BUG
case EFUSE_RESET:
#endif
return ESP_RST_POWERON; return ESP_RST_POWERON;
case RTC_SW_CPU_RESET: case RTC_SW_CPU_RESET:

2
components/soc/esp32c3/include/soc/soc_caps.h
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@@ -18,7 +18,7 @@
/*-------------------------- COMMON CAPS ---------------------------------------*/ /*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_HAS_EFUSE_RST_BUG 1
/*-------------------------- AES CAPS -----------------------------------------*/ /*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1) #define SOC_AES_SUPPORT_DMA (1)