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feat(rom): update rom for c5 eco2

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Breaking: Starting from this commit, ESP-IDF can only support ESP32-C5 v1.0 (ECO2)
This commit is contained in:
laokaiyao
2025-04-08 12:48:49 +08:00
parent 61064b442a
commit 0abc755342
24 changed files with 241 additions and 392 deletions
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2
Kconfig
View File

@ -118,6 +118,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
default "y" if IDF_TARGET="esp32c5"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
# TODO: [ESPTOOL-1044] remove when stub supported
select ESPTOOLPY_NO_STUB
config IDF_TARGET_ESP32P4
bool

26
components/bootloader/subproject/main/ld/esp32c5/bootloader.ld
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@ -7,20 +7,20 @@
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-C5 ROM static data usage is as follows:
* - 0x4084e9a0 - 0x4085c9a0: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4085c9a0 - 0x4085e9a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4085e9a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
* - 0x4084e5a0 - 0x4085c5a0: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4085c5a0 - 0x4085e5a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4085e5a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x4085c9a0).
* buffers area (0x4085c5a0).
*/
/* We consider 0x4085c9a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
/* We consider 0x4085c5a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x4085c9a0;
bootloader_usable_dram_end = 0x4085c5a0;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0x5000;
bootloader_iram_loader_seg_len = 0x7000;
@ -45,7 +45,7 @@ MEMORY
* 2. Update the value in this assert.
* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x4084E9A0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
ASSERT(bootloader_iram_loader_seg_start == 0x4084e5a0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(call_start_cpu0);
@ -277,32 +277,32 @@ SECTIONS
/**
* Appendix: Memory Usage of ROM bootloader
*
* 0x4084e9a0 ------------------> _dram0_0_start
* 0x4084e5a0 ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x4085c9a0 ------------------> __stack_sentry
* 0x4085c5a0 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x4085e9a0 ------------------> __stack (pro cpu)
* 0x4085e5a0 ------------------> __stack (pro cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x4085f500 ------------------> _dram0_rtos_reserved_start
* 0x4085f4f8 ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x4085fc5c ------------------> _dram0_rtos_reserved_end
* 0x4085fbb4 ------------------> _dram0_rtos_reserved_end
* | |
* 0x4085fc70 ------------------> _data_start_interface
* 0x4085fc60 ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |

15
components/esp_hw_support/port/esp32c5/Kconfig.hw_support
View File

@ -1,6 +1,6 @@
choice ESP32C5_REV_MIN
prompt "Minimum Supported ESP32-C5 Revision"
default ESP32C5_REV_MIN_0
default ESP32C5_REV_MIN_100
help
Required minimum chip revision. ESP-IDF will check for it and
reject to boot if the chip revision fails the check.
@ -9,16 +9,13 @@ choice ESP32C5_REV_MIN
The complied binary will only support chips above this revision,
this will also help to reduce binary size.
config ESP32C5_REV_MIN_0
bool "Rev v0.0 (ECO0)"
config ESP32C5_REV_MIN_1
bool "Rev v0.1 (ECO1)"
config ESP32C5_REV_MIN_100
bool "Rev v1.0 (ECO2)"
endchoice
config ESP32C5_REV_MIN_FULL
int
default 0 if ESP32C5_REV_MIN_0
default 1 if ESP32C5_REV_MIN_1
default 100 if ESP32C5_REV_MIN_100
config ESP_REV_MIN_FULL
int
@ -28,7 +25,7 @@ config ESP_REV_MIN_FULL
# MAX Revision
#
comment "Maximum Supported ESP32-C5 Revision (Rev v0.99)"
comment "Maximum Supported ESP32-C5 Revision (Rev v1.99)"
# Maximum revision that IDF supports.
# It can not be changed by user.
# Only Espressif can change it when a new version will be supported in IDF.
@ -36,7 +33,7 @@ config ESP_REV_MIN_FULL
config ESP32C5_REV_MAX_FULL
int
default 99
default 199
# keep in sync the "Maximum Supported Revision" description with this value
config ESP_REV_MAX_FULL

2
components/esp_rom/esp32c5/Kconfig.soc_caps.in
View File

@ -75,7 +75,7 @@ config ESP_ROM_HAS_NEWLIB
bool
default y
config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
bool
default y

2
components/esp_rom/esp32c5/esp_rom_caps.h
View File

@ -24,7 +24,7 @@
#define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver
#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs TODO: IDF-10110 need refactor
#define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included
#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions
#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock
#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init

2
components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

6
components/esp_rom/esp32c5/ld/esp32c5.rom.coexist.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.coexist.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/

6
components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.heap.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/

63
components/esp_rom/esp32c5/ld/esp32c5.rom.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -429,3 +429,60 @@ usb_serial_device_rx_one_char = 0x40000ab8;
usb_serial_device_rx_one_char_block = 0x40000abc;
usb_serial_device_tx_flush = 0x40000ac0;
usb_serial_device_tx_one_char = 0x40000ac4;
/***************************************
Group recovery_bootloader
***************************************/
/* Functions */
ets_get_bootloader_offset = 0x40001544;
ets_set_bootloader_offset = 0x40001548;
/***************************************
Group lldesc
***************************************/
/* Functions */
lldesc_build_chain = 0x4000154c;
/***************************************
Group sip
***************************************/
/* Functions */
sip_after_tx_complete = 0x40001550;
sip_alloc_to_host_evt = 0x40001554;
sip_download_begin = 0x40001558;
sip_get_ptr = 0x4000155c;
sip_get_state = 0x40001560;
sip_init_attach = 0x40001564;
sip_install_rx_ctrl_cb = 0x40001568;
sip_install_rx_data_cb = 0x4000156c;
sip_is_active = 0x40001570;
sip_post_init = 0x40001574;
sip_reclaim_from_host_cmd = 0x40001578;
sip_reclaim_tx_data_pkt = 0x4000157c;
sip_send = 0x40001580;
sip_to_host_chain_append = 0x40001584;
sip_to_host_evt_send_done = 0x40001588;
/***************************************
Group slc
***************************************/
/* Functions */
slc_add_credits = 0x4000158c;
slc_enable = 0x40001590;
slc_from_host_chain_fetch = 0x40001594;
slc_from_host_chain_recycle = 0x40001598;
slc_has_pkt_to_host = 0x4000159c;
slc_init_attach = 0x400015a0;
slc_init_credit = 0x400015a4;
slc_reattach = 0x400015a8;
slc_send_to_host_chain = 0x400015ac;
slc_set_host_io_max_window = 0x400015b0;
slc_to_host_chain_recycle = 0x400015b4;

15
components/esp_rom/esp32c5/ld/esp32c5.rom.libc.ld
View File

@ -3,6 +3,21 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.libc.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum e68b5b3e3d244713e5743335f3857c57
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group libc
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x400004b4;
memset = 0x400004b8;
strlen = 0x400004d8;

6
components/esp_rom/esp32c5/ld/esp32c5.rom.libgcc.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.libgcc.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/

34
components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.net80211.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -35,18 +35,18 @@ ic_ebuf_alloc = 0x40000b4c;
ic_reset_extra_softap_rx_ba = 0x40000b50;
ieee80211_align_eb = 0x40000b54;
ieee80211_ampdu_reorder = 0x40000b58;
/*ieee80211_ampdu_start_age_timer = 0x40000b5c;*/
/*ieee80211_encap_esfbuf = 0x40000b60;*/
ieee80211_ampdu_start_age_timer = 0x40000b5c;
ieee80211_encap_esfbuf = 0x40000b60;
ieee80211_is_tx_allowed = 0x40000b64;
/*ieee80211_output_pending_eb = 0x40000b68;*/
/*ieee80211_output_process = 0x40000b6c;*/
/*ieee80211_set_tx_desc = 0x40000b70;*/
ieee80211_output_pending_eb = 0x40000b68;
ieee80211_output_process = 0x40000b6c;
ieee80211_set_tx_desc = 0x40000b70;
ieee80211_classify = 0x40000b74;
ieee80211_copy_eb_header = 0x40000b78;
ieee80211_recycle_cache_eb = 0x40000b7c;
ieee80211_search_node = 0x40000b80;
/*ieee80211_crypto_encap = 0x40000b84;*/
/*ieee80211_crypto_decap = 0x40000b88;*/
ieee80211_crypto_encap = 0x40000b84;
ieee80211_crypto_decap = 0x40000b88;
ieee80211_decap = 0x40000b8c;
ieee80211_set_tx_pti = 0x40000b90;
ieee80211_gettid = 0x40000b94;
@ -60,13 +60,13 @@ ieee80211_find_ext_elem = 0x40000bb0;
ieee80211_find_ie = 0x40000bb4;
ieee80211_find_ext_ie = 0x40000bb8;
ieee80211_merge_mbssid_profile = 0x40000bbc;
/*ieee80211_encap_esfbuf_htc = 0x40000bc0;*/
/*wifi_get_macaddr = 0x40000bc4;*/
/*wifi_rf_phy_disable = 0x40000bc8;*/
/*wifi_rf_phy_enable = 0x40000bcc;*/
/*wifi_is_started = 0x40000bd0;*/
/*sta_input = 0x40000bd4;*/
/*sta_rx_eapol = 0x40000bd8;*/
ieee80211_encap_esfbuf_htc = 0x40000bc0;
wifi_get_macaddr = 0x40000bc4;
wifi_rf_phy_disable = 0x40000bc8;
wifi_rf_phy_enable = 0x40000bcc;
wifi_is_started = 0x40000bd0;
sta_input = 0x40000bd4;
sta_rx_eapol = 0x40000bd8;
sta_reset_beacon_timeout = 0x40000bdc;
sta_get_beacon_timeout = 0x40000be0;
ampdu_process_multicast_address_qos_frame = 0x40000be4;

14
components/esp_rom/esp32c5/ld/esp32c5.rom.newlib-normal.ld → components/esp_rom/esp32c5/ld/esp32c5.rom.newlib-nano.ld
View File

@ -1,20 +1,20 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.newlib-normal.ld for esp32c5
/* ROM function interface esp32c5.rom.newlib-nano.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib_normal_format
Group newlib_nano_format
***************************************/
/* Functions */
@ -37,5 +37,5 @@ vprintf = 0x40000620;
viprintf = 0x40000624;
vsnprintf = 0x40000628;
vsniprintf = 0x4000062c;
sscanf = 0x40000630;
siscanf = 0x40000634;
_printf_common = 0x40000630;
_printf_i = 0x40000634;

10
components/esp_rom/esp32c5/ld/esp32c5.rom.newlib.ld
View File

@ -1,18 +1,16 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.newlib.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. !!! BUT EDITED !!!
* The file was originally generated for use with newlib, but it was split into
* multiple files to make it compatible with picolibc.
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************

278
components/esp_rom/esp32c5/ld/esp32c5.rom.phy.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.phy.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -21,277 +21,7 @@
phy_param_addr = 0x400010dc;
chip752_phyrom_version = 0x400010e0;
chip752_phyrom_version_num = 0x400010e4;
phy_rate_to_index = 0x400010e8;
phy_get_target_pwr = 0x400010ec;
phy_get_max_pwr = 0x400010f0;
phy_get_pwr_index = 0x400010f4;
phy_get_rc_dout = 0x400010f8;
phy_rc_cal = 0x400010fc;
phy_abs_temp = 0x40001100;
phy_set_chan_interp = 0x40001104;
phy_loop_clk_en = 0x40001108;
phy_get_data_sat = 0x4000110c;
phy_byte_to_word = 0x40001110;
phy_get_rx_freq = 0x40001114;
phy_bb_bss_cbw40 = 0x40001118;
phy_set_chan_reg = 0x4000111c;
phy_i2c_master_reset = 0x40001120;
phy_chan14_mic_enable = 0x40001124;
phy_chan14_mic_cfg = 0x40001128;
phy_set_most_tpw = 0x4000112c;
phy_get_most_tpw = 0x40001130;
phy_tx_state_out = 0x40001134;
phy_ant_dft_cfg = 0x40001138;
phy_ant_wifitx_cfg = 0x4000113c;
phy_ant_wifirx_cfg = 0x40001140;
phy_ant_bttx_cfg = 0x40001144;
phy_ant_btrx_cfg = 0x40001148;
phy_chan_dump_cfg = 0x4000114c;
phy_chan_dump_cfg_752 = 0x40001150;
phy_enable_low_rate = 0x40001154;
phy_disable_low_rate = 0x40001158;
phy_is_low_rate_enabled = 0x4000115c;
phy_dig_reg_backup = 0x40001160;
phy_chan_filt_set = 0x40001164;
phy_rx11blr_cfg = 0x40001168;
phy_set_cca = 0x4000116c;
phy_set_rx_sense = 0x40001170;
phy_freq_module_resetn = 0x40001174;
phy_freq_chan_en_sw = 0x40001178;
phy_write_chan_freq = 0x4000117c;
phy_get_freq_mem_param = 0x40001180;
phy_get_freq_mem_addr = 0x40001184;
phy_wr_freq_mem = 0x40001188;
phy_read_rf_freq_mem = 0x4000118c;
phy_freq_i2c_mem_write = 0x40001190;
phy_freq_num_get_data = 0x40001194;
phy_freq_i2c_num_addr = 0x40001198;
phy_freq_i2c_write_set = 0x4000119c;
phy_pll_cap_mem_update = 0x400011a0;
phy_en_hw_set_freq = 0x400011a4;
phy_dis_hw_set_freq = 0x400011a8;
phy_wait_freq_set_busy = 0x400011ac;
phy_i2c_enter_critical_ = 0x400011b0;
phy_i2c_exit_critical_ = 0x400011b4;
phy_i2c_clk_sel = 0x400011b8;
phy_get_i2c_read_mask_ = 0x400011bc;
phy_get_i2c_mst0_mask = 0x400011c0;
phy_get_i2c_hostid_ = 0x400011c4;
phy_chip_i2c_readReg_org = 0x400011c8;
phy_chip_i2c_readReg = 0x400011cc;
phy_i2c_paral_set_mst0 = 0x400011d0;
phy_i2c_paral_set_read = 0x400011d4;
phy_i2c_paral_read = 0x400011d8;
phy_i2c_paral_write = 0x400011dc;
phy_i2c_paral_write_num = 0x400011e0;
phy_i2c_paral_write_mask = 0x400011e4;
phy_i2c_readReg = 0x400011e8;
phy_chip_i2c_writeReg = 0x400011ec;
phy_i2c_writeReg = 0x400011f0;
phy_i2c_readReg_Mask = 0x400011f4;
phy_set_txcap_reg = 0x400011f8;
phy_i2c_sar2_init_code = 0x400011fc;
phy_i2c_pkdet_set = 0x40001200;
phy_filter_dcap_set = 0x40001204;
phy_i2c_rc_cal_set = 0x40001208;
phy_ckgen_5g_cal = 0x4000120c;
phy_ckgen_2g_cal = 0x40001210;
phy_adc_rate_set = 0x40001214;
phy_dac_rate_set = 0x40001218;
phy_encode_i2c_master = 0x4000121c;
phy_i2c_master_fill = 0x40001220;
phy_band_reg = 0x40001224;
phy_open_fe_bb_clk = 0x40001228;
phy_get_mac_addr = 0x4000122c;
phy_set_mac_data = 0x40001230;
phy_rfcal_data_sub = 0x40001234;
phy_rf_cal_data_recovery = 0x40001238;
phy_rf_cal_data_backup = 0x4000123c;
phy_rfcal_data_check = 0x40001240;
phy_pbus_force_mode = 0x40001244;
phy_pbus_rd_addr_ = 0x40001248;
phy_pbus_force_test = 0x4000124c;
phy_pbus_rd = 0x40001250;
phy_pbus_debugmode = 0x40001254;
phy_pbus_workmode = 0x40001258;
phy_pbus_clear_reg = 0x4000125c;
phy_pbus_set_rxgain = 0x40001260;
phy_pbus_set_dco = 0x40001264;
phy_set_loopback_gain = 0x40001268;
phy_txcal_debuge_mode_ = 0x4000126c;
phy_txcal_work_mode = 0x40001270;
phy_write_pbus_mem = 0x40001274;
phy_set_pbus_mem_2g = 0x40001278;
phy_set_pbus_mem_5g = 0x4000127c;
phy_pbus_reg_store = 0x40001280;
phy_set_pbus_mem = 0x40001284;
phy_get_rx_pbus_freq = 0x40001288;
phy_set_rx_pbus_freq = 0x4000128c;
phy_pbus_xpd_iq_path = 0x40001290;
phy_pbus_set_rftx1_5g = 0x40001294;
phy_pwdet_reg_init = 0x40001298;
phy_pwdet_sar2_init = 0x4000129c;
phy_en_pwdet = 0x400012a0;
phy_get_sar_sig_ref = 0x400012a4;
phy_pwdet_tone_start = 0x400012a8;
phy_get_tone_sar_dout = 0x400012ac;
phy_get_fm_sar_dout = 0x400012b0;
phy_txtone_linear_pwr = 0x400012b4;
phy_linear_to_db = 0x400012b8;
phy_get_power_db = 0x400012bc;
phy_meas_tone_pwr_db = 0x400012c0;
phy_pwdet_wait_idle = 0x400012c4;
phy_pkdet_vol_start = 0x400012c8;
phy_read_sar_dout = 0x400012cc;
phy_read_sar2_code = 0x400012d0;
phy_get_sar2_vol = 0x400012d4;
phy_get_pkdet_data = 0x400012d8;
phy_rx_pkdet_dc_cal = 0x400012dc;
phy_disable_agc = 0x400012e0;
phy_enable_agc = 0x400012e4;
phy_disable_cca = 0x400012e8;
phy_enable_cca = 0x400012ec;
phy_write_gain_mem = 0x400012f0;
phy_bb_bss_cbw40_dig = 0x400012f4;
phy_tx_paon_set = 0x400012f8;
phy_i2cmst_reg_init = 0x400012fc;
phy_bt_gain_offset = 0x40001300;
phy_fe_reg_init = 0x40001304;
phy_mac_enable_bb = 0x40001308;
phy_bb_wdg_cfg = 0x4000130c;
phy_fe_txrx_reset = 0x40001310;
phy_set_rx_comp_ = 0x40001314;
phy_agc_max_gain_set = 0x40001318;
phy_agc_reg_init = 0x4000131c;
phy_bb_reg_init = 0x40001320;
phy_open_i2c_xpd = 0x40001324;
phy_force_txrx_off = 0x40001328;
phy_txiq_set_reg = 0x4000132c;
phy_rxiq_set_reg = 0x40001330;
phy_rx_gain_force = 0x40001334;
phy_set_txclk_en = 0x40001338;
phy_set_rxclk_en = 0x4000133c;
phy_start_tx_tone_step = 0x40001340;
phy_stop_tx_tone = 0x40001344;
phy_bb_wdg_test_en = 0x40001348;
phy_noise_floor_auto_set = 0x4000134c;
phy_read_hw_noisefloor = 0x40001350;
phy_iq_corr_enable = 0x40001354;
phy_wifi_agc_sat_gain = 0x40001358;
phy_bbpll_cal = 0x4000135c;
phy_ant_init = 0x40001360;
phy_wifi_fbw_sel = 0x40001364;
phy_bt_filter_reg = 0x40001368;
phy_rx_sense_set = 0x4000136c;
phy_tx_state_set = 0x40001370;
phy_close_pa = 0x40001374;
phy_freq_correct = 0x40001378;
phy_set_pbus_reg = 0x4000137c;
phy_wifi_rifs_mode_en = 0x40001380;
phy_rfagc_disable = 0x40001384;
phy_pkdadc_set = 0x40001388;
phy_nrx_freq_set = 0x4000138c;
phy_fe_adc_on = 0x40001390;
phy_force_pwr_index = 0x40001394;
phy_fft_scale_force = 0x40001398;
phy_force_rx_gain = 0x4000139c;
phy_wifi_enable_set = 0x400013a0;
phy_bb_cbw_chan_cfg = 0x400013a4;
phy_vht_support = 0x400013a8;
phy_csidump_force_lltf_cfg = 0x400013ac;
phy_hemu_ru26_good_res = 0x400013b0;
phy_bb_cfo_cfg = 0x400013b4;
phy_freq_band_reg_set = 0x400013b8;
phy_set_bb_wdg = 0x400013bc;
phy_sifs_reg_init = 0x400013c0;
phy_bbtx_outfilter = 0x400013c4;
phy_bb_wdt_rst_enable = 0x400013c8;
phy_bb_wdt_int_enable = 0x400013cc;
phy_bb_wdt_timeout_clear = 0x400013d0;
phy_bb_wdt_get_status = 0x400013d4;
phy_freq_to_chan = 0x400013d8;
phy_chan_to_freq = 0x400013dc;
phy_freq_to_index = 0x400013e0;
phy_iq_est_enable = 0x400013e4;
phy_iq_est_disable = 0x400013e8;
phy_dc_iq_est = 0x400013ec;
phy_set_cal_rxdc = 0x400013f0;
phy_rxiq_get_mis = 0x400013f4;
phy_rxiq_cover_mg_mp = 0x400013f8;
phy_rfcal_rxiq = 0x400013fc;
phy_get_rfcal_rxiq_data = 0x40001400;
phy_get_dco_comp = 0x40001404;
phy_pbus_rx_dco_cal = 0x40001408;
phy_rxdc_est_min = 0x4000140c;
phy_rx_dco_cal_1step = 0x40001410;
phy_set_lb_txiq = 0x40001414;
phy_rxiq_opt = 0x40001418;
phy_set_rx_gain_cal_iq = 0x4000141c;
phy_set_rx_gain_cal_dc = 0x40001420;
phy_spur_reg_write = 0x40001424;
phy_spur_cal = 0x40001428;
phy_spur_coef_cfg = 0x4000142c;
phy_bb_gain_index = 0x40001430;
phy_rfrx_gain_index = 0x40001434;
phy_gen_rx_gain_table = 0x40001438;
phy_get_rxbb_dc = 0x4000143c;
phy_wr_rx_gain_mem = 0x40001440;
phy_set_tsens_power_ = 0x40001444;
phy_get_tsens_value_ = 0x40001448;
phy_tsens_read_init = 0x4000144c;
phy_code_to_temp = 0x40001450;
phy_tsens_dac_to_index = 0x40001454;
phy_tsens_dac_cal = 0x40001458;
phy_tsens_code_read = 0x4000145c;
phy_tsens_temp_read = 0x40001460;
phy_tsens_temp_read_local = 0x40001464;
phy_temp_to_power_ = 0x40001468;
phy_bt_txdc_cal = 0x4000146c;
phy_bt_txiq_cal = 0x40001470;
phy_txdc_cal = 0x40001474;
phy_txdc_cal_pwdet = 0x40001478;
phy_txiq_get_mis_pwr = 0x4000147c;
phy_txiq_cover = 0x40001480;
phy_rfcal_txiq = 0x40001484;
phy_get_power_atten = 0x40001488;
phy_pwdet_ref_code = 0x4000148c;
phy_pwdet_code_cal = 0x40001490;
phy_rfcal_txcap = 0x40001494;
phy_txcap_setting = 0x40001498;
phy_get_cal_chan = 0x4000149c;
phy_get_chan_cal_index = 0x400014a0;
phy_get_chan_cap = 0x400014a4;
phy_freq_to_mbgain = 0x400014a8;
phy_rfcal_pwrctrl = 0x400014ac;
phy_get_pwdet_offset_ = 0x400014b0;
phy_tx_pwctrl_init_cal = 0x400014b4;
phy_tx_pwctrl_init = 0x400014b8;
phy_bt_tx_pwctrl_init = 0x400014bc;
phy_txbbgain_to_index = 0x400014c0;
phy_index_to_txbbgain = 0x400014c4;
phy_bt_get_tx_gain = 0x400014c8;
phy_dig_gain_check = 0x400014cc;
phy_wifi_get_tx_gain = 0x400014d0;
phy_wifi_11g_rate_chg = 0x400014d4;
phy_bt_chan_pwr_interp = 0x400014d8;
phy_set_tx_gain_mem = 0x400014dc;
phy_get_rate_fcc_index = 0x400014e0;
phy_get_chan_target_power = 0x400014e4;
phy_get_tx_gain_value = 0x400014e8;
phy_wifi_get_target_power = 0x400014ec;
phy_wifi_get_tx_tab_ = 0x400014f0;
phy_wifi_set_tx_gain = 0x400014f4;
phy_bt_get_tx_tab_ = 0x400014f8;
phy_bt_set_tx_gain = 0x400014fc;
phy_bt_tx_gain_init = 0x40001500;
phy_pbus_xpd_rx_off = 0x40001528;
phy_i2c_writeReg_Mask = 0x4000152c;
phy_pbus_xpd_rx_on = 0x40001530;
phy_pbus_xpd_tx_on = 0x40001534;
phy_get_romfuncs = 0x40001538;
phy_chip_set_chan_ana_ = 0x4000153c;
phy_pbus_xpd_tx_off = 0x40001540;
/* Data (.data, .bss, .rodata) */
phy_rom_phyFuns = 0x4085fb80;
phy_param_rom = 0x4085fc70;
phy_rom_phyFuns_eco1 = 0x4085fc6c;
phy_param_rom = 0x4085fc70;

120
components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.pp.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
@ -27,14 +27,14 @@ esf_buf_recycle = 0x40000bfc;
GetAccess = 0x40000c00;
hal_mac_is_low_rate_enabled = 0x40000c04;
hal_mac_tx_get_blockack = 0x40000c08;
/*hal_mac_tx_set_ppdu = 0x40000c0c;*/
hal_mac_tx_set_ppdu = 0x40000c0c;
hal_mac_tx_clr_mplen = 0x40000c10;
hal_mac_get_txq_state = 0x40000c14;
hal_mac_clr_txq_state = 0x40000c18;
hal_mac_get_txq_complete = 0x40000c1c;
hal_mac_deinit_twt_tx = 0x40000c20;
hal_mac_is_dma_enable = 0x40000c24;
/*hal_he_get_bss_color = 0x40000c28;*/
hal_he_get_bss_color = 0x40000c28;
hal_he_set_ersu = 0x40000c2c;
hal_he_get_mplen_addr_start = 0x40000c30;
hal_he_get_mplen_addr_end = 0x40000c34;
@ -51,11 +51,9 @@ hal_tsf_timer_set_target = 0x40000c5c;
hal_tsf_clear_soc_wakeup_request = 0x40000c60;
hal_get_tsf_time = 0x40000c64;
hal_get_sta_tsf = 0x40000c68;
dbg_hal_check_clr_mplen_bitmap = 0x40000c6c;
dbg_hal_check_set_mplen_bitmap = 0x40000c70;
ic_get_trc = 0x40000c74;
ic_mac_deinit = 0x40000c78;
/* ic_mac_init = 0x40000c7c; */
ic_mac_init = 0x40000c7c;
ic_interface_enabled = 0x40000c80;
is_lmac_idle = 0x40000c84;
ic_get_he_rts_threshold_bytes = 0x40000c88;
@ -101,7 +99,7 @@ mac_tx_set_plcp2 = 0x40000d24;
mac_tx_set_len = 0x40000d28;
mac_tx_set_htsig = 0x40000d2c;
mac_tx_set_vhtsig = 0x40000d30;
/*mac_tx_set_hesig = 0x40000d34;*/
mac_tx_set_hesig = 0x40000d34;
mac_tx_set_tb = 0x40000d38;
mac_tx_set_mplen = 0x40000d3c;
mac_tx_set_txop_q = 0x40000d40;
@ -109,17 +107,17 @@ mac_tx_set_pti = 0x40000d44;
pm_check_state = 0x40000d48;
pm_disable_dream_timer = 0x40000d4c;
pm_disable_sleep_delay_timer = 0x40000d50;
/*pm_dream = 0x40000d54;*/
pm_dream = 0x40000d54;
pm_mac_wakeup = 0x40000d58;
pm_mac_sleep = 0x40000d5c;
/*pm_enable_active_timer = 0x40000d60;*/
pm_enable_active_timer = 0x40000d60;
pm_enable_sleep_delay_timer = 0x40000d64;
pm_local_tsf_process = 0x40000d68;
pm_set_beacon_filter = 0x40000d6c;
/*pm_is_in_wifi_slice_threshold = 0x40000d70;*/
pm_is_waked = 0x40000d74;
/*pm_keep_alive = 0x40000d78;*/
/*pm_on_beacon_rx = 0x40000d7c;*/
pm_keep_alive = 0x40000d78;
pm_on_beacon_rx = 0x40000d7c;
pm_on_data_rx = 0x40000d80;
pm_on_data_tx = 0x40000d84;
pm_on_tbtt = 0x40000d88;
@ -129,31 +127,31 @@ pm_on_isr_set_twt_target = 0x40000d94;
pm_on_isr_twt_wake = 0x40000d98;
pm_on_tsf_timer = 0x40000d9c;
pm_on_twt_force_tx = 0x40000da0;
/*pm_parse_beacon = 0x40000da4;*/
/*pm_process_tim = 0x40000da8;*/
pm_parse_beacon = 0x40000da4;
pm_process_tim = 0x40000da8;
pm_rx_beacon_process = 0x40000dac;
pm_rx_data_process = 0x40000db0;
/*pm_sleep = 0x40000db4;*/
pm_sleep = 0x40000db4;
pm_sleep_for = 0x40000db8;
/*pm_tbtt_process = 0x40000dbc;*/
/*pm_tx_data_done_process = 0x40000dc0;*/
pm_tbtt_process = 0x40000dbc;
pm_tx_data_done_process = 0x40000dc0;
pm_allow_tx = 0x40000dc4;
pm_extend_tbtt_adaptive_servo = 0x40000dc8;
/*pm_scale_listen_interval = 0x40000dcc;*/
pm_scale_listen_interval = 0x40000dcc;
pm_parse_mbssid_element = 0x40000dd0;
pm_disconnected_wake = 0x40000dd4;
/*pm_tx_data_process = 0x40000dd8;*/
pm_tx_data_process = 0x40000dd8;
pm_is_twt_awake = 0x40000ddc;
pm_enable_twt_keep_alive = 0x40000de0;
pm_twt_on_tsf_timer = 0x40000de4;
/*pm_twt_process = 0x40000de8;*/
pm_twt_process = 0x40000de8;
pm_is_twt_start = 0x40000dec;
pm_twt_set_target_wdev_time = 0x40000df0;
pm_twt_set_target_tsf = 0x40000df4;
pm_enable_twt_keep_alive_timer = 0x40000df8;
/*pm_mac_try_enable_modem_state = 0x40000dfc;*/
pm_beacon_monitor_tbtt_timeout_process = 0x40000e00;
/*pm_update_next_tbtt = 0x40000e04;*/
pm_update_next_tbtt = 0x40000e04;
pm_twt_disallow_tx = 0x40000e08;
pm_clear_wakeup_signal = 0x40000e0c;
/*pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000e10;
@ -180,7 +178,7 @@ ppGetTxframe = 0x40000e60;
ppMapTxQueue = 0x40000e64;
ppProcTxSecFrame = 0x40000e68;
ppProcessRxPktHdr = 0x40000e6c;
/*ppProcessTxQ = 0x40000e70;*/
ppProcessTxQ = 0x40000e70;
ppRecordBarRRC = 0x40000e74;
ppRecycleAmpdu = 0x40000e78;
ppRecycleRxPkt = 0x40000e7c;
@ -222,7 +220,7 @@ pp_coex_tx_release = 0x40000f08;
ppAdd2AMPDUTail = 0x40000f0c;
ppDirectRecycleAmpdu = 0x40000f10;
ppRegressAmpdu = 0x40000f14;
/*pp_timer_do_process = 0x40000f18;*/
pp_timer_do_process = 0x40000f18;
rcGetAmpduSched = 0x40000f1c;
rcUpdateRxDone = 0x40000f20;
rc_get_trc = 0x40000f24;
@ -232,14 +230,14 @@ rcampduuprate = 0x40000f30;
rcClearCurAMPDUSched = 0x40000f34;
rcClearCurSched = 0x40000f38;
rcClearCurStat = 0x40000f3c;
/* rcGetSched = 0x40000f40; */
rcGetSched = 0x40000f40;
rcLowerSched = 0x40000f44;
rcSetTxAmpduLimit = 0x40000f48;
rcTxUpdatePer = 0x40000f4c;
/*rcUpdateAckSnr = 0x40000f50;*/
rcUpdateAckSnr = 0x40000f50;
rcUpdateRate = 0x40000f54;
/*rcUpdateTxDone = 0x40000f58;*/
/*rcUpdateTxDoneAmpdu2 = 0x40000f5c;*/
rcUpdateTxDone = 0x40000f58;
rcUpdateTxDoneAmpdu2 = 0x40000f5c;
rcUpSched = 0x40000f60;
rcReachRetryLimit = 0x40000f64;
rcGetDCMMaxRate = 0x40000f68;
@ -264,7 +262,7 @@ wDev_AppendRxBlocks = 0x40000fb0;
wDev_DiscardFrame = 0x40000fb4;
wDev_GetNoiseFloor = 0x40000fb8;
wDev_IndicateAmpdu = 0x40000fbc;
/*wDev_IndicateFrame = 0x40000fc0;*/
wDev_IndicateFrame = 0x40000fc0;
wdev_mac_reg_load = 0x40000fc4;
wdev_mac_reg_store = 0x40000fc8;
wdev_mac_special_reg_load = 0x40000fcc;
@ -272,7 +270,7 @@ wdev_mac_special_reg_store = 0x40000fd0;
wdev_mac_wakeup = 0x40000fd4;
wdev_mac_sleep = 0x40000fd8;
wDev_ProcessFiq = 0x40000fdc;
/*wDev_ProcessRxSucData = 0x40000fe0;*/
wDev_ProcessRxSucData = 0x40000fe0;
wdevProcessRxSucDataAll = 0x40000fe4;
wdev_csi_len_align = 0x40000fe8;
wDev_IndicateBeaconMemoryFrame = 0x40000fec;
@ -284,8 +282,6 @@ wdev_process_tsf_timer = 0x40001000;
wdev_process_beacon_filter = 0x40001004;
wdev_process_mac_modem_beacon_miss = 0x40001008;
config_is_cache_tx_buf_enabled = 0x4000100c;
config_get_wifi_feature_capabilities = 0x40001010;
config_get_wifi_ampdu_tx_hetb_tid_limit = 0x40001014;
esp_test_disable_tx_statistics = 0x40001018;
esp_test_enable_tx_statistics = 0x4000101c;
esp_test_clr_tx_statistics = 0x40001020;
@ -335,12 +331,6 @@ is_use_muedca = 0x400010cc;
pwr_hal_clear_mac_modem_state_wakeup_protect_signal = 0x400010d0;
get_estimated_batime = 0x400010d4;
get_sublen_offset = 0x400010d8;
pm_coex_schm_overall_period_get = 0x40001504;
ppRemoveHEAMPDUflags = 0x4000150c;
tsf_hal_get_tbtt_interval = 0x40001510;
/*pm_get_tbtt_count = 0x4000151c;*/
tsf_hal_get_time = 0x40001520;
tsf_hal_get_counter_value = 0x40001524;
/* Data (.data, .bss, .rodata) */
our_instances_ptr = 0x4004ffe0;
pTxRx = 0x4085ff74;
@ -452,3 +442,57 @@ he_max_apep_length = 0x4004fd40;
g_pp_timer_info_ptr = 0x4085fc94;
g_rts_threshold_bytes_ptr = 0x4085fc90;
g_he_max_apep_length_tab_ptr = 0x4085fc8c;
/* ROM function interface esp32c5.rom.eco1.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group rom_pp_eco1
***************************************/
/* Functions */
pm_coex_schm_overall_period_get = 0x40001504;
pm_coex_pwr_update = 0x40001508;
ppRemoveHEAMPDUflags = 0x4000150c;
tsf_hal_get_tbtt_interval = 0x40001510;
pm_beacon_monitor_tbtt_start = 0x40001514;
pm_save_tbtt_info = 0x40001518;
pm_get_tbtt_count = 0x4000151c;
tsf_hal_get_time = 0x40001520;
tsf_hal_get_counter_value = 0x40001524;
/* ROM function interface esp32c5.rom.eco2.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group rom_pp_eco2
***************************************/
/* Functions */
pm_enable_max_idle_timer = 0x400015b8;
pm_beacon_offset_is_enabled = 0x400015bc;
pm_beacon_offset_is_sampling = 0x400015c0;
pm_beacon_offset_add_total_counter = 0x400015c4;
pm_beacon_offset_add_loss_counter = 0x400015c8;
pm_beacon_offset_check = 0x400015cc;
pm_beacon_offset_get_average = 0x400015d0;
pm_beacon_offset_get_expect = 0x400015d4;
pm_beacon_offset_get_params = 0x400015d8;
/* Data (.data, .bss, .rodata) */
s_tbttstart_ptr = 0x4085fc68;
s_pm_beacon_offset_ptr = 0x4085fc64;
s_pm_beacon_offset_config_ptr = 0x4085fc60;

6
components/esp_rom/esp32c5/ld/esp32c5.rom.rvfp.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.rvfp.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/

6
components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld
View File

@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32c5.rom.spiflash.ld for esp32c5
*
*
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
* Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
*
* Compatible with ROM where ECO version equal or greater to 0.
* Compatible with ROM where ECO version equal or greater to 2.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/

2
components/esp_rom/esp32c5/ld/esp32c5.rom.systimer.ld
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/esp_rom/esp32c5/ld/esp32c5.rom.version.ld
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

2
components/esp_system/ld/esp32c5/memory.ld.in
View File

@ -16,7 +16,7 @@
#include "ld.common"
#define SRAM_SEG_START 0x40800000
#define SRAM_SEG_END 0x4084E9A0 /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_SEG_END 0x4084E5A0 /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_SEG_SIZE SRAM_SEG_END - SRAM_SEG_START
/*

8
components/soc/esp32c5/include/soc/interrupts.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -57,6 +57,8 @@ typedef enum {
ETS_HP_APM_M3_INTR_SOURCE,
ETS_HP_APM_M4_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_CPU_APM_M0_INTR_SOURCE,
ETS_CPU_APM_M1_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
@ -77,9 +79,9 @@ typedef enum {
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_APB_ADC_INTR_SOURCE = 62, /**< interrupt of APB ADC, LEVEL*/
ETS_APB_ADC_INTR_SOURCE = 64, /**< interrupt of APB ADC, LEVEL*/
ETS_TEMPERATURE_SENSOR_INTR_SOURCE = ETS_APB_ADC_INTR_SOURCE,
ETS_MCPWM0_INTR_SOURCE = 63, /**< interrupt of MCPWM0, LEVEL*/
ETS_MCPWM0_INTR_SOURCE = 65, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
ETS_PARL_IO_RX_INTR_SOURCE,

2
components/soc/esp32c5/include/soc/soc.h
View File

@ -202,7 +202,7 @@
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4085e9a0
#define SOC_ROM_STACK_START 0x4085e5a0
#define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.

4
components/soc/esp32c5/interrupts.c
View File

@ -49,6 +49,8 @@ const char *const esp_isr_names[] = {
[ETS_HP_APM_M3_INTR_SOURCE] = "HP_APM_M3",
[ETS_HP_APM_M4_INTR_SOURCE] = "HP_APM_M4",
[ETS_LP_APM0_INTR_SOURCE] = "LP_APM0",
[ETS_CPU_APM_M0_INTR_SOURCE] = "CPU_APM_M0",
[ETS_CPU_APM_M1_INTR_SOURCE] = "CPU_APM_M1",
[ETS_MSPI_INTR_SOURCE] = "MSPI",
[ETS_I2S0_INTR_SOURCE] = "I2S0",
[ETS_UHCI0_INTR_SOURCE] = "UHCI0",
@ -74,6 +76,8 @@ const char *const esp_isr_names[] = {
[ETS_PCNT_INTR_SOURCE] = "PCNT",
[ETS_PARL_IO_TX_INTR_SOURCE] = "PARL_IO_TX",
[ETS_PARL_IO_RX_INTR_SOURCE] = "PARL_IO_RX",
[ETS_SLC0_INTR_SOURCE] = "SLC0",
[ETS_SLC1_INTR_SOURCE] = "SLC1",
[ETS_DMA_IN_CH0_INTR_SOURCE] = "DMA_IN_CH0",
[ETS_DMA_IN_CH1_INTR_SOURCE] = "DMA_IN_CH1",
[ETS_DMA_IN_CH2_INTR_SOURCE] = "DMA_IN_CH2",