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Merge branch 'feature/esp32c61_eco3_gpio_update' into 'master'

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change(gpio): add GPIO25~29 for ESP32C61 ECO3

Closes IDF-12874 and IDF-9316

See merge request espressif/esp-idf!39714
This commit is contained in:
Song Ruo Jing
2025-06-10 16:17:05 +08:00
parent f4e8813d45 da4ac0c56a
commit 0fa5b07c7e
15 changed files with 97 additions and 37 deletions
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28
components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -44,7 +44,7 @@ typedef enum {
/**
* @brief Change GPIO(0-24) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* @brief Change GPIO(0-29) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
@@ -61,7 +61,7 @@ typedef enum {
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Sample the value of GPIO input pins(0-24) and returns a bitmask.
* @brief Sample the value of GPIO input pins(0-29) and returns a bitmask.
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
@@ -93,7 +93,7 @@ void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~24
* @param uint32_t gpio : gpio number, 0~29
* gpio == 0x30, input 0 to signal
* gpio == 0x20, input 1 to signal
*
@@ -108,10 +108,10 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~24
* @param uint32_t gpio : gpio number, 0~29
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x80, cancel output put to the gpio
* signal_idx == 0x100, cancel output put to the gpio
*
* @param bool out_inv : the signal output is invert or not
*
@@ -124,7 +124,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~24
* @param uint32_t gpio_num : gpio number, 0~29
*
* @return None
*/
@@ -133,7 +133,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~24
* @param uint32_t gpio_num : gpio number, 0~29
*
* @param uint32_t drv : 0-3
*
@@ -144,7 +144,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~24
* @param uint32_t gpio_num : gpio number, 0~29
*
* @return None
*/
@@ -153,7 +153,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~24
* @param uint32_t gpio_num : gpio number, 0~29
*
* @return None
*/
@@ -162,7 +162,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~24
* @param uint32_t gpio_num : gpio number, 0~29
*
* @return None
*/
@@ -171,7 +171,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~24
* @param uint32_t gpio_num : gpio number, 0~29
*
* @return None
*/
@@ -180,7 +180,7 @@ void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~24
* @param uint32_t gpio_num : gpio number, 0~29
*
* @return None
*/
@@ -189,7 +189,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~24
* @param uint32_t gpio_num : gpio number, 0~29
*
* @return None
*/

7
components/soc/esp32c61/gpio_periph.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -32,6 +32,11 @@ const uint32_t GPIO_HOLD_MASK[] = {
BIT(22), //GPIO22
BIT(23), //GPIO23
BIT(24), //GPIO24
BIT(25), //GPIO25
BIT(26), //GPIO26
BIT(27), //GPIO27
BIT(28), //GPIO28
BIT(29), //GPIO29
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

8
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
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@@ -385,7 +385,7 @@ config SOC_GPIO_PORT
config SOC_GPIO_PIN_COUNT
int
default 25
default 30
config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
@@ -409,11 +409,11 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
config SOC_GPIO_IN_RANGE_MAX
int
default 24
default 29
config SOC_GPIO_OUT_RANGE_MAX
int
default 24
default 29
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
@@ -429,7 +429,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x1FFFF80
default 0x3FFFFF80
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool

7
components/soc/esp32c61/include/soc/gpio_num.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -40,6 +40,11 @@ typedef enum {
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
GPIO_NUM_28 = 28, /*!< GPIO28, input and output */
GPIO_NUM_29 = 29, /*!< GPIO29, input and output */
GPIO_NUM_MAX,
} gpio_num_t;

10
components/soc/esp32c61/include/soc/soc_caps.h
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@@ -161,7 +161,7 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C61 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 25
#define SOC_GPIO_PIN_COUNT 30
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
@@ -178,16 +178,16 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 24
#define SOC_GPIO_OUT_RANGE_MAX 24
#define SOC_GPIO_IN_RANGE_MAX 29
#define SOC_GPIO_OUT_RANGE_MAX 29
// GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_24)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x1FFFF80ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_29)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x3FFFFF80ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)

5
components/soc/esp32c61/register/soc/io_mux_reg.h
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@@ -112,9 +112,8 @@ extern "C" {
#define EXT_OSC_SLOW_GPIO_NUM 0
#define MAX_RTC_GPIO_NUM 6
#define MAX_PAD_GPIO_NUM 24
#define MAX_GPIO_NUM 28
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define MAX_PAD_GPIO_NUM 29
#define MAX_GPIO_NUM 33
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check

7
components/soc/esp32c61/rtc_io_periph.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -32,4 +32,9 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-1,//GPIO22
-1,//GPIO23
-1,//GPIO24
-1,//GPIO25
-1,//GPIO26
-1,//GPIO27
-1,//GPIO28
-1,//GPIO29
};

1
components/soc/esp32h2/register/soc/io_mux_reg.h
View File

@@ -163,7 +163,6 @@
#define MAX_RTC_GPIO_NUM 14 // GPIO7~14 are the pads with LP function
#define MAX_PAD_GPIO_NUM 27
#define MAX_GPIO_NUM 31
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE

1
components/soc/esp32h21/register/soc/io_mux_reg.h
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@@ -150,7 +150,6 @@ extern "C" {
#define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function
#define MAX_PAD_GPIO_NUM 25
#define MAX_GPIO_NUM 29
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE

1
components/soc/esp32h4/register/soc/io_mux_reg.h
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@@ -133,7 +133,6 @@ extern "C" {
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 39
#define MAX_GPIO_NUM 39
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check

1
components/soc/esp32p4/register/soc/io_mux_reg.h
View File

@@ -197,7 +197,6 @@
#define MAX_RTC_GPIO_NUM 15
#define MAX_PAD_GPIO_NUM 54
#define MAX_GPIO_NUM 56
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE

27
docs/en/api-reference/peripherals/gpio/esp32c61.inc
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@@ -9,7 +9,7 @@
.. gpio-summary
The {IDF_TARGET_NAME} chip features 25 physical GPIO pins (GPIO0 ~ GPIO24). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The {IDF_TARGET_NAME} chip features 30 physical GPIO pins (GPIO0 ~ GPIO29). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
@@ -147,6 +147,31 @@ The table below provides more information on pin usage, and please note the comm
-
-
* - GPIO25
-
-
-
* - GPIO26
-
-
-
* - GPIO27
-
-
-
* - GPIO28
-
-
-
* - GPIO29
-
-
-
.. note::
- Some pins are used as strapping pins, which can be used to select in which boot mode to load the chip, etc.. The details can be found in `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`_ > ``Strapping Pins``.

27
docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc
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@@ -9,7 +9,7 @@
.. gpio-summary
{IDF_TARGET_NAME} 芯片具有 25 个物理 GPIO 管脚（GPIO0 ~ GPIO24）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
{IDF_TARGET_NAME} 芯片具有 30 个物理 GPIO 管脚（GPIO0 ~ GPIO29）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。
@@ -147,6 +147,31 @@
-
-
* - GPIO25
-
-
-
* - GPIO26
-
-
-
* - GPIO27
-
-
-
* - GPIO28
-
-
-
* - GPIO29
-
-
-
.. note::
- 其中一些管脚被用作 Strapping 管脚，可用于选择加载芯片的启动模式等。详细信息请见 `ESP32-C61 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_ > ``Strapping 管脚``。

2
examples/common_components/env_caps/esp32c61/Kconfig.env_caps
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@@ -4,7 +4,7 @@ config ENV_GPIO_RANGE_MIN
config ENV_GPIO_RANGE_MAX
int
default 24
default 29
config ENV_GPIO_IN_RANGE_MAX
int

2
examples/common_components/env_caps/esp32p4/Kconfig.env_caps
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@@ -4,7 +4,7 @@ config ENV_GPIO_RANGE_MIN
config ENV_GPIO_RANGE_MAX
int
default 56
default 54
config ENV_GPIO_IN_RANGE_MAX
int