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Merge branch 'refactor/mspi_clk_src_refactor' into 'master'

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mspi: clk src refactor

Closes IDF-10464

See merge request espressif/esp-idf!35365
This commit is contained in:
Armando (Dou Yiwen)
2024-12-12 10:10:36 +08:00
parent 1f4ea21092 6528ab5971
commit 14b290a83a
25 changed files with 196 additions and 161 deletions
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2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
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@ -53,7 +53,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
}

2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
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@ -51,7 +51,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
mspi_ll_fast_set_hs_divider(6);
}

6
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
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@ -19,7 +19,7 @@
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
#include "hal/spimem_flash_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "esp_private/bootloader_flash_internal.h"
@ -44,8 +44,8 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
_spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
_spimem_ctrlr_ll_set_core_clock(0, 6);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
_mspi_timing_ll_set_flash_core_clock(0, 80);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

22
components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c
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@ -16,6 +16,7 @@
#include "hal/spi_flash_hal.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "esp_private/mspi_timing_tuning.h"
#include "esp_private/mspi_timing_config.h"
#include "mspi_timing_by_mspi_delay.h"
@ -23,16 +24,11 @@
#include "mspi_timing_by_flash_delay.h"
#if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY || SOC_MEMSPI_TIMING_TUNING_BY_DQS || SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY
#include "mspi_timing_tuning_configs.h"
#include "hal/mspi_timing_tuning_ll.h"
#endif
#if SOC_MEMSPI_CLK_SRC_IS_INDEPENDENT
#include "hal/spimem_flash_ll.h"
#endif
#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-10464
#include "hal/mspi_timing_tuning_ll.h"
#endif
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
#include "esp_ipc_isr.h"
#endif
@ -469,13 +465,9 @@ void mspi_timing_psram_tuning(void)
*----------------------------------------------------------------------------*/
void mspi_timing_enter_low_speed_mode(bool control_spi1)
{
#if SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-10464
mspi_ll_clock_src_sel(MSPI_CLK_SRC_XTAL);
#else
spimem_flash_ll_set_clock_source(MSPI_CLK_SRC_ROM_DEFAULT);
#if MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_ROM_DEFAULT);
#endif
#endif //SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
/**
@ -509,13 +501,9 @@ void mspi_timing_enter_low_speed_mode(bool control_spi1)
*/
void mspi_timing_enter_high_speed_mode(bool control_spi1)
{
#if SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61// TODO: IDF-10464
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
#else
spimem_flash_ll_set_clock_source(MSPI_CLK_SRC_DEFAULT);
#if MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
#endif
#endif //SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
/**

2
components/esp_hw_support/mspi_timing_tuning/port/esp32p4/mspi_timing_config.c
View File

@ -40,7 +40,7 @@ void mspi_timing_config_set_flash_clock(uint32_t flash_freq_mhz, mspi_timing_spe
#if MSPI_TIMING_FLASH_NEEDS_TUNING
assert(HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel == 1);
uint32_t core_clock_mhz = MSPI_TIMING_SPLL_FREQ_MHZ / MSPI_TIMING_LL_FLASH_CORE_CLK_DIV;
uint32_t core_clock_mhz = MSPI_TIMING_SPLL_FREQ_MHZ / MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV;
assert(core_clock_mhz == 120);
uint32_t freqdiv = core_clock_mhz / flash_freq_mhz;

7
components/hal/esp32/include/hal/mspi_timing_tuning_ll.h Normal file
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@ -0,0 +1,7 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

7
components/hal/esp32c2/include/hal/mspi_timing_tuning_ll.h Normal file
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@ -0,0 +1,7 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

7
components/hal/esp32c3/include/hal/mspi_timing_tuning_ll.h Normal file
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@ -0,0 +1,7 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

17
components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h
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@ -21,21 +21,24 @@ extern "C" {
/************************** MSPI pll clock configurations **************************/
/**
* @brief Select mspi clock source
/*
* @brief Select FLASH clock source
*
* @param clk_src the clock source of mspi clock
* @param mspi_id mspi_id
* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
*/
static inline __attribute__((always_inline)) void mspi_ll_clock_src_sel(soc_periph_mspi_clk_src_t clk_src)
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
{
HAL_ASSERT(mspi_id == 0);
switch (clk_src) {
case MSPI_CLK_SRC_XTAL:
case FLASH_CLK_SRC_XTAL:
PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
break;
case MSPI_CLK_SRC_RC_FAST:
case FLASH_CLK_SRC_RC_FAST:
PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
break;
case MSPI_CLK_SRC_SPLL:
case FLASH_CLK_SRC_SPLL:
PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
break;
default:

7
components/hal/esp32c6/include/hal/mspi_timing_tuning_ll.h Normal file
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@ -0,0 +1,7 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

17
components/hal/esp32c61/include/hal/mspi_timing_tuning_ll.h
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@ -21,21 +21,24 @@ extern "C" {
/************************** MSPI pll clock configurations **************************/
/**
* @brief Select mspi clock source
/*
* @brief Select FLASH clock source
*
* @param clk_src the clock source of mspi clock
* @param mspi_id mspi_id
* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
*/
static inline __attribute__((always_inline)) void mspi_ll_clock_src_sel(soc_periph_mspi_clk_src_t clk_src)
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
{
HAL_ASSERT(mspi_id == 0);
switch (clk_src) {
case MSPI_CLK_SRC_XTAL:
case FLASH_CLK_SRC_XTAL:
PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
break;
case MSPI_CLK_SRC_RC_FAST:
case FLASH_CLK_SRC_RC_FAST:
PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
break;
case MSPI_CLK_SRC_SPLL:
case FLASH_CLK_SRC_SPLL:
PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
break;
default:

55
components/hal/esp32h2/include/hal/mspi_timing_tuning_ll.h Normal file
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@ -0,0 +1,55 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
//Timing tuning not applied, and flash has its own clock source. Can change flash clock source
#define MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE 1
/************************** MSPI pll clock configurations **************************/
/*
* @brief Select FLASH clock source
*
* @param mspi_id mspi_id
* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
*/
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
{
HAL_ASSERT(mspi_id == 0);
switch (clk_src) {
case FLASH_CLK_SRC_XTAL:
PCR.mspi_conf.mspi_clk_sel = 0;
break;
case FLASH_CLK_SRC_RC_FAST:
PCR.mspi_conf.mspi_clk_sel = 1;
break;
case FLASH_CLK_SRC_PLL_F64M:
PCR.mspi_conf.mspi_clk_sel = 2;
break;
case FLASH_CLK_SRC_PLL_F48M:
PCR.mspi_conf.mspi_clk_sel = 3;
break;
default:
HAL_ASSERT(false);
}
}
#ifdef __cplusplus
}
#endif

21
components/hal/esp32h2/include/hal/spimem_flash_ll.h
View File

@ -474,27 +474,6 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
dev->ctrl.val = ctrl.val;
}
__attribute__((always_inline))
static inline void spimem_flash_ll_set_clock_source(soc_periph_mspi_clk_src_t clk_src)
{
switch (clk_src) {
case MSPI_CLK_SRC_XTAL:
PCR.mspi_conf.mspi_clk_sel = 0;
break;
case MSPI_CLK_SRC_RC_FAST:
PCR.mspi_conf.mspi_clk_sel = 1;
break;
case MSPI_CLK_SRC_PLL_F64M:
PCR.mspi_conf.mspi_clk_sel = 2;
break;
case MSPI_CLK_SRC_PLL_F48M:
PCR.mspi_conf.mspi_clk_sel = 3;
break;
default:
HAL_ASSERT(false);
}
}
/**
* Set clock frequency to work at.
*

50
components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h
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@ -23,6 +23,7 @@
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/spi_mem_c_reg.h"
#include "soc/spi1_mem_c_reg.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
@ -31,7 +32,8 @@ extern "C" {
#define MSPI_TIMING_LL_MSPI_ID_0 0
#define MSPI_TIMING_LL_MSPI_ID_1 1
#define MSPI_TIMING_LL_FLASH_CORE_CLK_DIV 4
#define MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV 4
#define MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV 6
#define MSPI_TIMING_LL_FLASH_FDUMMY_RIN_SUPPORTED 1
#define MSPI_TIMING_LL_FLASH_OCT_MASK (SPI_MEM_C_FCMD_OCT | SPI_MEM_C_FADDR_OCT | SPI_MEM_C_FDIN_OCT | SPI_MEM_C_FDOUT_OCT)
@ -238,6 +240,41 @@ static inline void mspi_timing_ll_pin_drv_set(uint8_t drv)
/*---------------------------------------------------------------
Flash tuning
---------------------------------------------------------------*/
/*
* @brief Select FLASH clock source
*
* @param mspi_id mspi_id
* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
*/
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
{
HAL_ASSERT(mspi_id == MSPI_TIMING_LL_MSPI_ID_0);
uint32_t clk_val = 0;
switch (clk_src) {
case FLASH_CLK_SRC_XTAL:
clk_val = 0;
break;
case FLASH_CLK_SRC_SPLL:
clk_val = 1;
break;
case FLASH_CLK_SRC_CPLL:
clk_val = 2;
break;
default:
HAL_ASSERT(false);
break;
}
HP_SYS_CLKRST.soc_clk_ctrl0.reg_flash_sys_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_pll_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel = clk_val;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define mspi_timing_ll_set_flash_clk_src(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mspi_timing_ll_set_flash_clk_src(__VA_ARGS__)
/**
* Set MSPI Flash core clock
*
@ -247,12 +284,15 @@ static inline void mspi_timing_ll_pin_drv_set(uint8_t drv)
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_core_clock(int spi_num, uint32_t core_clk_mhz)
{
(void)spi_num;
HAL_ASSERT(spi_num == MSPI_TIMING_LL_MSPI_ID_0);
if (core_clk_mhz == 120) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl00, reg_flash_core_clk_div_num, (MSPI_TIMING_LL_FLASH_CORE_CLK_DIV - 1));
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl00, reg_flash_core_clk_div_num, (MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV - 1));
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 1;
} else if (core_clk_mhz == 80) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl00, reg_flash_core_clk_div_num, (MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV - 1));
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 1;
} else {
//ESP32P4 flash timing tuning is based on SPLL==480MHz, flash_core_clock==120MHz. We add assertion here to ensure this
//ESP32P4 flash timing tuning is based on SPLL==480MHz, flash_core_clock==120MHz / 80MHz. We add assertion here to ensure this
HAL_ASSERT(false);
}
}
@ -297,7 +337,7 @@ static inline void mspi_timing_ll_set_flash_clock(uint8_t spi_num, uint32_t freq
__attribute__((always_inline))
static inline void mspi_timinng_ll_enable_flash_timing_adjust_clk(uint8_t spi_num)
{
(void)spi_num;
HAL_ASSERT(spi_num == MSPI_TIMING_LL_MSPI_ID_0);
REG_GET_BIT(SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CLK_ENA);
}

53
components/hal/esp32p4/include/hal/spimem_flash_ll.h
View File

@ -733,59 +733,6 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou
dev->ctrl.wp_reg = out_lev;
}
/*
* @brief Select FLASH clock source
*
* @param mspi_id mspi_id
* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
*/
__attribute__((always_inline))
static inline void _spimem_flash_ll_select_clk_source(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
{
(void)mspi_id;
uint32_t clk_val = 0;
switch (clk_src) {
case FLASH_CLK_SRC_XTAL:
clk_val = 0;
break;
case FLASH_CLK_SRC_SPLL:
clk_val = 1;
break;
case FLASH_CLK_SRC_CPLL:
clk_val = 2;
break;
default:
HAL_ASSERT(false);
break;
}
HP_SYS_CLKRST.soc_clk_ctrl0.reg_flash_sys_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_pll_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel = clk_val;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define spimem_flash_ll_select_clk_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_flash_ll_select_clk_source(__VA_ARGS__)
/**
* @brief Set FLASH core clock
*
* @param mspi_id mspi_id
* @param freqdiv Divider value
*/
__attribute__((always_inline))
static inline void _spimem_ctrlr_ll_set_core_clock(uint8_t mspi_id, uint32_t freqdiv)
{
(void)mspi_id;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl00, reg_flash_core_clk_div_num, freqdiv - 1);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define spimem_ctrlr_ll_set_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_ctrlr_ll_set_core_clock(__VA_ARGS__)
/**
* @brief Disable FLASH MSPI clock
*

7
components/hal/esp32s2/include/hal/mspi_timing_tuning_ll.h Normal file
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@ -0,0 +1,7 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//For compatibility

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@ -1131,10 +1131,6 @@ config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2

18
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@ -488,20 +488,20 @@ typedef enum {
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
} soc_periph_parlio_clk_src_t;
//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MSPI digital controller
* @brief Array initializer for all supported clock sources of FLASH MSPI controller
*/
#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
/**
* @brief MSPI digital controller clock source
* @brief FLASH MSPI controller clock source
*/
typedef enum {
MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */
MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_mspi_clk_src_t;
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
FLASH_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum { // TODO

1
components/soc/esp32c5/include/soc/soc_caps.h
View File

@ -461,7 +461,6 @@
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
#define SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
// TODO: [ESP32C5] IDF-8707

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@ -815,10 +815,6 @@ config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2

20
components/soc/esp32c61/include/soc/clk_tree_defs.h
View File

@ -348,21 +348,21 @@ typedef enum {
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MSPI digital controller
* @brief Array initializer for all supported clock sources of FLASH MSPI controller
*/
#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
/**
* @brief MSPI digital controller clock source
* @brief FLASH MSPI controller clock source
*/
typedef enum {
MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */
MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL, /*!< Select PLL_F64M as the default clock choice */
MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_mspi_clk_src_t;
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
FLASH_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL, /*!< Select PLL_F64M as the default clock choice */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum {

1
components/soc/esp32c61/include/soc/soc_caps.h
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@ -345,7 +345,6 @@
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
#define SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -1107,10 +1107,6 @@ config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED
bool
default y
config SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2

22
components/soc/esp32h2/include/soc/clk_tree_defs.h
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@ -482,22 +482,22 @@ typedef enum {
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_parlio_clk_src_t;
//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MSPI digital controller
* @brief Array initializer for all supported clock sources of FLASH MSPI controller
*/
#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M}
#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M}
/**
* @brief MSPI digital controller clock source
* @brief FLASH MSPI controller clock source
*/
typedef enum {
MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MSPI_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */
MSPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */
MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_mspi_clk_src_t;
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
FLASH_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */
FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum {

1
components/soc/esp32h2/include/soc/soc_caps.h
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@ -431,7 +431,6 @@
#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1
#define SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units