Merge branch 'fix/fix_intr_alloc_expected_result' into 'master'

fix(ci): fix expected intr_dump result

Closes IDFCI-1790

See merge request espressif/esp-idf!25459
This commit is contained in:
Lu Ze Yu
2023-08-22 15:21:42 +08:00
4 changed files with 24 additions and 24 deletions

View File

@@ -2,14 +2,14 @@ CPU 0 interrupt status:
Int Level Type Status Int Level Type Status
0 * * Reserved 0 * * Reserved
1 * * Reserved 1 * * Reserved
2 2 Level Used: RTC_CORE 2 1 Level Used: RTC_CORE
3 2 Level Used: SYSTIMER_TARGET2_EDGE 3 1 Level Used: SYSTIMER_TARGET2_EDGE
4 2 Level Used: ETS_FROM_CPU_INTR0 4 1 Level Used: ETS_FROM_CPU_INTR0
5 * * Reserved 5 * * Reserved
6 * * Reserved 6 * * Reserved
7 2 Level Used: SYSTIMER_TARGET0_EDGE 7 1 Level Used: SYSTIMER_TARGET0_EDGE
8 * * Reserved 8 * * Reserved
9 2 Level Used: UART 9 1 Level Used: UART
10 * * Free 10 * * Free
11 * * Free 11 * * Free
12 * * Free 12 * * Free

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@@ -2,15 +2,15 @@ CPU 0 interrupt status:
Int Level Type Status Int Level Type Status
0 * * Reserved 0 * * Reserved
1 * * Reserved 1 * * Reserved
2 2 Level Used: RTC_CORE 2 1 Level Used: RTC_CORE
3 2 Level Used: SYSTIMER_TARGET2_EDGE 3 1 Level Used: SYSTIMER_TARGET2_EDGE
4 2 Level Used: FROM_CPU_INTR0 4 1 Level Used: FROM_CPU_INTR0
5 * * Reserved 5 * * Reserved
6 * * Reserved 6 * * Reserved
7 2 Level Used: SYSTIMER_TARGET0_EDGE 7 1 Level Used: SYSTIMER_TARGET0_EDGE
8 * * Reserved 8 * * Reserved
9 2 Level Used: TG0_WDT_LEVEL 9 1 Level Used: TG0_WDT_LEVEL
10 2 Level Used: UART0 10 1 Level Used: UART0
11 * * Free 11 * * Free
12 * * Free 12 * * Free
13 * * Free 13 * * Free

View File

@@ -2,18 +2,18 @@ CPU 0 interrupt status:
Int Level Type Status Int Level Type Status
0 * * Reserved 0 * * Reserved
1 * * Reserved 1 * * Reserved
2 2 Level Used: LP_RTC_TIMER 2 1 Level Used: LP_RTC_TIMER
3 * * Reserved 3 * * Reserved
4 * * Reserved 4 * * Reserved
5 * * Reserved 5 * * Reserved
6 * * Reserved 6 * * Reserved
7 * * Reserved 7 * * Reserved
8 * * Reserved 8 * * Reserved
9 2 Level Used: SYSTIMER_TARGET2 9 1 Level Used: SYSTIMER_TARGET2
10 2 Level Used: CPU_FROM_CPU_0 10 1 Level Used: CPU_FROM_CPU_0
11 2 Level Used: SYSTIMER_TARGET0 11 1 Level Used: SYSTIMER_TARGET0
12 2 Level Used: TG0_WDT 12 1 Level Used: TG0_WDT
13 2 Level Used: UART0 13 1 Level Used: UART0
14 * * Free 14 * * Free
15 * * Free 15 * * Free
16 * * Free 16 * * Free

View File

@@ -2,18 +2,18 @@ CPU 0 interrupt status:
Int Level Type Status Int Level Type Status
0 * * Reserved 0 * * Reserved
1 * * Reserved 1 * * Reserved
2 2 Level Used: LP_RTC_TIMER 2 1 Level Used: LP_RTC_TIMER
3 * * Reserved 3 * * Reserved
4 * * Reserved 4 * * Reserved
5 * * Reserved 5 * * Reserved
6 * * Reserved 6 * * Reserved
7 * * Reserved 7 * * Reserved
8 * * Reserved 8 * * Reserved
9 2 Level Used: SYSTIMER_TARGET2 9 1 Level Used: SYSTIMER_TARGET2
10 2 Level Used: CPUFROM_CPU_0 10 1 Level Used: CPUFROM_CPU_0
11 2 Level Used: SYSTIMER_TARGET0 11 1 Level Used: SYSTIMER_TARGET0
12 2 Level Used: TG0_WDT 12 1 Level Used: TG0_WDT
13 2 Level Used: UART0 13 1 Level Used: UART0
14 * * Free 14 * * Free
15 * * Free 15 * * Free
16 * * Free 16 * * Free