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change(hal): update lp_timer register structure and support driver for esp32h21

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This commit is contained in:
Li Shuai
2025-03-04 22:39:52 +08:00
committed by BOT
parent ac5c5de378
commit 1da425bdc7
2 changed files with 140 additions and 231 deletions
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62
components/hal/esp32h21/include/hal/lp_timer_ll.h Normal file
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@@ -0,0 +1,62 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H2 LP_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_aon_reg.h"
#include "hal/lp_timer_types.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.alarm = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow = 1;
}
#ifdef __cplusplus
}
#endif

309
components/soc/esp32h21/register/soc/lp_timer_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,247 +10,94 @@
extern "C" {
#endif
/** Group: configure_register */
/** Type of timer_tar0_low register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_tar_low0:32;
};
uint32_t val;
} lp_timer_tar0_low_reg_t;
typedef struct {
union {
struct {
uint32_t target_lo: 32;
};
uint32_t val;
} lo;
union {
struct {
uint32_t target_hi: 16;
uint32_t reserved0: 15;
uint32_t enable : 1;
};
uint32_t val;
} hi;
} lp_timer_target_reg_t;
/** Type of timer_tar0_high register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_tar_high0:16;
uint32_t reserved_16:15;
/** timer_main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_main_timer_tar_en0:1;
};
uint32_t val;
} lp_timer_tar0_high_reg_t;
/** Type of timer_update register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** timer_main_timer_update : WT; bitpos: [27]; default: 0;
* need_des
*/
uint32_t timer_main_timer_update:1;
/** timer_main_timer_regdma_work : R/W; bitpos: [28]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when regdma working
*/
uint32_t timer_main_timer_regdma_work:1;
/** timer_main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t timer_main_timer_xtal_off:1;
/** timer_main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_main_timer_sys_stall:1;
/** timer_main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_main_timer_sys_rst:1;
uint32_t reserved0: 27;
uint32_t update : 1;
uint32_t regdma_work: 1;
uint32_t xtal_off : 1;
uint32_t sys_stall: 1;
uint32_t sys_rst : 1;
};
uint32_t val;
} lp_timer_update_reg_t;
/** Type of timer_main_buf0_low register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_buf0_low:32;
};
uint32_t val;
} lp_timer_main_buf0_low_reg_t;
/** Type of timer_main_buf0_high register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_buf0_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf0_high_reg_t;
/** Type of timer_main_buf1_low register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_buf1_low:32;
};
uint32_t val;
} lp_timer_main_buf1_low_reg_t;
/** Type of timer_main_buf1_high register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_buf1_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf1_high_reg_t;
/** Type of timer_main_overflow register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** timer_main_timer_alarm_load : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_main_timer_alarm_load:1;
};
uint32_t val;
} lp_timer_main_overflow_reg_t;
/** Type of timer_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_overflow_raw:1;
/** timer_soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_soc_wakeup_int_raw:1;
};
uint32_t val;
} lp_timer_int_raw_reg_t;
/** Type of timer_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_overflow_st:1;
/** timer_soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_soc_wakeup_int_st:1;
};
uint32_t val;
} lp_timer_int_st_reg_t;
/** Type of timer_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_overflow_ena:1;
/** timer_soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_soc_wakeup_int_ena:1;
};
uint32_t val;
} lp_timer_int_ena_reg_t;
/** Type of timer_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_overflow_clr:1;
/** timer_soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_soc_wakeup_int_clr:1;
};
uint32_t val;
} lp_timer_int_clr_reg_t;
/** Type of timer_date register
* need_des
*/
typedef union {
struct {
/** timer_date : R/W; bitpos: [30:0]; default: 37785904;
* need_des
*/
uint32_t timer_date:31;
/** timer_clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_clk_en:1;
};
uint32_t val;
} lp_timer_date_reg_t;
typedef struct {
volatile lp_timer_tar0_low_reg_t timer_tar0_low;
volatile lp_timer_tar0_high_reg_t timer_tar0_high;
uint32_t reserved_008[2];
volatile lp_timer_update_reg_t timer_update;
volatile lp_timer_main_buf0_low_reg_t timer_main_buf0_low;
volatile lp_timer_main_buf0_high_reg_t timer_main_buf0_high;
volatile lp_timer_main_buf1_low_reg_t timer_main_buf1_low;
volatile lp_timer_main_buf1_high_reg_t timer_main_buf1_high;
volatile lp_timer_main_overflow_reg_t timer_main_overflow;
volatile lp_timer_int_raw_reg_t timer_int_raw;
volatile lp_timer_int_st_reg_t timer_int_st;
volatile lp_timer_int_ena_reg_t timer_int_ena;
volatile lp_timer_int_clr_reg_t timer_int_clr;
uint32_t reserved_038[241];
volatile lp_timer_date_reg_t timer_date;
} lp_dev_t;
union {
struct {
uint32_t counter_lo: 32;
};
uint32_t val;
} lo;
union {
struct {
uint32_t counter_hi: 16;
uint32_t reserved0 : 16;
};
uint32_t val;
} hi;
} lp_timer_counter_reg_t;
typedef union {
struct {
uint32_t reserved0: 31;
uint32_t trigger : 1;
};
uint32_t val;
} lp_timer_overflow_reg_t;
typedef union {
struct {
uint32_t reserved0: 30;
uint32_t overflow : 1;
uint32_t alarm : 1;
};
uint32_t val;
} lp_timer_intr_reg_t;
typedef union {
struct {
uint32_t date : 31;
uint32_t clk_en: 1;
};
uint32_t val;
} lp_timer_date_clken_reg_t;
typedef struct lp_timer_dev_t{
volatile lp_timer_target_reg_t target[1];
uint32_t reserved0[2];
volatile lp_timer_update_reg_t update;
volatile lp_timer_counter_reg_t counter[2];
volatile lp_timer_overflow_reg_t overflow;
volatile lp_timer_intr_reg_t int_raw;
volatile lp_timer_intr_reg_t int_st;
volatile lp_timer_intr_reg_t int_en;
volatile lp_timer_intr_reg_t int_clr;
uint32_t reserved[241];
volatile lp_timer_date_clken_reg_t date_clken;
} lp_timer_dev_t;
extern lp_timer_dev_t LP_TIMER;
#ifndef __cplusplus
_Static_assert(sizeof(lp_dev_t) == 0x400, "Invalid size of lp_dev_t structure");
_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
#endif
#ifdef __cplusplus