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change(gpio): esp32p4 available pins are GPIO0 ~ GPIO54

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This commit is contained in:
Song Ruo Jing
2023-12-19 22:31:14 +08:00
parent 88cc473910
commit 20f6505aa6
12 changed files with 34 additions and 68 deletions
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24
components/esp_rom/include/esp32p4/rom/gpio.h
View File

@@ -85,7 +85,7 @@ void gpio_init(void);
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Change GPIO(32-56) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
* @brief Change GPIO(32-54) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
@@ -111,7 +111,7 @@ void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enabl
uint32_t gpio_input_get(void);
/**
* @brief Sample the value of GPIO input pins(32-56) and returns a bitmask.
* @brief Sample the value of GPIO input pins(32-54) and returns a bitmask.
*
* @param None
*
@@ -197,7 +197,7 @@ void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~56
* @param uint32_t gpio : gpio number, 0~54
* gpio == 0x3E, input 0 to signal
* gpio == 0x3F, input 1 to signal
*
@@ -212,7 +212,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~56
* @param uint32_t gpio : gpio number, 0~54
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x100, cancel output put to the gpio
@@ -228,7 +228,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~56
* @param uint32_t gpio_num : gpio number, 0~54
*
* @return None
*/
@@ -237,7 +237,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~56
* @param uint32_t gpio_num : gpio number, 0~54
*
* @param uint32_t drv : 0-3
*
@@ -248,7 +248,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~56
* @param uint32_t gpio_num : gpio number, 0~54
*
* @return None
*/
@@ -257,7 +257,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~56
* @param uint32_t gpio_num : gpio number, 0~54
*
* @return None
*/
@@ -266,7 +266,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~56
* @param uint32_t gpio_num : gpio number, 0~54
*
* @return None
*/
@@ -275,7 +275,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~56
* @param uint32_t gpio_num : gpio number, 0~54
*
* @return None
*/
@@ -284,7 +284,7 @@ void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~56
* @param uint32_t gpio_num : gpio number, 0~54
*
* @return None
*/
@@ -293,7 +293,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~56
* @param uint32_t gpio_num : gpio number, 0~54
*
* @return None
*/

16
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@@ -39,9 +39,9 @@ extern "C" {
#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
#define GPIO_LL_INTR0_ENA (BIT(0))
// #define GPIO_LL_INTR1_ENA (BIT(1)) // TODO: IDF-7995
// #define GPIO_LL_INTR2_ENA (BIT(2))
// #define GPIO_LL_INTR3_ENA (BIT(3))
#define GPIO_LL_INTR1_ENA (BIT(1))
#define GPIO_LL_INTR2_ENA (BIT(3))
#define GPIO_LL_INTR3_ENA (BIT(4))
/**
* @brief Get the configuration for an IO
@@ -289,7 +289,7 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
// GPIO 16-47
HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low |= (bit_mask >> SOC_RTCIO_PIN_COUNT);
} else {
// GPIO 48-56
// GPIO 48-54
HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
@@ -312,7 +312,7 @@ static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t
// GPIO 16-47
HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low &= ~(bit_mask >> SOC_RTCIO_PIN_COUNT);
} else {
// GPIO 48-56
// GPIO 48-54
HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
@@ -486,7 +486,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
// GPIO 16-47
HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low |= (bit_mask >> SOC_RTCIO_PIN_COUNT);
} else {
// GPIO 48-56
// GPIO 48-54
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
@@ -511,7 +511,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
// GPIO 16-47
HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low &= ~(bit_mask >> SOC_RTCIO_PIN_COUNT);
} else {
// GPIO 48-56
// GPIO 48-54
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
@@ -541,7 +541,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
// GPIO 16-47
return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> SOC_RTCIO_PIN_COUNT));
} else {
// GPIO 48-56
// GPIO 48-54
return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)));
}
}

2
components/hal/include/hal/gpio_types.h
View File

@@ -74,8 +74,6 @@ typedef enum {
#define GPIO_PIN_REG_52 IO_MUX_GPIO52_REG
#define GPIO_PIN_REG_53 IO_MUX_GPIO53_REG
#define GPIO_PIN_REG_54 IO_MUX_GPIO54_REG
#define GPIO_PIN_REG_55 IO_MUX_GPIO55_REG
#define GPIO_PIN_REG_56 IO_MUX_GPIO56_REG
typedef enum {
GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */

4
components/soc/esp32p4/gpio_periph.c
View File

@@ -63,8 +63,6 @@ const uint32_t GPIO_PIN_MUX_REG[] = {
IO_MUX_GPIO52_REG,
IO_MUX_GPIO53_REG,
IO_MUX_GPIO54_REG,
IO_MUX_GPIO55_REG,
IO_MUX_GPIO56_REG,
};
ESP_STATIC_ASSERT(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
@@ -125,8 +123,6 @@ const uint32_t GPIO_HOLD_MASK[] = {
BIT(4), //GPIO52
BIT(5), //GPIO53
BIT(6), //GPIO54
BIT(7), //GPIO55
BIT(8), //GPIO56
};
ESP_STATIC_ASSERT(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

10
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -401,7 +401,7 @@ config SOC_GPIO_PORT
config SOC_GPIO_PIN_COUNT
int
default 57
default 55
config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
@@ -429,15 +429,15 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x01FFFFFFFFFFFFFF
default 0x007FFFFFFFFFFFFF
config SOC_GPIO_IN_RANGE_MAX
int
default 56
default 54
config SOC_GPIO_OUT_RANGE_MAX
int
default 56
default 54
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
@@ -445,7 +445,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x01FFFFFFFFFF0000
default 0x007FFFFFFFFF0000
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool

2
components/soc/esp32p4/include/soc/gpio_num.h
View File

@@ -70,8 +70,6 @@ typedef enum {
GPIO_NUM_52 = 52, /*!< GPIO52, input and output */
GPIO_NUM_53 = 53, /*!< GPIO53, input and output */
GPIO_NUM_54 = 54, /*!< GPIO54, input and output */
GPIO_NUM_55 = 55, /*!< GPIO55, input and output */
GPIO_NUM_56 = 56, /*!< GPIO56, input and output */
GPIO_NUM_MAX,
} gpio_num_t;

4
components/soc/esp32p4/include/soc/io_mux_reg.h
View File

@@ -146,8 +146,6 @@
#define IO_MUX_GPIO52_REG PERIPHS_IO_MUX_U_PAD_GPIO52
#define IO_MUX_GPIO53_REG PERIPHS_IO_MUX_U_PAD_GPIO53
#define IO_MUX_GPIO54_REG PERIPHS_IO_MUX_U_PAD_GPIO54
#define IO_MUX_GPIO55_REG PERIPHS_IO_MUX_U_PAD_GPIO55
#define IO_MUX_GPIO56_REG PERIPHS_IO_MUX_U_PAD_GPIO56
#define PIN_FUNC_GPIO 1
@@ -225,7 +223,7 @@
// #define EXT_OSC_SLOW_GPIO_NUM 1 // TODO: IDF-7526
#define MAX_RTC_GPIO_NUM 16
#define MAX_PAD_GPIO_NUM 56
#define MAX_PAD_GPIO_NUM 54
#define MAX_GPIO_NUM 56
#define HIGH_IO_HOLD_BIT_SHIFT 32

12
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -184,7 +184,7 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-P4 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 57
#define SOC_GPIO_PIN_COUNT 55
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: IDF-7481
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: IDF-7481
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
@@ -200,16 +200,16 @@
// GPIO0~15 on ESP32P4 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_VALID_GPIO_MASK (0x01FFFFFFFFFFFFFF)
#define SOC_GPIO_VALID_GPIO_MASK (0x007FFFFFFFFFFFFF)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 56
#define SOC_GPIO_OUT_RANGE_MAX 56
#define SOC_GPIO_IN_RANGE_MAX 54
#define SOC_GPIO_OUT_RANGE_MAX 54
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_56)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x01FFFFFFFFFF0000ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)

2
components/soc/esp32p4/rtc_io_periph.c
View File

@@ -62,6 +62,4 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-1,//GPIO52
-1,//GPIO53
-1,//GPIO54
-1,//GPIO55
-1,//GPIO56
};

2
docs/docs_not_updated/esp32p4.txt
View File

@@ -61,7 +61,6 @@ api-reference/storage/mass_mfg.rst
api-reference/storage/fatfsgen.rst
api-reference/storage/index.rst
api-reference/storage/nvs_partition_parse.rst
api-reference/peripherals/gpio/esp32p4.inc
api-reference/peripherals/adc_continuous.rst
api-reference/peripherals/adc_oneshot.rst
api-reference/peripherals/usb_host.rst
@@ -70,7 +69,6 @@ api-reference/peripherals/usb_host/usb_host_notes_index.rst
api-reference/peripherals/usb_host/usb_host_notes_dwc_otg.rst
api-reference/peripherals/usb_host/usb_host_notes_design.rst
api-reference/peripherals/usb_device.rst
api-reference/peripherals/gpio.rst
api-reference/peripherals/dac.rst
api-reference/peripherals/touch_element.rst
api-reference/peripherals/lcd.rst

12
docs/en/api-reference/peripherals/gpio/esp32p4.inc
View File

@@ -9,7 +9,7 @@
.. gpio-summary
The {IDF_TARGET_NAME} chip features 57 physical GPIO pins (GPIO0 ~ GPIO56). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The {IDF_TARGET_NAME} chip features 55 physical GPIO pins (GPIO0 ~ GPIO54). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
@@ -297,16 +297,6 @@ The table below provides more information on pin usage, and please note the comm
-
-
* - GPIO55
-
-
-
* - GPIO56
-
-
-
.. note::
- Strapping pin: GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 are strapping pins. For more infomation, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.

12
docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc
View File

@@ -9,7 +9,7 @@
.. gpio-summary
{IDF_TARGET_NAME} 芯片具有 57 个物理 GPIO 管脚（GPIO0 ~ GPIO56）。
{IDF_TARGET_NAME} 芯片具有 55 个物理 GPIO 管脚（GPIO0 ~ GPIO54）。
每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
@@ -299,16 +299,6 @@
-
-
* - GPIO55
-
-
-
* - GPIO56
-
-
-
.. note::
- Strapping 管脚：GPIO34, GPIO35、GPIO36、GPIO37 和 GPIO38 是 Strapping 管脚。更多信息请参考 `ESP32-P4 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。