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Merge remote-tracking branch 'origin/master' into feature/openssl

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This commit is contained in:
Wu Jian Gang
2016-10-13 17:14:40 +08:00
parent 5d60a1153d bdd67c98d6
commit 216b831646
247 changed files with 66071 additions and 2244 deletions
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10
.gitignore vendored
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@@ -7,8 +7,18 @@ GTAGS
GRTAGS
GPATH
# emacs
.dir-locals.el
# emacs temp file suffixes
*~
.#*
\#*#
# Example project files
examples/*/sdkconfig
examples/*/sdkconfig.old
examples/*/build
# Bootloader files
components/bootloader/src/sdkconfig.old

319
.gitlab-ci.yml
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@@ -7,7 +7,7 @@ before_script:
# add gitlab ssh key
- mkdir -p ~/.ssh
- chmod 700 ~/.ssh
- echo -n $GITLAB_KEY >> ~/.ssh/id_rsa_base64
- echo -n $GITLAB_KEY > ~/.ssh/id_rsa_base64
- base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa
- chmod 600 ~/.ssh/id_rsa
- echo -e "Host gitlab.espressif.cn\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
@@ -62,12 +62,30 @@ build_ssc:
expire_in: 6 mos
script:
- git clone ssh://git@gitlab.espressif.cn:27227/yinling/SSC.git
- git clone $GITLAB_SSH_SERVER/yinling/SSC.git
- cd SSC
- git checkout ${CI_BUILD_REF_NAME} || echo "Using SSC default branch..."
- make defconfig
- chmod +x gen_misc_ng.sh
- ./gen_misc_ng.sh
build_examples:
<<: *build_template
artifacts:
paths:
- build_examples/*/*/build/*.bin
- build_examples/*/*/build/*.elf
- build_examples/*/*/build/*.map
- build_examples/*/*/build/bootloader/*.bin
expire_in: 6 mos
script:
# it's not possible to build 100% out-of-tree and have the "artifacts"
# mechanism work, but this is the next best thing
- mkdir build_examples
- cd build_examples
- ${IDF_PATH}/make/build_examples.sh
test_nvs_on_host:
stage: test
image: espressif/esp32-ci-env
@@ -87,46 +105,34 @@ test_build_system:
script:
- ./make/test_build_system.sh
# template for test jobs
.test_template: &test_template
stage: test
when: on_success
test_report:
stage: deploy
only:
- master
- triggers
tags:
- test_report
allow_failure: true
variables:
# need user to set SDK_NAME and CONFIG_FILE (may need to set BIN_PATH and APP_NAME later) in before_script
SCRIPT_PATH: /home/gitlab-runner/auto_test_script
BIN_PATH: ${CI_PROJECT_DIR}/SSC/build/
APP_NAME: ssc
LOG_PATH: $CI_PROJECT_DIR/$CI_BUILD_REF
LOG_PATH: "$CI_PROJECT_DIR/$CI_BUILD_REF"
TEST_CASE_FILE_PATH: "$CI_PROJECT_DIR/components/idf_test"
REPORT_PATH: "$CI_PROJECT_DIR/CI_Test_Report"
artifacts:
when: always
paths:
- $LOG_PATH
- $REPORT_PATH
expire_in: 6 mos
script:
- cd $SCRIPT_PATH
- python CIRunner.py -l $LOG_PATH -c $SDK_NAME/$CONFIG_FILE bin_path $APP_NAME $BIN_PATH
sanity_test:
<<: *test_template
tags:
- ESP32
- SSC_T1_1
- SSC_T2_1
- SSC_T1_WAN
before_script:
- SDK_NAME=ESP32_IDF
- CONFIG_FILE=sanity_test.yml
# clone test bench
- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
- cd auto_test_script
# generate report
- python CITestReport.py -l $LOG_PATH -t $TEST_CASE_FILE_PATH -p $REPORT_PATH
push_master_to_github:
before_script:
- echo "Not setting up GitLab key, not fetching submodules"
stage: deploy
only:
- master
@@ -139,9 +145,256 @@ push_master_to_github:
script:
- mkdir -p ~/.ssh
- chmod 700 ~/.ssh
- echo -n $GH_PUSH_KEY >> ~/.ssh/id_rsa_base64
- echo -n $GH_PUSH_KEY > ~/.ssh/id_rsa_base64
- base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa
- chmod 600 ~/.ssh/id_rsa
- echo -e "Host github.com\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
- git remote add github git@github.com:espressif/esp-idf.git
- git push github HEAD:master
- git push --follow-tags github HEAD:master
# AUTO GENERATED PART START, DO NOT MODIFY CONTENT BELOW
# template for test jobs
.test_template: &test_template
stage: test
when: on_success
only:
- master
- triggers
allow_failure: true
variables:
# LOCAL_ENV_CONFIG_PATH: define in template and jobs can overwrite if required
LOCAL_ENV_CONFIG_PATH: /home/gitlab-runner/LocalConfig/ESP32_IDF
BIN_PATH: "$CI_PROJECT_DIR/SSC/build/"
APP_NAME: "ssc"
LOG_PATH: "$CI_PROJECT_DIR/$CI_BUILD_REF"
# append test level folder to TEST_CASE_FILE_PATH in before_script of test job
TEST_CASE_FILE_PATH: "$CI_PROJECT_DIR/components/idf_test"
# jobs MUST set CONFIG_FILE in before_script, and overwrite the variables above if necessary
artifacts:
when: always
paths:
- $LOG_PATH
expire_in: 6 mos
script:
# add gitlab ssh key
- mkdir -p ~/.ssh
- chmod 700 ~/.ssh
- echo -n $GITLAB_KEY > ~/.ssh/id_rsa_base64
- base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa
- chmod 600 ~/.ssh/id_rsa
- echo -e "Host gitlab.espressif.cn\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
# clone test bench
- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
- cd auto_test_script
# run test
- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH bin_path $APP_NAME $BIN_PATH
# template for overnight test jobs
.test_template_night: &test_template_night
<<: *test_template
only:
# can only be triggered
- triggers
script:
# must be night build triggers, otherwise exit without test
- test $NIGHT_BUILD = "Yes" || exit 0
# add gitlab ssh key
- mkdir -p ~/.ssh
- chmod 700 ~/.ssh
- echo -n $GITLAB_KEY > ~/.ssh/id_rsa_base64
- base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa
- chmod 600 ~/.ssh/id_rsa
- echo -e "Host gitlab.espressif.cn\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
# clone test bench
- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
- cd auto_test_script
# run test
- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH bin_path $APP_NAME $BIN_PATH
IT_Function_SYS_01:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_SYS_01.yml
IT_Function_WIFI_01:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_01.yml
IT_Function_WIFI_02:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_02.yml
IT_Function_TCPIP_01:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_01.yml
IT_Function_TCPIP_02:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_02.yml
IT_Function_TCPIP_03:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_03.yml
IT_Function_TCPIP_04:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_04.yml
IT_Function_TCPIP_05:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_05.yml
IT_Function_TCPIP_06:
<<: *test_template_night
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_06.yml
IT_Function_WIFI_03:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T3_PhyMode
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_03.yml
IT_Function_WIFI_04:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_APC
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_04.yml
IT_Function_WIFI_05:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_WEP
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_05.yml
IT_Function_WIFI_06:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T2_PhyMode
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_WIFI_06.yml
IT_Function_TCPIP_07:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T1_2
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_07.yml
IT_Function_TCPIP_08:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_08.yml
IT_Function_TCPIP_09:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_09.yml
IT_Function_TCPIP_10:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T1_2
- SSC_T2_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_10.yml
IT_Function_TCPIP_11:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_11.yml
IT_Function_TCPIP_12:
<<: *test_template
tags:
- ESP32_IDF
- SSC_T1_1
- SSC_T1_2
before_script:
- TEST_CASE_FILE_PATH=$TEST_CASE_FILE_PATH/integration_test
- CONFIG_FILE=$TEST_CASE_FILE_PATH/CIConfigs/IT_Function_TCPIP_12.yml

3
.gitmodules vendored
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@@ -4,3 +4,6 @@
[submodule "components/esptool_py/esptool"]
path = components/esptool_py/esptool
url = https://github.com/themadinventor/esptool.git
[submodule "components/bt/lib"]
path = components/bt/lib
url = https://github.com/espressif/esp32-bt-lib.git

37
CONTRIBUTING.md Normal file
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@@ -0,0 +1,37 @@
# Contributions Guide
We welcome contributions to the esp-idf project!
## How to Contribute
Contributions to esp-idf - fixing bugs, adding features, adding documentation - are welcome. We accept contributions via [Github Pull Requests](https://help.github.com/articles/about-pull-requests/).
## Before Contributing
Before sending us a Pull Request, please consider this list of points:
* Is the contribution entirely your own work, or already licensed under an Apache License 2.0 compatible Open Source License? If not then we unfortunately cannot accept it.
* Does any new code conform to the esp-idf Style Guide? (Style Guide currently pending).
* Is the code adequately commented for people to understand how it is structured?
* Is there documentation or examples that go with code contributions? [There are additional suggestions for writing good examples in the examples README](examples/README.md).
* Are comments and documentation written in clear English, with no spelling or grammar errors?
* If the contribution contains multiple commits, are they grouped together into logical changes (one major change per pull request)? Are any commits with names like "fixed typo" [squashed into previous commits](http://eli.thegreenplace.net/2014/02/19/squashing-github-pull-requests-into-a-single-commit/)?
* If you're unsure about any of these points, please open the Pull Request anyhow and then ask us for feedback.
## Pull Request Process
After you open the Pull Request, there will probably be some discussion in the comments field of the request itself.
Once the Pull Request is ready to merge, it will first be merged into our internal git system for in-house automated testing.
If this process passes, it will be merged onto the public github repository.
## Legal Part
Before a contribution can be accepted, you will need to sign our [Contributor Agreement](docs/contributor-agreement.rst). You will be prompted for this automatically as part of the Pull Request process.

50
Kconfig
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@@ -7,50 +7,18 @@ mainmenu "Espressif IoT Development Framework Configuration"
menu "SDK tool configuration"
config TOOLPREFIX
string "Compiler toolchain path/prefix"
default "xtensa-esp32-elf-"
help
The prefix/path that is used to call the toolchain. The default setting assumes
a crosstool-ng gcc setup that is in your PATH.
string "Compiler toolchain path/prefix"
default "xtensa-esp32-elf-"
help
The prefix/path that is used to call the toolchain. The default setting assumes
a crosstool-ng gcc setup that is in your PATH.
config PYTHON
string "Python 2 interpreter"
default "python"
help
The executable name/path that is used to run python. On some systems Python 2.x
may need to be invoked as python2.
config MEMMAP_BT
bool "Reserve space for Bluetooth stack"
default "n"
help
The Bluetooth stack uses memory that cannot be used as generic memory anymore. This
reserves the space for that within the memory map of the compiled binary.
config MEMMAP_SMP
bool "Reserve memory for two cores"
default "y"
help
The ESP32 contains two cores. If you plan to only use one, you can disable this item
to save some memory. (ToDo: Make this automatically depend on unicore support)
config MEMMAP_TRACEMEM
bool "Use TRAX tracing feature"
default "n"
help
The ESP32 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
config MEMMAP_SPISRAM
bool "Use external SPI SRAM chip as main memory"
default "n"
help
The ESP32 can control an external SPI SRAM chip, adding the memory it contains to the
main memory map. Enable this if you have this hardware and want to use it in the same
way as on-chip RAM.
default "python"
help
The executable name/path that is used to run python. On some systems Python 2.x
may need to be invoked as python2.
endmenu
source "$COMPONENT_KCONFIGS_PROJBUILD"

18
README.md
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@@ -1,6 +1,18 @@
# Using Espressif IoT Development Framework with the ESP32
# Prerequisites
# Setting Up ESP-IDF
In the [docs](docs) directory you will find per-platform setup guides:
* [Windows Setup Guide](docs/windows-setup.rst)
* [Mac OS Setup Guide](docs/macos-setup.rst)
* [Linux Setup Guide](docs/linux-setup.rst)
# Finding A Project
As well as the [esp-idf-template](https://github.com/espressif/esp-idf-template) project mentioned in the setup guide, esp-idf comes with some example projects in the [examples](examples) directory.
Once you've found the project you want to work with, change to its directory and you can configure and build it:
# Configuring your project
@@ -52,8 +64,10 @@ For more details about partition tables and how to create custom variations, vie
# Resources
* The [docs directory of the esp-idf repository](https://github.com/espressif/esp-idf/tree/master/docs) contains esp-idf documentation.
* The [docs directory of the esp-idf repository](docs) contains esp-idf documentation.
* The [esp32.com forum](http://esp32.com/) is a place to ask questions and find community resources.
* [Check the Issues section on github](https://github.com/espressif/esp-idf/issues) if you find a bug or have a feature request. Please check existing Issues before opening a new one.
* If you're interested in contributing to esp-idf, please check the [CONTRIBUTING.md](CONTRIBUTING.md) file.

38
components/bootloader/Kconfig.projbuild
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@@ -1,33 +1,31 @@
menu "Bootloader config"
choice BOOTLOADER_LOG_LEVEL
choice LOG_BOOTLOADER_LEVEL
bool "Bootloader log verbosity"
default BOOTLOADER_LOG_LEVEL_NOTICE
default LOG_BOOTLOADER_LEVEL_WARN
help
Specify how much output to see in the bootloader logs.
Specify how much output to see in bootloader logs.
Note that if MTDO is HIGH on reset, all early boot output
(including bootloader logs) are suppressed.
config BOOTLOADER_LOG_LEVEL_NONE
config LOG_BOOTLOADER_LEVEL_NONE
bool "No output"
config BOOTLOADER_LOG_LEVEL_ERROR
config LOG_BOOTLOADER_LEVEL_ERROR
bool "Error"
config BOOTLOADER_LOG_LEVEL_WARN
config LOG_BOOTLOADER_LEVEL_WARN
bool "Warning"
config BOOTLOADER_LOG_LEVEL_INFO
config LOG_BOOTLOADER_LEVEL_INFO
bool "Info"
config BOOTLOADER_LOG_LEVEL_NOTICE
bool "Notice"
config BOOTLOADER_LOG_LEVEL_DEBUG
config LOG_BOOTLOADER_LEVEL_DEBUG
bool "Debug"
config LOG_BOOTLOADER_LEVEL_VERBOSE
bool "Verbose"
endchoice
config BOOTLOADER_LOG_COLORS
bool "Use ANSI terminal colors in bootloader log output"
default "y"
help
Enable ANSI terminal color codes in bootloader output.
In order to view these, your terminal program must support ANSI color codes.
config LOG_BOOTLOADER_LEVEL
int
default 0 if LOG_BOOTLOADER_LEVEL_NONE
default 1 if LOG_BOOTLOADER_LEVEL_ERROR
default 2 if LOG_BOOTLOADER_LEVEL_WARN
default 3 if LOG_BOOTLOADER_LEVEL_INFO
default 4 if LOG_BOOTLOADER_LEVEL_DEBUG
default 5 if LOG_BOOTLOADER_LEVEL_VERBOSE
endmenu

3
components/bootloader/Makefile.projbuild
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@@ -45,4 +45,7 @@ $(COMPONENT_PATH)/src/sdkconfig: $(PROJECT_PATH)/sdkconfig
bootloader-flash: $(BOOTLOADER_BIN)
$(MAKE) -C $(BOOTLOADER_COMPONENT_PATH)/src flash MAKEFLAGS= V=$(V)
else
CFLAGS += -D BOOTLOADER_BUILD=1 -I $(IDF_PATH)/components/esp32/include
endif

6
components/bootloader/src/Makefile
View File

@@ -4,14 +4,14 @@
#
PROJECT_NAME := bootloader
COMPONENTS := esptool_py bootloader
COMPONENTS := esptool_py bootloader log
# The bootloader pseudo-component is also included in this build, for its Kconfig.projbuild to be included.
#
# IS_BOOTLOADER_BUILD tells the component Makefile.projbuild to be a no-op
IS_BOOTLOADER_BUILD := 1
#We cannot include the esp32 component directly but we need its includes. This is fixed by
#adding it in the main/Makefile directory.
#We cannot include the esp32 component directly but we need its includes.
#This is fixed by adding CFLAGS from Makefile.projbuild
include $(IDF_PATH)/make/project.mk

4
components/bootloader/src/main/bootloader_config.h
View File

@@ -30,6 +30,10 @@ extern "C"
#define IROM_HIGH 0x40400000
#define DROM_LOW 0x3F400000
#define DROM_HIGH 0x3F800000
#define RTC_IRAM_LOW 0x400C0000
#define RTC_IRAM_HIGH 0x400C2000
#define RTC_DATA_LOW 0x50000000
#define RTC_DATA_HIGH 0x50002000
/*spi mode,saved in third byte in flash */
enum {

114
components/bootloader/src/main/bootloader_log.h
View File

@@ -1,114 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __BOOT_LOG_H__
#define __BOOT_LOG_H__
#ifdef __cplusplus
extern "C"
{
#endif
#include "sdkconfig.h"
#define BOOT_LOG_LEVEL_NONE (0)
#define BOOT_LOG_LEVEL_ERROR (1)
#define BOOT_LOG_LEVEL_WARN (2)
#define BOOT_LOG_LEVEL_INFO (3)
#define BOOT_LOG_LEVEL_NOTICE (4)
#define BOOT_LOG_LEVEL_DEBUG (5)
#define Black "30"
#define Red "31"
#define Green "32"
#define Brown "33"
#define Blue "34"
#define Purple "35"
#define Cyan "36"
#if CONFIG_BOOTLOADER_LOG_COLORS
#define LOG_COLOR(COLOR) "\033[0;"COLOR"m"
#define LOG_BOLD(COLOR) "\033[1;"COLOR"m"
#define LOG_RESET_COLOR "\033[0m"
#else
#define LOG_COLOR(...)
#define LOG_BOLD(...)
#define LOG_RESET_COLOR ""
#endif
// BOOT_LOG_LEVEL defined by make menuconfig
#if CONFIG_BOOTLOADER_LOG_LEVEL_NONE
#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_NONE
#elif CONFIG_BOOTLOADER_LOG_LEVEL_ERROR
#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_ERROR
#elif CONFIG_BOOTLOADER_LOG_LEVEL_WARN
#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_WARN
#elif CONFIG_BOOTLOADER_LOG_LEVEL_INFO
#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_INFO
#elif CONFIG_BOOTLOADER_LOG_LEVEL_NOTICE
#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_NOTICE
#elif CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG
#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_DEBUG
#else
#error "No bootloader log level set in menuconfig!"
#endif
//printf("\033[0;36m[NOTICE][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);
#define log_notice(format, ...) \
do{\
if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_NOTICE){\
ets_printf(LOG_COLOR(Cyan) format "\r\n", ##__VA_ARGS__); \
ets_printf(LOG_RESET_COLOR); \
}\
}while(0)
#define log_info(format, ...) \
do{\
if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_INFO){\
ets_printf(LOG_BOLD(Cyan) format "\r\n", ##__VA_ARGS__); \
ets_printf(LOG_RESET_COLOR); \
}\
}while(0)
//printf("\033[0;31m[ERROR][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);
#define log_error(format, ...) \
do{\
if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_ERROR){\
ets_printf(LOG_COLOR(Red) "[ERROR][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
ets_printf(LOG_RESET_COLOR); \
}\
}while(0)
//printf("\033[1;33m[WARN][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);
#define log_warn(format, ...) \
do{\
if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_WARN){\
ets_printf(LOG_BOLD(Brown) "[WARN][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
ets_printf(LOG_RESET_COLOR); \
}\
}while(0)
//printf("\033[1;32m[DEBUG][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);
#define log_debug(format, ...) \
do{\
if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_DEBUG){\
ets_printf(LOG_BOLD(Green) "[DEBUG][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
ets_printf(LOG_RESET_COLOR); \
}\
}while(0)
#ifdef __cplusplus
}
#endif
#endif /* __BOOT_LOGGING_H__ */

147
components/bootloader/src/main/bootloader_start.c
View File

@@ -16,13 +16,16 @@
#include <limits.h>
#include "esp_attr.h"
#include "esp_log.h"
#include "rom/cache.h"
#include "rom/ets_sys.h"
#include "rom/spi_flash.h"
#include "rom/crc.h"
#include "rom/rtc.h"
#include "soc/soc.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/efuse_reg.h"
@@ -31,11 +34,12 @@
#include "sdkconfig.h"
#include "bootloader_log.h"
#include "bootloader_config.h"
extern int _bss_start;
extern int _bss_end;
static const char* TAG = "boot";
/*
We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
@@ -58,36 +62,7 @@ void IRAM_ATTR set_cache_and_start_app(uint32_t drom_addr,
void IRAM_ATTR call_start_cpu0()
{
//Make page 0 access raise an exception
//Also some other unused pages so we can catch weirdness
//ToDo: this but nicer.
asm volatile (\
"movi a4,0x00000000\n" \
"movi a5,0xf\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x80000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xa0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xc0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xe0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x20000000\n" \
"movi a5,0x0\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x40000000\n" \
"movi a5,0x2\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"isync\n" \
:::"a4","a5");
cpu_configure_region_protection();
//Clear bss
memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
@@ -130,7 +105,7 @@ uint32_t get_bin_len(uint32_t pos)
{
uint32_t len = 8 + 16;
uint8_t i;
log_debug("pos %d %x\n",pos,*(uint8_t *)pos);
ESP_LOGD(TAG, "pos %d %x",pos,*(uint8_t *)pos);
if(0xE9 != *(uint8_t *)pos) {
return 0;
}
@@ -142,7 +117,7 @@ uint32_t get_bin_len(uint32_t pos)
} else {
len += 16;
}
log_debug("bin length = %d\n", len);
ESP_LOGD(TAG, "bin length = %d", len);
return len;
}
@@ -161,7 +136,7 @@ void boot_cache_redirect( uint32_t pos, size_t size )
uint32_t count = (size + 0xffff) / 0x10000;
Cache_Read_Disable( 0 );
Cache_Flush( 0 );
log_debug( "mmu set paddr=%08x count=%d", pos_aligned, count );
ESP_LOGD(TAG, "mmu set paddr=%08x count=%d", pos_aligned, count );
cache_flash_mmu_set( 0, 0, 0x3f400000, pos_aligned, 64, count );
Cache_Read_Enable( 0 );
}
@@ -183,13 +158,13 @@ bool load_partition_table(bootloader_state_t* bs, uint32_t addr)
int index = 0;
char *partition_usage;
log_info("Partition Table:");
log_info("## Label Usage Type ST Offset Length");
ESP_LOGI(TAG, "Partition Table:");
ESP_LOGI(TAG, "## Label Usage Type ST Offset Length");
while (addr < end) {
log_debug("load partition table entry from %x(%08x)", addr, MEM_CACHE(addr));
ESP_LOGD(TAG, "load partition table entry from %x(%08x)", addr, MEM_CACHE(addr));
memcpy(&partition, MEM_CACHE(addr), sizeof(partition));
log_debug("type=%x subtype=%x", partition.type, partition.subtype);
ESP_LOGD(TAG, "type=%x subtype=%x", partition.type, partition.subtype);
partition_usage = "unknown";
if (partition.magic == PARTITION_MAGIC) { /* valid partition definition */
@@ -244,14 +219,14 @@ bool load_partition_table(bootloader_state_t* bs, uint32_t addr)
}
/* print partition type info */
log_info("%2d %-16s %-16s %02x %02x %08x %08x", index, partition.label, partition_usage,
ESP_LOGI(TAG, "%2d %-16s %-16s %02x %02x %08x %08x", index, partition.label, partition_usage,
partition.type, partition.subtype,
partition.pos.offset, partition.pos.size);
index++;
addr += sizeof(partition);
}
log_info("End of partition table");
ESP_LOGI(TAG,"End of partition table");
return true;
}
@@ -274,14 +249,7 @@ static bool ota_select_valid(const ota_select *s)
void bootloader_main()
{
//Run start routine.
/*ESP32 2ND bootload start here*/
log_info( "\n" );
log_info( "**************************************" );
log_info( "* hello espressif ESP32! *" );
log_info( "* 2nd boot is running! *" );
log_info( "* version (%s) *", BOOT_VERSION);
log_info( "**************************************");
ESP_LOGI(TAG, "Espressif ESP32 2nd stage bootloader v. %s", BOOT_VERSION);
struct flash_hdr fhdr;
bootloader_state_t bs;
@@ -289,7 +257,7 @@ void bootloader_main()
ota_select sa,sb;
memset(&bs, 0, sizeof(bs));
log_notice( "compile time %s\n", __TIME__ );
ESP_LOGI(TAG, "compile time " __TIME__ );
/* close watch dog here */
REG_CLR_BIT( RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
REG_CLR_BIT( TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN );
@@ -302,14 +270,14 @@ void bootloader_main()
print_flash_info(&fhdr);
if (!load_partition_table(&bs, PARTITION_ADD)) {
log_error("load partition table error!");
ESP_LOGE(TAG, "load partition table error!");
return;
}
partition_pos_t load_part_pos;
if (bs.ota_info.offset != 0) { // check if partition table has OTA info partition
//log_error("OTA info sector handling is not implemented");
//ESP_LOGE("OTA info sector handling is not implemented");
boot_cache_redirect(bs.ota_info.offset, bs.ota_info.size );
memcpy(&sa,MEM_CACHE(bs.ota_info.offset & 0x0000ffff),sizeof(sa));
memcpy(&sb,MEM_CACHE((bs.ota_info.offset + 0x1000)&0x0000ffff) ,sizeof(sb));
@@ -325,13 +293,13 @@ void bootloader_main()
spiRet1 = SPIEraseSector(bs.ota_info.offset/0x1000);
spiRet2 = SPIEraseSector(bs.ota_info.offset/0x1000+1);
if (spiRet1 != SPI_FLASH_RESULT_OK || spiRet2 != SPI_FLASH_RESULT_OK ) {
log_error(SPI_ERROR_LOG);
ESP_LOGE(TAG, SPI_ERROR_LOG);
return;
}
spiRet1 = SPIWrite(bs.ota_info.offset,(uint32_t *)&sa,sizeof(ota_select));
spiRet2 = SPIWrite(bs.ota_info.offset + 0x1000,(uint32_t *)&sb,sizeof(ota_select));
if (spiRet1 != SPI_FLASH_RESULT_OK || spiRet2 != SPI_FLASH_RESULT_OK ) {
log_error(SPI_ERROR_LOG);
ESP_LOGE(TAG, SPI_ERROR_LOG);
return;
}
Cache_Read_Enable(0);
@@ -344,7 +312,7 @@ void bootloader_main()
}else if(ota_select_valid(&sb)) {
load_part_pos = bs.ota[(sb.ota_seq - 1) % bs.app_count];
}else {
log_error("ota data partition info error");
ESP_LOGE(TAG, "ota data partition info error");
return;
}
}
@@ -353,15 +321,15 @@ void bootloader_main()
} else if (bs.test.offset != 0) { // otherwise, look for test app parition
load_part_pos = bs.test;
} else { // nothing to load, bail out
log_error("nothing to load");
ESP_LOGE(TAG, "nothing to load");
return;
}
log_info("Loading app partition at offset %08x", load_part_pos);
ESP_LOGI(TAG, "Loading app partition at offset %08x", load_part_pos);
if(fhdr.secury_boot_flag == 0x01) {
/* protect the 2nd_boot */
if(false == secure_boot()){
log_error("secure boot failed");
ESP_LOGE(TAG, "secure boot failed");
return;
}
}
@@ -369,7 +337,7 @@ void bootloader_main()
if(fhdr.encrypt_flag == 0x01) {
/* encrypt flash */
if (false == flash_encrypt(&bs)) {
log_error("flash encrypt failed");
ESP_LOGE(TAG, "flash encrypt failed");
return;
}
}
@@ -395,11 +363,15 @@ void unpack_load_app(const partition_pos_t* partition)
uint32_t irom_load_addr = 0;
uint32_t irom_size = 0;
log_debug("bin_header: %u %u %u %u %08x\n", image_header.magic,
image_header.blocks,
image_header.spi_mode,
image_header.spi_size,
(unsigned)image_header.entry_addr);
/* Reload the RTC memory sections whenever a non-deepsleep reset
is occuring */
bool load_rtc_memory = rtc_get_reset_reason(0) != DEEPSLEEP_RESET;
ESP_LOGD(TAG, "bin_header: %u %u %u %u %08x", image_header.magic,
image_header.blocks,
image_header.spi_mode,
image_header.spi_size,
(unsigned)image_header.entry_addr);
for (uint32_t section_index = 0;
section_index < image_header.blocks;
@@ -420,7 +392,7 @@ void unpack_load_app(const partition_pos_t* partition)
}
if (address >= DROM_LOW && address < DROM_HIGH) {
log_debug("found drom section, map from %08x to %08x\n", pos,
ESP_LOGD(TAG, "found drom section, map from %08x to %08x", pos,
section_header.load_addr);
drom_addr = partition->offset + pos - sizeof(section_header);
drom_load_addr = section_header.load_addr;
@@ -430,7 +402,7 @@ void unpack_load_app(const partition_pos_t* partition)
}
if (address >= IROM_LOW && address < IROM_HIGH) {
log_debug("found irom section, map from %08x to %08x\n", pos,
ESP_LOGD(TAG, "found irom section, map from %08x to %08x", pos,
section_header.load_addr);
irom_addr = partition->offset + pos - sizeof(section_header);
irom_load_addr = section_header.load_addr;
@@ -439,7 +411,18 @@ void unpack_load_app(const partition_pos_t* partition)
map = true;
}
log_notice("section %d: paddr=0x%08x vaddr=0x%08x size=0x%05x (%6d) %s", section_index, pos, section_header.load_addr, section_header.data_len, section_header.data_len, (load)?"load":(map)?"map":"");
if (!load_rtc_memory && address >= RTC_IRAM_LOW && address < RTC_IRAM_HIGH) {
ESP_LOGD(TAG, "Skipping RTC code section at %08x\n", pos);
load = false;
}
if (!load_rtc_memory && address >= RTC_DATA_LOW && address < RTC_DATA_HIGH) {
ESP_LOGD(TAG, "Skipping RTC data section at %08x\n", pos);
load = false;
}
ESP_LOGI(TAG, "section %d: paddr=0x%08x vaddr=0x%08x size=0x%05x (%6d) %s", section_index, pos,
section_header.load_addr, section_header.data_len, section_header.data_len, (load)?"load":(map)?"map":"");
if (!load) {
pos += section_header.data_len;
@@ -468,29 +451,29 @@ void IRAM_ATTR set_cache_and_start_app(
uint32_t irom_size,
uint32_t entry_addr)
{
log_debug("configure drom and irom and start\n");
ESP_LOGD(TAG, "configure drom and irom and start");
Cache_Read_Disable( 0 );
Cache_Read_Disable( 1 );
Cache_Flush( 0 );
Cache_Flush( 1 );
uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k
log_debug( "d mmu set paddr=%08x vaddr=%08x size=%d n=%d \n", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count );
ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count );
int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
log_debug( "rc=%d", rc );
ESP_LOGV(TAG, "rc=%d", rc );
rc = cache_flash_mmu_set( 1, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
log_debug( "rc=%d", rc );
ESP_LOGV(TAG, "rc=%d", rc );
uint32_t irom_page_count = (irom_size + 64*1024 - 1) / (64*1024); // round up to 64k
log_debug( "i mmu set paddr=%08x vaddr=%08x size=%d n=%d\n", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count );
ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count );
rc = cache_flash_mmu_set( 0, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
log_debug( "rc=%d", rc );
ESP_LOGV(TAG, "rc=%d", rc );
rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
log_debug( "rc=%d", rc );
ESP_LOGV(TAG, "rc=%d", rc );
REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
Cache_Read_Enable( 0 );
Cache_Read_Enable( 1 );
log_notice("start: 0x%08x\n", entry_addr);
ESP_LOGD(TAG, "start: 0x%08x", entry_addr);
typedef void (*entry_t)(void);
entry_t entry = ((entry_t) entry_addr);
@@ -506,11 +489,11 @@ void print_flash_info(struct flash_hdr* pfhdr)
struct flash_hdr fhdr = *pfhdr;
log_debug( "[D]: magic %02x\n", fhdr.magic );
log_debug( "[D]: blocks %02x\n", fhdr.blocks );
log_debug( "[D]: spi_mode %02x\n", fhdr.spi_mode );
log_debug( "[D]: spi_speed %02x\n", fhdr.spi_speed );
log_debug( "[D]: spi_size %02x\n", fhdr.spi_size );
ESP_LOGD(TAG, "magic %02x", fhdr.magic );
ESP_LOGD(TAG, "blocks %02x", fhdr.blocks );
ESP_LOGD(TAG, "spi_mode %02x", fhdr.spi_mode );
ESP_LOGD(TAG, "spi_speed %02x", fhdr.spi_speed );
ESP_LOGD(TAG, "spi_size %02x", fhdr.spi_size );
const char* str;
switch ( fhdr.spi_speed ) {
@@ -534,7 +517,7 @@ void print_flash_info(struct flash_hdr* pfhdr)
str = "20MHz";
break;
}
log_notice( " SPI Speed : %s", str );
ESP_LOGI(TAG, "SPI Speed : %s", str );
@@ -566,7 +549,7 @@ void print_flash_info(struct flash_hdr* pfhdr)
str = "DIO";
break;
}
log_notice( " SPI Mode : %s", str );
ESP_LOGI(TAG, "SPI Mode : %s", str );
@@ -595,6 +578,6 @@ void print_flash_info(struct flash_hdr* pfhdr)
str = "1MB";
break;
}
log_notice( " SPI Flash Size : %s", str );
ESP_LOGI(TAG, "SPI Flash Size : %s", str );
#endif
}

1
components/bootloader/src/main/component.mk
View File

@@ -8,6 +8,5 @@
#
COMPONENT_ADD_LDFLAGS := -L $(abspath .) -lmain -T esp32.bootloader.ld -T $(IDF_PATH)/components/esp32/ld/esp32.rom.ld
COMPONENT_EXTRA_INCLUDES := $(IDF_PATH)/components/esp32/include
include $(IDF_PATH)/make/component_common.mk

62
components/bootloader/src/main/flash_encrypt.c
View File

@@ -16,6 +16,7 @@
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "rom/cache.h"
#include "rom/ets_sys.h"
@@ -28,13 +29,14 @@
#include "sdkconfig.h"
#include "bootloader_log.h"
#include "bootloader_config.h"
static const char* TAG = "flash_encrypt";
/**
* @function : bitcount
* @description: caculate bit 1 in flash_crypt_cnt
* if it's even number ,need encrypt flash data,and burn efuse
* @description: calculate bit 1 in flash_crypt_cnt
* if it's even number, need encrypt flash data, and burn efuse
*
* @inputs: n flash_crypt_cnt
* @return: number of 1 in flash_crypt_cnt
@@ -68,19 +70,19 @@ bool flash_encrypt_write(uint32_t pos, uint32_t len)
spiRet = SPIRead(pos, buf, SPI_SEC_SIZE);
if (spiRet != SPI_FLASH_RESULT_OK) {
Cache_Read_Enable(0);
log_error(SPI_ERROR_LOG);
ESP_LOGE(TAG, SPI_ERROR_LOG);
return false;
}
spiRet = SPIEraseSector(pos/SPI_SEC_SIZE);
if (spiRet != SPI_FLASH_RESULT_OK) {
Cache_Read_Enable(0);
log_error(SPI_ERROR_LOG);
ESP_LOGE(TAG, SPI_ERROR_LOG);
return false;
}
spiRet = SPI_Encrypt_Write(pos, buf, SPI_SEC_SIZE);
if (spiRet != SPI_FLASH_RESULT_OK) {
Cache_Read_Enable(0);
log_error(SPI_ERROR_LOG);
ESP_LOGE(TAG, SPI_ERROR_LOG);
return false;
}
pos += SPI_SEC_SIZE;
@@ -104,53 +106,53 @@ bool flash_encrypt(bootloader_state_t *bs)
uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_FLASH_CRYPT_CNT);
uint8_t count = bitcount(flash_crypt_cnt);
int i = 0;
log_debug("flash crypt cnt %x, count %d\n", flash_crypt_cnt, count);
ESP_LOGD(TAG, "flash encrypt cnt %x, bitcount %d", flash_crypt_cnt, count);
if ((count % 2) == 0) {
boot_cache_redirect( 0, 64*1024);
/* encrypt iv and abstruct */
if (false == flash_encrypt_write(0,SPI_SEC_SIZE)) {
log_error("encrypt iv and abstruct error");
if (false == flash_encrypt_write(0, SPI_SEC_SIZE)) {
ESP_LOGE(TAG, "encrypt iv and abstract error");
return false;
}
/* encrypt write boot bin*/
bin_len = get_bin_len((uint32_t)MEM_CACHE(0x1000));
if(bin_len != 0) {
if (false == flash_encrypt_write(0x1000,bin_len)) {
log_error("encrypt 2nd boot error");
if (false == flash_encrypt_write(0x1000, bin_len)) {
ESP_LOGE(TAG, "encrypt 2nd boot error");
return false;
}
} else {
log_error("2nd boot len error");
ESP_LOGE(TAG, "2nd boot len error");
return false;
}
/* encrypt partition table */
if (false == flash_encrypt_write(PARTITION_ADD,SPI_SEC_SIZE)) {
log_error("encrypt partition table error");
if (false == flash_encrypt_write(PARTITION_ADD, SPI_SEC_SIZE)) {
ESP_LOGE(TAG, "encrypt partition table error");
return false;
}
/* encrypt write factory bin */
if(bs->factory.offset != 0x00) {
log_debug("have factory bin\n");
boot_cache_redirect(bs->factory.offset,bs->factory.size);
ESP_LOGD(TAG, "have factory bin");
boot_cache_redirect(bs->factory.offset, bs->factory.size);
bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->factory.offset&0xffff));
if(bin_len != 0) {
if (false == flash_encrypt_write(bs->factory.offset,bin_len)) {
log_error("encrypt factory bin error");
if (false == flash_encrypt_write(bs->factory.offset, bin_len)) {
ESP_LOGE(TAG, "encrypt factory bin error");
return false;
}
}
}
/* encrypt write test bin */
if(bs->test.offset != 0x00) {
ets_printf("have test bin\n");
boot_cache_redirect(bs->test.offset,bs->test.size);
ESP_LOGD(TAG, "have test bin");
boot_cache_redirect(bs->test.offset, bs->test.size);
bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->test.offset&0xffff));
if(bin_len != 0) {
if (false == flash_encrypt_write(bs->test.offset,bin_len)) {
log_error("encrypt test bin error");
if (false == flash_encrypt_write(bs->test.offset, bin_len)) {
ESP_LOGE(TAG, "encrypt test bin error");
return false;
}
}
@@ -158,33 +160,33 @@ bool flash_encrypt(bootloader_state_t *bs)
/* encrypt write ota bin */
for (i = 0;i<16;i++) {
if(bs->ota[i].offset != 0x00) {
log_debug("have ota[%d] bin\n",i);
boot_cache_redirect(bs->ota[i].offset,bs->ota[i].size);
ESP_LOGD(TAG, "have ota[%d] bin",i);
boot_cache_redirect(bs->ota[i].offset, bs->ota[i].size);
bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->ota[i].offset&0xffff));
if(bin_len != 0) {
if (false == flash_encrypt_write(bs->ota[i].offset,bin_len)) {
log_error("encrypt ota bin error");
if (false == flash_encrypt_write(bs->ota[i].offset, bin_len)) {
ESP_LOGE(TAG, "encrypt ota bin error");
return false;
}
}
}
}
/* encrypt write ota info bin */
if (false == flash_encrypt_write(bs->ota_info.offset,2*SPI_SEC_SIZE)) {
log_error("encrypt ota binfo error");
if (false == flash_encrypt_write(bs->ota_info.offset, 2*SPI_SEC_SIZE)) {
ESP_LOGE(TAG, "encrypt ota info error");
return false;
}
REG_SET_FIELD(EFUSE_BLK0_WDATA0_REG, EFUSE_FLASH_CRYPT_CNT, 0x04);
REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */
while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */
log_warn("burn flash_crypt_cnt\n");
ESP_LOGW(TAG, "burn flash_crypt_cnt");
REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */
REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */
while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */
return true;
} else {
log_info("flash already encrypted.\n");
ESP_LOGI(TAG, "flash already encrypted.");
return true;
}
}

28
components/bootloader/src/main/secure_boot.c
View File

@@ -16,6 +16,7 @@
#include "esp_attr.h"
#include "esp_types.h"
#include "esp_log.h"
#include "rom/cache.h"
#include "rom/ets_sys.h"
@@ -29,12 +30,13 @@
#include "sdkconfig.h"
#include "bootloader_log.h"
#include "bootloader_config.h"
static const char* TAG = "secure_boot";
/**
* @function : secure_boot_generate
* @description: generate boot abstruct & iv
* @description: generate boot abstract & iv
*
* @inputs: bool
*/
@@ -53,17 +55,17 @@ bool secure_boot_generate(uint32_t bin_len){
spiRet = SPIEraseSector(0);
if (spiRet != SPI_FLASH_RESULT_OK)
{
log_error(SPI_ERROR_LOG);
ESP_LOGE(TAG, SPI_ERROR_LOG);
return false;
}
/* write iv to flash, 0x0000, 128 bytes (1024 bits) */
spiRet = SPIWrite(0, buf, 128);
if (spiRet != SPI_FLASH_RESULT_OK)
{
log_error(SPI_ERROR_LOG);
ESP_LOGE(TAG, SPI_ERROR_LOG);
return false;
}
log_debug("write iv to flash.\n");
ESP_LOGD(TAG, "write iv to flash.");
Cache_Read_Enable(0);
/* read 4K code image from flash, for test */
for (i = 0; i < bin_len; i+=128) {
@@ -77,10 +79,10 @@ bool secure_boot_generate(uint32_t bin_len){
/* write abstract to flash, 0x0080, 64 bytes (512 bits) */
spiRet = SPIWrite(0x80, buf, 64);
if (spiRet != SPI_FLASH_RESULT_OK) {
log_error(SPI_ERROR_LOG);
ESP_LOGE(TAG, SPI_ERROR_LOG);
return false;
}
log_debug("write abstract to flash.\n");
ESP_LOGD(TAG, "write abstract to flash.");
Cache_Read_Enable(0);
return true;
}
@@ -88,7 +90,7 @@ bool secure_boot_generate(uint32_t bin_len){
/**
* @function : secure_boot
* @description: protect boot code inflash
* @description: protect boot code in flash
*
* @inputs: bool
*/
@@ -96,17 +98,17 @@ bool secure_boot(void){
uint32_t bin_len = 0;
if (REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_RD_ABS_DONE_0)
{
log_info("already secure boot !\n");
ESP_LOGD(TAG, "already secure boot !");
return true;
} else {
boot_cache_redirect( 0, 64*1024);
bin_len = get_bin_len((uint32_t)MEM_CACHE(0x1000));
if (bin_len == 0) {
log_error("boot len is error");
ESP_LOGE(TAG, "boot len is error");
return false;
}
if (false == secure_boot_generate(bin_len)){
log_error("secure boot generate failed");
ESP_LOGE(TAG, "secure boot generate failed");
return false;
}
}
@@ -115,11 +117,11 @@ bool secure_boot(void){
REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */
while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */
log_warn("burn abstract_done_0\n");
ESP_LOGW(TAG, "burn abstract_done_0");
REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */
REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */
while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */
log_debug("read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6_REG));
ESP_LOGI(TAG, "read EFUSE_BLK0_RDATA6 %x", REG_READ(EFUSE_BLK0_RDATA6_REG));
return true;
}

36
components/bt/Kconfig
View File

@@ -3,21 +3,27 @@ visible if MEMMAP_BT
config BT_ENABLED
bool "Enable low-level BT stack"
depends on MEMMAP_BT
help
This compiles in the low-level BT stack.
bool
depends on ESP32_ENABLE_STACK_BT
help
This compiles in the low-level BT stack.
config BT_BTLE
bool "Enable BTLE"
depends on BT_ENABLED
help
This compiles BTLE support
config BT_BT
bool "Enable classic BT"
depends on BT_ENABLED
help
This enables classic BT support
#config BT_BTLE
# bool "Enable BTLE"
# depends on BT_ENABLED
# help
# This compiles BTLE support
#
#config BT_BT
# bool "Enable classic BT"
# depends on BT_ENABLED
# help
# This enables classic BT support
endmenu
# Memory reserved at start of DRAM for Bluetooth stack
config BT_RESERVE_DRAM
hex
default 0x10000 if MEMMAP_BT
default 0

134
components/bt/bt.c Normal file
View File

@@ -0,0 +1,134 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stddef.h>
#include <stdlib.h>
#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "freertos/portmacro.h"
#include "esp_types.h"
#include "esp_system.h"
#include "esp_task.h"
#include "esp_intr.h"
#include "esp_attr.h"
#include "bt.h"
#if CONFIG_BT_ENABLED
/* not for user call, so don't put to include file */
extern void btdm_osi_funcs_register(void *osi_funcs);
extern void btdm_controller_init(void);
#define BT_DEBUG(...)
#define BT_API_CALL_CHECK(info, api_call, ret) \
do{\
esp_err_t __err = (api_call);\
if ((ret) != __err) {\
BT_DEBUG("%s %d %s ret=%d\n", __FUNCTION__, __LINE__, (info), __err);\
return __err;\
}\
} while(0)
struct osi_funcs_t {
xt_handler (*_set_isr)(int n, xt_handler f, void *arg);
void (*_ints_on)(unsigned int mask);
void (*_interrupt_disable)(void);
void (*_interrupt_restore)(void);
void (*_task_yield)(void);
void *(*_semphr_create)(uint32_t max, uint32_t init);
int32_t (*_semphr_give_from_isr)(void *semphr, void *hptw);
int32_t (*_semphr_take)(void *semphr, uint32_t block_time_ms);
void *(*_mutex_create)(void);
int32_t (*_mutex_lock)(void *mutex);
int32_t (*_mutex_unlock)(void *mutex);
esp_err_t (* _read_efuse_mac)(uint8_t mac[6]);
};
static portMUX_TYPE global_int_mux = portMUX_INITIALIZER_UNLOCKED;
static void IRAM_ATTR interrupt_disable(void)
{
portENTER_CRITICAL(&global_int_mux);
}
static void IRAM_ATTR interrupt_restore(void)
{
portEXIT_CRITICAL(&global_int_mux);
}
static void * IRAM_ATTR semphr_create_wrapper(uint32_t max, uint32_t init)
{
return (void *)xSemaphoreCreateCounting(max, init);
}
static int32_t IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw)
{
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
}
static int32_t IRAM_ATTR semphr_take_wrapper(void *semphr, uint32_t block_time_ms)
{
return (int32_t)xSemaphoreTake(semphr, block_time_ms / portTICK_RATE_MS);
}
static void * IRAM_ATTR mutex_create_wrapper(void)
{
return (void *)xSemaphoreCreateMutex();
}
static int32_t IRAM_ATTR mutex_lock_wrapper(void *mutex)
{
return (int32_t)xSemaphoreTake(mutex, portMAX_DELAY);
}
static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex)
{
return (int32_t)xSemaphoreGive(mutex);
}
static struct osi_funcs_t osi_funcs = {
._set_isr = xt_set_interrupt_handler,
._ints_on = xt_ints_on,
._interrupt_disable = interrupt_disable,
._interrupt_restore = interrupt_restore,
._task_yield = vPortYield,
._semphr_create = semphr_create_wrapper,
._semphr_give_from_isr = semphr_give_from_isr_wrapper,
._semphr_take = semphr_take_wrapper,
._mutex_create = mutex_create_wrapper,
._mutex_lock = mutex_lock_wrapper,
._mutex_unlock = mutex_unlock_wrapper,
._read_efuse_mac = system_efuse_read_mac,
};
static void bt_controller_task(void *pvParam)
{
btdm_osi_funcs_register(&osi_funcs);
btdm_controller_init();
}
void bt_controller_init()
{
xTaskCreatePinnedToCore(bt_controller_task, "btController",
ESP_TASK_BT_CONTROLLER_STACK, NULL,
ESP_TASK_BT_CONTROLLER_PRIO, NULL, 0);
}
#endif

23
components/bt/component.mk Normal file
View File

@@ -0,0 +1,23 @@
#
# Component Makefile
#
#COMPONENT_ADD_INCLUDEDIRS :=
COMPONENT_ADD_INCLUDEDIRS := include
CFLAGS += -Wno-error=unused-label -Wno-error=return-type -Wno-error=missing-braces -Wno-error=pointer-sign -Wno-error=parentheses
LIBS := btdm_app
COMPONENT_ADD_LDFLAGS := -lbt -L$(abspath lib) \
$(addprefix -l,$(LIBS)) \
$(LINKER_SCRIPTS)
include $(IDF_PATH)/make/component_common.mk
ALL_LIB_FILES := $(patsubst %,$(COMPONENT_PATH)/lib/lib%.a,$(LIBS))
$(COMPONENT_LIBRARY): $(ALL_LIB_FILES)
# automatically trigger a git submodule update if BT library is missing
$(eval $(call SubmoduleCheck,$(ALL_LIB_FILES),$(COMPONENT_PATH)/lib))

69
components/bt/include/bt.h Normal file
View File

@@ -0,0 +1,69 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __BT_H__
#define __BT_H__
#include <stdint.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize BT controller
*
* This function should be called only once, before any other BT functions are called.
*/
void bt_controller_init();
/** @brief: vhci_host_callback
* used for vhci call host function to notify what host need to do
*
* notify_host_send_available: notify host can send packet to controller
* notify_host_recv: notify host that controller has packet send to host
*/
typedef struct vhci_host_callback {
void (*notify_host_send_available)(void);
int (*notify_host_recv)(uint8_t *data, uint16_t len);
} vhci_host_callback_t;
/** @brief: API_vhci_host_check_send_available
* used for check actively if the host can send packet to controller or not.
* return true for ready to send, false means cannot send packet
*/
bool API_vhci_host_check_send_available(void);
/** @brief: API_vhci_host_send_packet
* host send packet to controller
* param data is the packet point, the param len is the packet length
* return void
*/
void API_vhci_host_send_packet(uint8_t *data, uint16_t len);
/** @brief: API_vhci_host_register_callback
* register the vhci referece callback, the call back
* struct defined by vhci_host_callback structure.
* param is the vhci_host_callback type variable
*/
void API_vhci_host_register_callback(const vhci_host_callback_t *callback);
#ifdef __cplusplus
}
#endif
#endif /* __BT_H__ */

1
components/bt/lib Submodule

Submodule components/bt/lib added at bcbc35215c

14
components/driver/component.mk Normal file
View File

@@ -0,0 +1,14 @@
#
# Component Makefile
#
# This Makefile should, at the very least, just include $(SDK_PATH)/make/component.mk. By default,
# this will take the sources in this directory, compile them and link them into
# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
# please read the SDK documents if you need to do this.
#
COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_PRIV_INCLUDEDIRS := include/driver
include $(IDF_PATH)/make/component_common.mk

368
components/driver/gpio.c Normal file
View File

@@ -0,0 +1,368 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include "esp_err.h"
#include "esp_intr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/xtensa_api.h"
#include "driver/gpio.h"
#include "soc/soc.h"
//TODO: move debug options to menuconfig
#define GPIO_DBG_ENABLE (0)
#define GPIO_WARNING_ENABLE (0)
#define GPIO_ERROR_ENABLE (0)
#define GPIO_INFO_ENABLE (0)
//DBG INFOR
#if GPIO_INFO_ENABLE
#define GPIO_INFO ets_printf
#else
#define GPIO_INFO(...)
#endif
#if GPIO_WARNING_ENABLE
#define GPIO_WARNING(format,...) do{\
ets_printf("[waring][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define GPIO_WARNING(...)
#endif
#if GPIO_ERROR_ENABLE
#define GPIO_ERROR(format,...) do{\
ets_printf("[error][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define GPIO_ERROR(...)
#endif
const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
GPIO_PIN_REG_0,
GPIO_PIN_REG_1,
GPIO_PIN_REG_2,
GPIO_PIN_REG_3,
GPIO_PIN_REG_4,
GPIO_PIN_REG_5,
GPIO_PIN_REG_6,
GPIO_PIN_REG_7,
GPIO_PIN_REG_8,
GPIO_PIN_REG_9,
GPIO_PIN_REG_10,
GPIO_PIN_REG_11,
GPIO_PIN_REG_12,
GPIO_PIN_REG_13,
GPIO_PIN_REG_14,
GPIO_PIN_REG_15,
GPIO_PIN_REG_16,
GPIO_PIN_REG_17,
GPIO_PIN_REG_18,
GPIO_PIN_REG_19,
0,
GPIO_PIN_REG_21,
GPIO_PIN_REG_22,
GPIO_PIN_REG_23,
0,
GPIO_PIN_REG_25,
GPIO_PIN_REG_26,
GPIO_PIN_REG_27,
0,
0,
0,
0,
GPIO_PIN_REG_32,
GPIO_PIN_REG_33,
GPIO_PIN_REG_34,
GPIO_PIN_REG_35,
GPIO_PIN_REG_36,
GPIO_PIN_REG_37,
GPIO_PIN_REG_38,
GPIO_PIN_REG_39
};
static int is_valid_gpio(int gpio_num)
{
if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) {
GPIO_ERROR("GPIO io_num=%d does not exist\n",gpio_num);
return 0;
}
return 1;
}
esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(intr_type >= GPIO_INTR_MAX) {
GPIO_ERROR("Unknown GPIO intr:%u\n",intr_type);
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].int_type = intr_type;
return ESP_OK;
}
esp_err_t gpio_intr_enable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(xPortGetCoreID() == 0) {
GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr
} else {
GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr
}
return ESP_OK;
}
esp_err_t gpio_intr_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr
return ESP_OK;
}
static esp_err_t gpio_output_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num < 32) {
GPIO.enable_w1tc = (0x1 << gpio_num);
} else {
GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
}
return ESP_OK;
}
static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
{
if(gpio_num >= 34) {
GPIO_ERROR("io_num=%d can only be input\n",gpio_num);
return ESP_ERR_INVALID_ARG;
}
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num < 32) {
GPIO.enable_w1ts = (0x1 << gpio_num);
} else {
GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
}
return ESP_OK;
}
esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level)
{
if(!GPIO_IS_VALID_GPIO(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(level) {
if(gpio_num < 32) {
GPIO.out_w1ts = (1 << gpio_num);
} else {
GPIO.out1_w1ts.data = (1 << (gpio_num - 32));
}
} else {
if(gpio_num < 32) {
GPIO.out_w1tc = (1 << gpio_num);
} else {
GPIO.out1_w1tc.data = (1 << (gpio_num - 32));
}
}
return ESP_OK;
}
int gpio_get_level(gpio_num_t gpio_num)
{
if(gpio_num < 32) {
return (GPIO.in >> gpio_num) & 0x1;
} else {
return (GPIO.in1.data >> (gpio_num - 32)) & 0x1;
}
}
esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
switch(pull) {
case GPIO_PULLUP_ONLY:
PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_PULLDOWN_ONLY:
PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_PULLUP_PULLDOWN:
PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_FLOATING:
PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]);
break;
default:
GPIO_ERROR("Unknown pull up/down mode,gpio_num=%u,pull=%u\n",gpio_num,pull);
ret = ESP_ERR_INVALID_ARG;
break;
}
return ret;
}
esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
if(gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) {
GPIO_ERROR("io_num=%d can only be input\n",gpio_num);
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
if(mode & GPIO_MODE_DEF_INPUT) {
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
} else {
PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
}
if(mode & GPIO_MODE_DEF_OUTPUT) {
if(gpio_num < 32) {
GPIO.enable_w1ts = (0x1 << gpio_num);
} else {
GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
}
} else {
if(gpio_num < 32) {
GPIO.enable_w1tc = (0x1 << gpio_num);
} else {
GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
}
}
if(mode & GPIO_MODE_DEF_OD) {
GPIO.pin[gpio_num].pad_driver = 1;
} else {
GPIO.pin[gpio_num].pad_driver = 0;
}
return ret;
}
esp_err_t gpio_config(gpio_config_t *pGPIOConfig)
{
uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask);
uint32_t io_reg = 0;
uint32_t io_num = 0;
uint64_t bit_valid = 0;
if(pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) {
GPIO_ERROR("GPIO_PIN mask error \n");
return ESP_ERR_INVALID_ARG;
}
if((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) {
//GPIO 34/35/36/37/38/39 can only be used as input mode;
if((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) {
GPIO_ERROR("GPIO34-39 can only be used as input mode\n");
return ESP_ERR_INVALID_ARG;
}
}
do {
io_reg = GPIO_PIN_MUX_REG[io_num];
if(((gpio_pin_mask >> io_num) & BIT(0)) && io_reg) {
GPIO_INFO("Gpio%02d |Mode:",io_num);
if((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) {
GPIO_INFO("INPUT ");
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_num]);
} else {
PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[io_num]);
}
if((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) {
GPIO_INFO("OD ");
GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */
} else {
GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */
}
if((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) {
GPIO_INFO("OUTPUT ");
gpio_output_enable(io_num);
} else {
gpio_output_disable(io_num);
}
GPIO_INFO("|");
if(pGPIOConfig->pull_up_en) {
GPIO_INFO("PU ");
PIN_PULLUP_EN(io_reg);
} else {
PIN_PULLUP_DIS(io_reg);
}
if(pGPIOConfig->pull_down_en) {
GPIO_INFO("PD ");
PIN_PULLDWN_EN(io_reg);
} else {
PIN_PULLDWN_DIS(io_reg);
}
GPIO_INFO("Intr:%d |\n",pGPIOConfig->intr_type);
gpio_set_intr_type(io_num, pGPIOConfig->intr_type);
if(pGPIOConfig->intr_type) {
gpio_intr_enable(io_num);
} else {
gpio_intr_disable(io_num);
}
PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */
} else if(bit_valid && (io_reg == 0)) {
GPIO_WARNING("io_num=%d does not exist\n",io_num);
}
io_num++;
} while(io_num < GPIO_PIN_COUNT);
return ESP_OK;
}
esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg)
{
if(fn == NULL) {
return ESP_ERR_INVALID_ARG;
}
ESP_INTR_DISABLE(gpio_intr_num);
intr_matrix_set(xPortGetCoreID(), ETS_GPIO_INTR_SOURCE, gpio_intr_num);
xt_set_interrupt_handler(gpio_intr_num, fn, arg);
ESP_INTR_ENABLE(gpio_intr_num);
return ESP_OK;
}
/*only level interrupt can be used for wake-up function*/
esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
if((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) {
GPIO.pin[gpio_num].int_type = intr_type;
GPIO.pin[gpio_num].wakeup_enable = 0x1;
} else {
GPIO_ERROR("GPIO wakeup only support Level mode,but edge mode set. gpio_num:%u\n",gpio_num);
ret = ESP_ERR_INVALID_ARG;
}
return ret;
}
esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
GPIO.pin[gpio_num].wakeup_enable = 0;
return ESP_OK;
}

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_GPIO_H_
#define _DRIVER_GPIO_H_
#include "esp_err.h"
#include <esp_types.h>
#include "soc/gpio_reg.h"
#include "soc/gpio_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/io_mux_reg.h"
#include "rom/gpio.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_SEL_0 (BIT(0)) /* Pin 0 selected */
#define GPIO_SEL_1 (BIT(1)) /* Pin 1 selected */
#define GPIO_SEL_2 (BIT(2)) /* Pin 2 selected */
#define GPIO_SEL_3 (BIT(3)) /* Pin 3 selected */
#define GPIO_SEL_4 (BIT(4)) /* Pin 4 selected */
#define GPIO_SEL_5 (BIT(5)) /* Pin 5 selected */
#define GPIO_SEL_6 (BIT(6)) /* Pin 6 selected */
#define GPIO_SEL_7 (BIT(7)) /* Pin 7 selected */
#define GPIO_SEL_8 (BIT(8)) /* Pin 8 selected */
#define GPIO_SEL_9 (BIT(9)) /* Pin 9 selected */
#define GPIO_SEL_10 (BIT(10)) /* Pin 10 selected */
#define GPIO_SEL_11 (BIT(11)) /* Pin 11 selected */
#define GPIO_SEL_12 (BIT(12)) /* Pin 12 selected */
#define GPIO_SEL_13 (BIT(13)) /* Pin 13 selected */
#define GPIO_SEL_14 (BIT(14)) /* Pin 14 selected */
#define GPIO_SEL_15 (BIT(15)) /* Pin 15 selected */
#define GPIO_SEL_16 (BIT(16)) /* Pin 16 selected */
#define GPIO_SEL_17 (BIT(17)) /* Pin 17 selected */
#define GPIO_SEL_18 (BIT(18)) /* Pin 18 selected */
#define GPIO_SEL_19 (BIT(19)) /* Pin 19 selected */
#define GPIO_SEL_21 (BIT(21)) /* Pin 21 selected */
#define GPIO_SEL_22 (BIT(22)) /* Pin 22 selected */
#define GPIO_SEL_23 (BIT(23)) /* Pin 23 selected */
#define GPIO_SEL_25 (BIT(25)) /* Pin 25 selected */
#define GPIO_SEL_26 (BIT(26)) /* Pin 26 selected */
#define GPIO_SEL_27 (BIT(27)) /* Pin 27 selected */
#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /* Pin 32 selected */
#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /* Pin 33 selected */
#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /* Pin 34 selected */
#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /* Pin 35 selected */
#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /* Pin 36 selected */
#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /* Pin 37 selected */
#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /* Pin 38 selected */
#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /* Pin 39 selected */
#define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U
#define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U
#define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U
#define GPIO_PIN_REG_3 PERIPHS_IO_MUX_U0RXD_U
#define GPIO_PIN_REG_4 PERIPHS_IO_MUX_GPIO4_U
#define GPIO_PIN_REG_5 PERIPHS_IO_MUX_GPIO5_U
#define GPIO_PIN_REG_6 PERIPHS_IO_MUX_SD_CLK_U
#define GPIO_PIN_REG_7 PERIPHS_IO_MUX_SD_DATA0_U
#define GPIO_PIN_REG_8 PERIPHS_IO_MUX_SD_DATA1_U
#define GPIO_PIN_REG_9 PERIPHS_IO_MUX_SD_DATA2_U
#define GPIO_PIN_REG_10 PERIPHS_IO_MUX_SD_DATA3_U
#define GPIO_PIN_REG_11 PERIPHS_IO_MUX_SD_CMD_U
#define GPIO_PIN_REG_12 PERIPHS_IO_MUX_MTDI_U
#define GPIO_PIN_REG_13 PERIPHS_IO_MUX_MTCK_U
#define GPIO_PIN_REG_14 PERIPHS_IO_MUX_MTMS_U
#define GPIO_PIN_REG_15 PERIPHS_IO_MUX_MTDO_U
#define GPIO_PIN_REG_16 PERIPHS_IO_MUX_GPIO16_U
#define GPIO_PIN_REG_17 PERIPHS_IO_MUX_GPIO17_U
#define GPIO_PIN_REG_18 PERIPHS_IO_MUX_GPIO18_U
#define GPIO_PIN_REG_19 PERIPHS_IO_MUX_GPIO19_U
#define GPIO_PIN_REG_20 PERIPHS_IO_MUX_GPIO20_U
#define GPIO_PIN_REG_21 PERIPHS_IO_MUX_GPIO21_U
#define GPIO_PIN_REG_22 PERIPHS_IO_MUX_GPIO22_U
#define GPIO_PIN_REG_23 PERIPHS_IO_MUX_GPIO23_U
#define GPIO_PIN_REG_25 PERIPHS_IO_MUX_GPIO25_U
#define GPIO_PIN_REG_26 PERIPHS_IO_MUX_GPIO26_U
#define GPIO_PIN_REG_27 PERIPHS_IO_MUX_GPIO27_U
#define GPIO_PIN_REG_32 PERIPHS_IO_MUX_GPIO32_U
#define GPIO_PIN_REG_33 PERIPHS_IO_MUX_GPIO33_U
#define GPIO_PIN_REG_34 PERIPHS_IO_MUX_GPIO34_U
#define GPIO_PIN_REG_35 PERIPHS_IO_MUX_GPIO35_U
#define GPIO_PIN_REG_36 PERIPHS_IO_MUX_GPIO36_U
#define GPIO_PIN_REG_37 PERIPHS_IO_MUX_GPIO37_U
#define GPIO_PIN_REG_38 PERIPHS_IO_MUX_GPIO38_U
#define GPIO_PIN_REG_39 PERIPHS_IO_MUX_GPIO39_U
#define GPIO_APP_CPU_INTR_ENA (BIT(0))
#define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_PRO_CPU_INTR_ENA (BIT(2))
#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(3))
#define GPIO_SDIO_EXT_INTR_ENA (BIT(4))
#define GPIO_MODE_DEF_INPUT (BIT0)
#define GPIO_MODE_DEF_OUTPUT (BIT1)
#define GPIO_MODE_DEF_OD (BIT2)
#define GPIO_PIN_COUNT 40
extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT];
#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) //to decide whether it is a valid GPIO number
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) //to decide whether it can be a valid GPIO number of output mode
typedef enum {
GPIO_NUM_0 = 0,
GPIO_NUM_1 = 1,
GPIO_NUM_2 = 2,
GPIO_NUM_3 = 3,
GPIO_NUM_4 = 4,
GPIO_NUM_5 = 5,
GPIO_NUM_6 = 6,
GPIO_NUM_7 = 7,
GPIO_NUM_8 = 8,
GPIO_NUM_9 = 9,
GPIO_NUM_10 = 10,
GPIO_NUM_11 = 11,
GPIO_NUM_12 = 12,
GPIO_NUM_13 = 13,
GPIO_NUM_14 = 14,
GPIO_NUM_15 = 15,
GPIO_NUM_16 = 16,
GPIO_NUM_17 = 17,
GPIO_NUM_18 = 18,
GPIO_NUM_19 = 19,
GPIO_NUM_21 = 21,
GPIO_NUM_22 = 22,
GPIO_NUM_23 = 23,
GPIO_NUM_25 = 25,
GPIO_NUM_26 = 26,
GPIO_NUM_27 = 27,
GPIO_NUM_32 = 32,
GPIO_NUM_33 = 33,
GPIO_NUM_34 = 34, /*input mode only */
GPIO_NUM_35 = 35, /*input mode only */
GPIO_NUM_36 = 36, /*input mode only */
GPIO_NUM_37 = 37, /*input mode only */
GPIO_NUM_38 = 38, /*input mode only */
GPIO_NUM_39 = 39, /*input mode only */
} gpio_num_t;
typedef enum {
GPIO_INTR_DISABLE = 0, /* disable GPIO interrupt */
GPIO_INTR_POSEDGE = 1, /* GPIO interrupt type : rising edge */
GPIO_INTR_NEGEDGE = 2, /* GPIO interrupt type : falling edge */
GPIO_INTR_ANYEDGE = 3, /* GPIO interrupt type : both rising and falling edge */
GPIO_INTR_LOW_LEVEL = 4, /* GPIO interrupt type : input low level trigger */
GPIO_INTR_HIGH_LEVEL = 5, /* GPIO interrupt type : input high level trigger */
GPIO_INTR_MAX,
} gpio_int_type_t;
typedef enum {
GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT, /* GPIO mode : input only */
GPIO_MODE_OUTPUT = GPIO_MODE_DEF_OUTPUT, /* GPIO mode : output only mode */
GPIO_MODE_OUTPUT_OD = ((GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)), /* GPIO mode : output only with open-drain mode */
GPIO_MODE_INPUT_OUTPUT_OD = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)), /* GPIO mode : output and input with open-drain mode*/
GPIO_MODE_INPUT_OUTPUT = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)), /* GPIO mode : output and input mode */
} gpio_mode_t;
typedef enum {
GPIO_PULLUP_DISABLE = 0x0, /* disable GPIO pull-up resistor */
GPIO_PULLUP_ENABLE = 0x1, /* enable GPIO pull-up resistor */
} gpio_pullup_t;
typedef enum {
GPIO_PULLDOWN_DISABLE = 0x0, /* disable GPIO pull-down resistor */
GPIO_PULLDOWN_ENABLE = 0x1, /* enable GPIO pull-down resistor */
} gpio_pulldown_t;
typedef struct {
uint64_t pin_bit_mask; /* GPIO pin: set with bit mask, each bit maps to a GPIO */
gpio_mode_t mode; /* GPIO mode: set input/output mode */
gpio_pullup_t pull_up_en; /* GPIO pull-up */
gpio_pulldown_t pull_down_en; /* GPIO pull-down */
gpio_int_type_t intr_type; /* GPIO interrupt type */
} gpio_config_t;
typedef enum {
GPIO_LOW_LEVEL = 0,
GPIO_HIGH_LEVEL = 1,
GPIO_LEVEL_ERR,
} gpio_level_t;
typedef enum {
GPIO_PULLUP_ONLY, /* Pad pull up */
GPIO_PULLDOWN_ONLY, /* Pad pull down */
GPIO_PULLUP_PULLDOWN, /* Pad pull up + pull down*/
GPIO_FLOATING, /* Pad floating */
} gpio_pull_mode_t;
typedef void (*gpio_event_callback)(gpio_num_t gpio_intr_num);
/** \defgroup Driver_APIs Driver APIs
* @brief Driver APIs
*/
/** @addtogroup Driver_APIs
* @{
*/
/** \defgroup GPIO_Driver_APIs GPIO Driver APIs
* @brief GPIO APIs
*/
/** @addtogroup GPIO_Driver_APIs
* @{
*/
/**
* @brief GPIO common configuration
*
* Use this Function ,Configure GPIO's Mode,pull-up,PullDown,IntrType
*
* @parameter[in] pGPIOConfig
* pGPIOConfig.pin_bit_mask : Configure GPIO pins bits,set this parameter with bit mask.
* If you want to configure GPIO34 and GPIO16, pin_bit_mask=GPIO_Pin_16|GPIO_Pin_34;
* pGPIOConfig.mode : Configure GPIO mode,such as output ,input...
* pGPIOConfig.pull_up_en : Enable or Disable pull-up
* pGPIOConfig.pull_down_en : Enable or Disable pull-down
* pGPIOConfig.intr_type : Configure GPIO interrupt trigger type
* @return ESP_OK: success ;
* ESP_ERR_INVALID_ARG: parameter error
* ESP_FAIL : GPIO error
*
*/
esp_err_t gpio_config(gpio_config_t *pGPIOConfig);
/**
* @brief GPIO set interrupt trigger type
*
* @parameter[in] gpio_num : GPIO number.
* If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] intr_type: interrupt type, select from gpio_int_type_t
*
* @return ESP_OK : success
* ESP_ERR_INVALID_ARG: parameter error
*
*/
esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type);
/**
* @brief enable GPIO module interrupt signal
*
* @parameter[in] gpio_num : GPIO number.
* If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16);
*
* @return ESP_OK : success
* ESP_ERR_INVALID_ARG: parameter error
*
*/
esp_err_t gpio_intr_enable(gpio_num_t gpio_num);
/**
* @brief disable GPIO module interrupt signal
*
* @parameter[in] gpio_num : GPIO number.
* If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16);
*
* @return ESP_OK : success
* ESP_ERR_INVALID_ARG: parameter error
*
*/
esp_err_t gpio_intr_disable(gpio_num_t gpio_num);
/**
* @brief GPIO set output level
*
* @parameter[in] gpio_num : GPIO number.
* If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] level : Output level. 0: low ; 1: high
*
* @return ESP_OK : success
* ESP_FAIL : GPIO error
*
*/
esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level);
/**
* @brief GPIO get input level
*
* @parameter[in] gpio_num : GPIO number.
* If you want to get level of pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
*
* @return 0 : the GPIO input level is 0
* 1 : the GPIO input level is 1
*
*/
int gpio_get_level(gpio_num_t gpio_num);
/**
* @brief GPIO set direction
*
* Configure GPIO direction,such as output_only,input_only,output_and_input
*
* @parameter[in] gpio_num : Configure GPIO pins number,it should be GPIO number.
* If you want to set direction of GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] mode : Configure GPIO direction,such as output_only,input_only,...
*
* @return ESP_OK : success
* ESP_ERR_INVALID_ARG : fail
* ESP_FAIL : GPIO error
*
*/
esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode);
/**
* @brief GPIO set pull
*
* User this Function,configure GPIO pull mode,such as pull-up,pull-down
*
* @parameter[in] gpio_num : Configure GPIO pins number,it should be GPIO number.
* If you want to set pull up or down mode for GPIO16,gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] pull : Configure GPIO pull up/down mode,such as pullup_only,pulldown_only,pullup_and_pulldown,...
*
* @return ESP_OK : success
* ESP_ERR_INVALID_ARG : fail
* ESP_FAIL : GPIO error
*
*/
esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull);
/**
* @brief enable GPIO wake-up function.
*
* @param gpio_num_t gpio_num : GPIO number.
*
* @param gpio_int_type_t intr_type : only GPIO_INTR_LOLEVEL\GPIO_INTR_HILEVEL can be used
*
* @return ESP_OK: success
* ESP_ERR_INVALID_ARG: parameter error
*/
esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type);
/**
* @brief disable GPIO wake-up function.
*
* @param gpio_num_t gpio_num: GPIO number
*
* @return ESP_OK: success
* ESP_ERR_INVALID_ARG: parameter error
*/
esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num);
/**
* @brief register GPIO interrupt handler, the handler is an ISR.
* The handler will be attached to the same CPU core that this function is running on.
* Users should know that which CPU is running and then pick a INUM that is not used by system.
* We can find the information of INUM and interrupt level in soc.h.
* TODO: to move INUM options to menu_config
* @parameter uint32_t gpio_intr_num : GPIO interrupt number,check the info in soc.h, and please see the core-isa.h for more details
* @parameter void (* fn)(void* ) : interrupt handler function.
* Note that the handler function MUST be defined with attribution of "IRAM_ATTR".
* @parameter void * arg : parameter for handler function
*
* @return ESP_OK : success ;
* ESP_FAIL: gpio error
*/
esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg);
/**
* *************** ATTENTION ********************/
/**
*
* Each GPIO has its own separate configuration register, so we do not use
* a lock to serialize access to them. This works under the assumption that
* no situation will occur where two tasks try to configure the same GPIO
* pin simultaneously. It is up to the application developer to guarantee this.
*/
/*----------EXAMPLE TO CONIFGURE GPIO AS OUTPUT ------------ */
/* gpio_config_t io_conf;
* io_conf.intr_type = GPIO_INTR_DISABLE; //disable interrupt
* io_conf.mode = GPIO_MODE_OUTPUT; //set as output mode
* io_conf.pin_bit_mask = GPIO_SEL_18 | GPIO_SEL_19; //bit mask of the pins that you want to set,e.g.GPIO18/19
* io_conf.pull_down_en = 0; //disable pull-down mode
* io_conf.pull_up_en = 0; //disable pull-up mode
* gpio_config(&io_conf); //configure GPIO with the given settings
**/
/*----------EXAMPLE TO CONIFGURE GPIO AS OUTPUT ------------ */
/* io_conf.intr_type = GPIO_INTR_POSEDGE; //set posedge interrupt
* io_conf.mode = GPIO_MODE_INPUT; //set as input
* io_conf.pin_bit_mask = GPIO_SEL_4 | GPIO_SEL_5; //bit mask of the pins that you want to set, e.g.,GPIO4/5
* io_conf.pull_down_en = 0; //disable pull-down mode
* io_conf.pull_up_en = 1; //enable pull-up mode
* gpio_config(&io_conf); //configure GPIO with the given settings
*----------EXAMPLE TO SET ISR HANDLER ----------------------*/
/* gpio_isr_register(18,gpio_intr_test,NULL); //hook the isr handler for GPIO interrupt
* //the first parameter is INUM, you can pick one form interrupt level 1/2 which is not used by the system.
* //NOTE1:user should arrange the INUMs that used, better not to use a same INUM for different interrupt.
* //NOTE2:do not pick the INUM that already occupied by the system.
* //NOTE3:refer to soc.h to check which INUMs that can be used.
*-------------EXAMPLE OF HANDLER FUNCTION-------------------*/
/*#include "esp_attr.h"
* void IRAM_ATTR gpio_intr_test(void* arg)
*{
* //GPIO intr process
* ets_printf("in gpio_intr\n");
* uint32_t gpio_num = 0;
* uint32_t gpio_intr_status = READ_PERI_REG(GPIO_STATUS_REG); //read status to get interrupt status for GPIO0-31
* uint32_t gpio_intr_status_h = READ_PERI_REG(GPIO_STATUS1_REG);//read status1 to get interrupt status for GPIO32-39
* SET_PERI_REG_MASK(GPIO_STATUS_W1TC_REG, gpio_intr_status); //Clear intr for gpio0-gpio31
* SET_PERI_REG_MASK(GPIO_STATUS1_W1TC_REG, gpio_intr_status_h); //Clear intr for gpio32-39
* do {
* if(gpio_num < 32) {
* if(gpio_intr_status & BIT(gpio_num)) { //gpio0-gpio31
* ets_printf("Intr GPIO%d ,val: %d\n",gpio_num,gpio_get_level(gpio_num));
* //This is an isr handler, you should post an event to process it in RTOS queue.
* }
* } else {
* if(gpio_intr_status_h & BIT(gpio_num - 32)) {
* ets_printf("Intr GPIO%d, val : %d\n",gpio_num,gpio_get_level(gpio_num));
* //This is an isr handler, you should post an event to process it in RTOS queue.
* }
* }
* } while(++gpio_num < GPIO_PIN_COUNT);
*}
*----EXAMPLE OF I2C CONFIG AND PICK SIGNAL FOR IO MATRIX---*/
/* gpio_config_t io_conf;
* io_conf.intr_type = GPIO_INTR_DISABLE; //disable interrupt
* io_conf.mode = GPIO_MODE_INPUT_OUTPUT_OD; //set as output mode
* io_conf.pin_bit_mask = GPIO_SEL_21 | GPIO_SEL_22; //bit mask of the pins that you want to set,e.g.GPIO21/22
* io_conf.pull_down_en = 0; //disable pull-down mode
* io_conf.pull_up_en = 1; //enable pull-up mode
* gpio_config(&io_conf); //configure GPIO with the given settings
* gpio_matrix_out(21, EXT_I2C_SCL_O_IDX, 0, 0); //set output signal for io_matrix
* gpio_matrix_out(22, EXT_I2C_SDA_O_IDX, 0, 0); //set output signal for io_matrix
* gpio_matrix_in( 22, EXT_I2C_SDA_I_IDX, 0); //set input signal for io_matrix
*
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _DRIVER_GPIO_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_LEDC_H_
#define _DRIVER_LEDC_H_
#include "esp_err.h"
#include "soc/soc.h"
#include "soc/ledc_reg.h"
#include "soc/ledc_reg.h"
#include "soc/ledc_struct.h"
#include "driver/gpio.h"
#include "driver/periph_ctrl.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LEDC_APB_CLK_HZ (APB_CLK_FREQ)
#define LEDC_REF_CLK_HZ (1*1000000)
typedef enum {
LEDC_HIGH_SPEED_MODE = 0, /*LEDC high speed speed_mode */
//in this version, we only support high speed speed_mode. We will access low speed speed_mode later
//LEDC_LOW_SPEED_MODE, /*LEDC low speed speed_mode */
LEDC_SPEED_MODE_MAX,
} ledc_mode_t;
typedef enum {
LEDC_INTR_DISABLE = 0, /*Disable LEDC interrupt */
LEDC_INTR_FADE_END, /*Enable LEDC interrupt */
} ledc_intr_type_t;
typedef enum {
LEDC_DUTY_DIR_DECREASE = 0, /*LEDC duty decrease direction */
LEDC_DUTY_DIR_INCREASE = 1, /*LEDC duty increase direction */
} ledc_duty_direction_t;
typedef enum {
LEDC_REF_TICK = 0, /*LEDC timer clock divided from reference tick(1Mhz) */
LEDC_APB_CLK, /*LEDC timer clock divided from APB clock(80Mhz)*/
} ledc_clk_src_t;
typedef enum {
LEDC_TIMER_0 = 0, /*LEDC source timer TIMER0 */
LEDC_TIMER_1, /*LEDC source timer TIMER1 */
LEDC_TIMER_2, /*LEDC source timer TIMER2 */
LEDC_TIMER_3, /*LEDC source timer TIMER3 */
} ledc_timer_t;
typedef enum {
LEDC_CHANNEL_0 = 0, /*LEDC channel 0 */
LEDC_CHANNEL_1, /*LEDC channel 1 */
LEDC_CHANNEL_2, /*LEDC channel 2 */
LEDC_CHANNEL_3, /*LEDC channel 3 */
LEDC_CHANNEL_4, /*LEDC channel 4 */
LEDC_CHANNEL_5, /*LEDC channel 5 */
LEDC_CHANNEL_6, /*LEDC channel 6 */
LEDC_CHANNEL_7, /*LEDC channel 7 */
} ledc_channel_t;
typedef enum {
LEDC_TIMER_10_BIT = 10, /*LEDC PWM depth 10Bit */
LEDC_TIMER_11_BIT = 11, /*LEDC PWM depth 11Bit */
LEDC_TIMER_12_BIT = 12, /*LEDC PWM depth 12Bit */
LEDC_TIMER_13_BIT = 13, /*LEDC PWM depth 13Bit */
LEDC_TIMER_14_BIT = 14, /*LEDC PWM depth 14Bit */
LEDC_TIMER_15_BIT = 15, /*LEDC PWM depth 15Bit */
} ledc_timer_bit_t;
typedef struct {
int gpio_num; /*the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16*/
ledc_mode_t speed_mode; /*LEDC speed speed_mode, high-speed mode or low-speed mode*/
ledc_channel_t channel; /*LEDC channel(0 - 7)*/
ledc_intr_type_t intr_type; /*configure interrupt, Fade interrupt enable or Fade interrupt disable*/
ledc_timer_t timer_sel; /*Select the timer source of channel (0 - 3)*/
uint32_t duty; /*LEDC channel duty, the duty range is [0, (2**bit_num) - 1], */
} ledc_channel_config_t;
typedef struct {
ledc_mode_t speed_mode; /*LEDC speed speed_mode, high-speed mode or low-speed mode*/
ledc_timer_bit_t bit_num; /*LEDC channel duty depth*/
ledc_timer_t timer_num; /*The timer source of channel (0 - 3)*/
uint32_t freq_hz; /*LEDC timer frequency(Hz)*/
} ledc_timer_config_t;
/**
* @brief LEDC channel configuration
*
* User this Function, configure LEDC channel with the given channel/output gpio_num/interrupt/source timer/frequency(Hz)/LEDC depth
*
* @param[in] ledc_channel_config_t
* ledc_channel_config_t.speed_mode : LEDC speed speed_mode
* ledc_channel_config_t.gpio_num : LEDC output gpio_num, if you want to use gpio16, ledc_channel_config_t.gpio_num = 16
* ledc_channel_config_t.channel : LEDC channel(0 - 7)
* ledc_channel_config_t.intr_type : configure interrupt, Fade interrupt enable or Fade interrupt disable
* ledc_channel_config_t.timer_sel : Select the timer source of channel (0 - 3), high speed channel must bind with high speed timer.
* ledc_channel_config_t.duty : LEDC channel duty, the duty range is [0, (2**timer_bit_num) - 1],
* @return ESP_OK: success
* ESP_ERR_INVALID_ARG: parameter error
*
*/
esp_err_t ledc_channel_config(ledc_channel_config_t* ledc_conf);
/**
* @brief LEDC timer configuration
*
* User this Function, configure LEDC timer with the given source timer/frequency(Hz)/bit_num
*
* @param[in] ledc_timer_config_t
* ledc_timer_config_t.speed_mode : LEDC speed speed_mode
* ledc_timer_config_t.timer_num : Select the timer source of channel (0 - 3)
* ledc_timer_config_t.freq_hz : LEDC channel frequency(Hz),
* ledc_timer_config_t.bit_num : LEDC channel duty depth
* @return ESP_OK: success
* ESP_ERR_INVALID_ARG: parameter error
* ESP_FAIL: Can not find a proper pre-divider number base on the given frequency and the current bit_num.
*
*/
esp_err_t ledc_timer_config(ledc_timer_config_t* timer_conf);
/**
* @brief LEDC update channel parameters
*
* Call this function to activate the LEDC updated parameters.
* After ledc_set_duty, ledc_set_fade, we need to call this function to update the settings.
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] channel : LEDC channel(0-7), select from ledc_channel_t
*
* @return ESP_OK: success
* ESP_ERR_INVALID_ARG: parameter error
*
*/
esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel);
/**
* @brief LEDC stop
*
* Disable LEDC output, and set idle level
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] channel : LEDC channel(0-7), select from ledc_channel_t
*
* @return ESP_OK: success
* ESP_ERR_INVALID_ARG: parameter error
*/
esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level);
/**
* @brief LEDC set channel frequency(Hz)
*
* Set LEDC frequency(Hz)
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] timer_num : LEDC timer index(0-3), select from ledc_timer_t
*
* @param[in] freq_hz : set the LEDC frequency
*
* @return ESP_OK: success
* ESP_ERR_INVALID_ARG: parameter error
* ESP_FAIL: Can not find a proper pre-divider number base on the given frequency and the current bit_num.
*/
esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t freq_hz);
/**
* @brief LEDC get channel frequency(Hz)
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] timer_num : LEDC timer index(0-3), select from ledc_timer_t
*
* @return 0 : error
* others : current LEDC frequency
*
*/
uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num);
/**
* @brief LEDC set duty
*
* Set LEDC duty, After the function calls the ledc_update_duty function, the function can take effect.
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] channel : LEDC channel(0-7), select from ledc_channel_t
*
* @param[in] duty : set the LEDC duty, the duty range is [0, (2**bit_num) - 1]
*
* @return ESP_OK: success
* ESP_ERR_INVALID_ARG: parameter error
*/
esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty);
/**
* @brief LEDC get duty
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] channel : LEDC channel(0-7), select from ledc_channel_t
*
*
* @return -1: parameter error
* other value: current LEDC duty
*
*/
int ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel);
/**
* @brief LEDC set gradient
*
* Set LEDC gradient, After the function calls the ledc_update_duty function, the function can take effect.
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] channel : LEDC channel(0-7), select from ledc_channel_t
*
* @param[in] duty : set the start of the gradient duty, the duty range is [0, (2**bit_num) - 1]
*
* @param[in] gradule_direction : set the direction of the gradient
*
* @param[in] step_num : set the number of the gradient
*
* @param[in] duty_cyle_num : set how many LEDC tick each time the gradient lasts
*
* @param[in] duty_scale : set gradient change amplitude
*
* @return ESP_OK : success
* ESP_ERR_INVALID_ARG : parameter error
*/
esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, ledc_duty_direction_t gradule_direction,
uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale);
/**
* @brief register LEDC interrupt handler, the handler is an ISR.
* The handler will be attached to the same CPU core that this function is running on.
* Users should know that which CPU is running and then pick a INUM that is not used by system.
* We can find the information of INUM and interrupt level in soc.h.
* TODO: to move INUM options to menu_config
* @param[in] uint32_t ledc_intr_num : LEDC interrupt number, check the info in soc.h, and please see the core-isa.h for more details
* @param[in] void (* fn)(void* ) : interrupt handler function.
* Note that the handler function MUST be defined with attribution of "IRAM_ATTR".
* @param[in] void * arg : parameter for handler function
*
* @return ESP_OK : success ;
* ESP_ERR_INVALID_ARG : function ptr error.
*/
esp_err_t ledc_isr_register(uint32_t ledc_intr_num, void (*fn)(void*), void * arg);
/**
* @brief configure LEDC settings
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] timer_sel : timer index(0-3), there are 4 timers in LEDC module
*
* @param[in] div_num : timer clock divide number, the timer clock is divided from the selected clock source
*
* @param[in] bit_num : the count number of one period, counter range is 0 ~ ((2 ** bit_num) - 1)
*
* @param[in] clk_src : select LEDC source clock.
*
* @return -1: parameter error
* other value: current LEDC duty
*
*/
esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t div_num, uint32_t bit_num, ledc_clk_src_t clk_src);
/**
* @brief reset LEDC timer
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t
*
*
* @return ESP_ERR_INVALID_ARG: parameter error
* ESP_OK: success
*
*/
esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel);
/**
* @brief pause LEDC timer counter
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t
*
*
* @return ESP_ERR_INVALID_ARG: parameter error
* ESP_OK: success
*
*/
esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, uint32_t timer_sel);
/**
* @brief pause LEDC timer resume
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t
*
*
* @return ESP_ERR_INVALID_ARG: parameter error
* ESP_OK: success
*
*/
esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, uint32_t timer_sel);
/**
* @brief bind LEDC channel with the selected timer
*
* @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version
*
* @param[in] channel : LEDC channel index(0-7), select from ledc_channel_t
*
* @param[in] timer_idx : LEDC timer index(0-3), select from ledc_timer_t
*
*
* @return ESP_ERR_INVALID_ARG: parameter error
* ESP_OK: success
*
*/
esp_err_t ledc_bind_channel_timer(ledc_mode_t speed_mode, uint32_t channel, uint32_t timer_idx);
/***************************EXAMPLE**********************************
*
*
* ----------------EXAMPLE OF LEDC SETTING ---------------------
* //1. enable LEDC
* periph_module_enable(PERIPH_LEDC_MODULE); //enable LEDC module, or you can not set any register of it.
*
* //2. set LEDC timer
* ledc_timer_config_t timer_conf = {
* .bit_num = LEDC_TIMER_12_BIT, //set timer counter bit number
* .freq_hz = 1000, //set frequency of pwm, here, 1000Hz
* .speed_mode = LEDC_HIGH_SPEED_MODE //timer mode,
* .timer_num = LEDC_TIMER_0, //timer number
* };
* ledc_timer_config(&timer_conf); //setup timer.
*
* //3. set LEDC channel
* ledc_channel_config_t ledc_conf = {
* .channel = LEDC_CHANNEL_0; //set LEDC channel 0
* .duty = 1000; //set the duty for initialization.(duty range is 0 ~ ((2**bit_num)-1)
* .gpio_num = 16; //GPIO number
* .intr_type = LEDC_INTR_FADE_END; //GPIO INTR TYPE, as an example, we enable fade_end interrupt here.
* .speed_mode = LEDC_HIGH_SPEED_MODE; //set LEDC mode, from ledc_mode_t
* .timer_sel = LEDC_TIMER_0; //set LEDC timer source, if different channel use one timer, the frequency and bit_num of these channels should be the same
* }
* ledc_channel_config(&ledc_conf); //setup the configuration
*
* ----------------EXAMPLE OF SETTING DUTY --- -----------------
* uint32_t ledc_channel = LEDC_CHANNEL_0; //LEDC channel(0-73)
* uint32_t duty = 2000; //duty range is 0 ~ ((2**bit_num)-1)
* LEDC_set_duty(LEDC_HIGH_SPEED_MODE, ledc_channel, duty); //set speed mode, channel, and duty.
* ledc_update_duty(LEDC_HIGH_SPEED_MODE, ledc_channel); //after set duty, we need to call ledc_update_duty to update the settings.
*
*
* ----------------EXAMPLE OF LEDC INTERRUPT ------------------
* //we have fade_end interrupt and counter overflow interrupt. we just give an example of fade_end interrupt here.
* ledc_isr_register(18, ledc_isr_handler, NULL); //hook the isr handler for LEDC interrupt
* //the first parameter is INUM, you can pick one form interrupt level 1/2 which is not used by the system.
* //NOTE1:user should arrange the INUMs that used, better not to use a same INUM for different interrupt source.
* //NOTE2:do not pick the INUM that already occupied by the system.
* //NOTE3:refer to soc.h to check which INUMs that can be used.
* ----------------EXAMPLE OF INTERRUPT HANDLER ---------------
* #include "esp_attr.h"
* void IRAM_ATTR ledc_isr_handler(void* arg) //we should add 'IRAM_ATTR' attribution when we declare the isr function
* {
* uint32_t intr_st = LEDC.int_st.val; //read LEDC interrupt status.
*
* //you will find which channels have triggered fade_end interrupt here,
* //then, you can post some event to RTOS queue to process the event.
* //later we will add a queue in the driver code.
*
* LEDC.int_clr.val = intr_st; //clear LEDC interrupt status.
* }
*
*
*--------------------------END OF EXAMPLE --------------------------
*/
#ifdef __cplusplus
}
#endif
#endif /* _DRIVER_LEDC_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_PERIPH_CTRL_H_
#define _DRIVER_PERIPH_CTRL_H_
#include "esp_err.h"
#include "soc/soc.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_UART2_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_PWM0_MODULE,
PERIPH_PWM1_MODULE,
PERIPH_PWM2_MODULE,
PERIPH_PWM3_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_UHCI1_MODULE,
} periph_module_t;
/**
* @brief enable peripheral module
*
* @param[in] periph : Peripheral module name
*
*
* @return NULL
*
*/
void periph_module_enable(periph_module_t periph);
/**
* @brief disable peripheral module
*
* @param[in] periph : Peripheral module name
*
*
* @return NULL
*
*/
void periph_module_disable(periph_module_t periph);
#ifdef __cplusplus
}
#endif
#endif /* _DRIVER_PERIPH_CTRL_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include "esp_intr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "soc/gpio_sig_map.h"
#include "driver/ledc.h"
//TODO: to use APIs in esp_log.h.
#define LEDC_DBG_WARING_ENABLE (0)
#define LEDC_DBG_ERROR_ENABLE (0)
#define LEDC_INFO_ENABLE (0)
#define LEDC_DBG_ENABLE (0)
//DBG INFOR
#if LEDC_DBG_ENABLE
#define LEDC_DBG(format,...) do{\
ets_printf("[dbg][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define LEDC_DBG(...)
#endif
#if LEDC_INFO_ENABLE
#define LEDC_INFO(format,...) do{\
ets_printf("[info][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define LEDC_INFO(...)
#endif
#if LEDC_DBG_WARING_ENABLE
#define LEDC_WARING(format,...) do{\
ets_printf("[waring][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define LEDC_WARING(...)
#endif
#if LEDC_DBG_ERROR_ENABLE
#define LEDC_ERROR(format,...) do{\
ets_printf("[error][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define LEDC_ERROR(...)
#endif
static portMUX_TYPE ledc_spinlock = portMUX_INITIALIZER_UNLOCKED;
static bool ledc_is_valid_channel(uint32_t channel)
{
if(channel > LEDC_CHANNEL_7) {
LEDC_ERROR("LEDC CHANNEL ERR: %d\n",channel);
return false;
}
return true;
}
static bool ledc_is_valid_mode(uint32_t mode)
{
if(mode >= LEDC_SPEED_MODE_MAX) {
LEDC_ERROR("LEDC MODE ERR: %d\n",mode);
return false;
}
return true;
}
static bool ledc_is_valid_timer(int timer)
{
if(timer > LEDC_TIMER_3) {
LEDC_ERROR("LEDC TIMER ERR: %d\n", timer);
return false;
}
return true;
}
esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t div_num, uint32_t bit_num, ledc_clk_src_t clk_src)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_timer(timer_sel)) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
LEDC.timer_group[speed_mode].timer[timer_sel].conf.div_num = div_num;
LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = clk_src;
LEDC.timer_group[speed_mode].timer[timer_sel].conf.bit_num = bit_num;
if(speed_mode != LEDC_HIGH_SPEED_MODE) {
LEDC.timer_group[speed_mode].timer[timer_sel].conf.low_speed_update = 1;
}
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
static esp_err_t ledc_duty_config(ledc_mode_t speed_mode, uint32_t channel_num, uint32_t hpoint_val, uint32_t duty_val,
uint32_t duty_direction, uint32_t duty_num, uint32_t duty_cycle, uint32_t duty_scale)
{
portENTER_CRITICAL(&ledc_spinlock);
LEDC.channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val;
LEDC.channel_group[speed_mode].channel[channel_num].duty.duty = duty_val;
LEDC.channel_group[speed_mode].channel[channel_num].conf1.val = ((duty_direction & LEDC_DUTY_INC_HSCH0_V) << LEDC_DUTY_INC_HSCH0_S) |
((duty_num & LEDC_DUTY_NUM_HSCH0_V) << LEDC_DUTY_NUM_HSCH0_S) |
((duty_cycle & LEDC_DUTY_CYCLE_HSCH0_V) << LEDC_DUTY_CYCLE_HSCH0_S) |
((duty_scale & LEDC_DUTY_SCALE_HSCH0_V) << LEDC_DUTY_SCALE_HSCH0_S);
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
esp_err_t ledc_bind_channel_timer(ledc_mode_t speed_mode, uint32_t channel, uint32_t timer_idx)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_timer(timer_idx)) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
LEDC.channel_group[speed_mode].channel[channel].conf0.timer_sel = timer_idx;
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_timer(timer_sel)) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
LEDC.timer_group[speed_mode].timer[timer_sel].conf.rst = 1;
LEDC.timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, uint32_t timer_sel)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_timer(timer_sel)) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
LEDC.timer_group[speed_mode].timer[timer_sel].conf.pause = 1;
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, uint32_t timer_sel)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_timer(timer_sel)) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
LEDC.timer_group[speed_mode].timer[timer_sel].conf.pause = 0;
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
static esp_err_t ledc_enable_intr_type(ledc_mode_t speed_mode, uint32_t channel, ledc_intr_type_t type)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
uint32_t value;
uint32_t intr_type = type;
portENTER_CRITICAL(&ledc_spinlock);
value = LEDC.int_ena.val;
if(intr_type == LEDC_INTR_FADE_END) {
LEDC.int_ena.val = value | BIT(LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S + channel);
} else {
LEDC.int_ena.val = (value & (~(BIT(LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S + channel))));
}
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
esp_err_t ledc_isr_register(uint32_t ledc_intr_num, void (*fn)(void*), void * arg)
{
if(fn == NULL) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
ESP_INTR_DISABLE(ledc_intr_num);
intr_matrix_set(xPortGetCoreID(), ETS_LEDC_INTR_SOURCE, ledc_intr_num);
xt_set_interrupt_handler(ledc_intr_num, fn, arg);
ESP_INTR_ENABLE(ledc_intr_num);
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
esp_err_t ledc_timer_config(ledc_timer_config_t* timer_conf)
{
int freq_hz = timer_conf->freq_hz;
int bit_num = timer_conf->bit_num;
int timer_num = timer_conf->timer_num;
int speed_mode = timer_conf->speed_mode;
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(freq_hz == 0 || bit_num == 0 || bit_num > LEDC_TIMER_15_BIT) {
LEDC_ERROR("freq_hz=%u bit_num=%u\n", freq_hz, bit_num);
return ESP_ERR_INVALID_ARG;
}
if(timer_num > LEDC_TIMER_3) {
LEDC_ERROR("Time Select %u\n", timer_num);
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
uint32_t precision = (0x1 << bit_num); //2**depth
uint64_t div_param = ((uint64_t) LEDC_APB_CLK_HZ << 8) / freq_hz / precision; //8bit fragment
int timer_clk_src;
/*Fail ,because the div_num overflow or too small*/
if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) { //REF TICK
/*Selet the reference tick*/
div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision;
if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) {
LEDC_ERROR("div param err,div_param=%u\n", div_param);
ret = ESP_FAIL;
}
timer_clk_src = LEDC_REF_TICK;
} else { //APB TICK
timer_clk_src = LEDC_APB_CLK;
}
/*set timer parameters*/
/*timer settings decide the clk of counter and the period of PWM*/
ledc_timer_set(speed_mode, timer_num, div_param, bit_num, timer_clk_src);
/* reset timer.*/
ledc_timer_rst(speed_mode, timer_num);
return ret;
}
esp_err_t ledc_channel_config(ledc_channel_config_t* ledc_conf)
{
uint32_t speed_mode = ledc_conf->speed_mode;
uint32_t gpio_num = ledc_conf->gpio_num;
uint32_t ledc_channel = ledc_conf->channel;
uint32_t timer_select = ledc_conf->timer_sel;
uint32_t intr_type = ledc_conf->intr_type;
uint32_t duty = ledc_conf->duty;
if(!ledc_is_valid_channel(ledc_channel)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)) {
LEDC_ERROR("GPIO number error: IO%d\n ", gpio_num);
return ESP_ERR_INVALID_ARG;
}
if(timer_select > LEDC_TIMER_3) {
LEDC_ERROR("Time Select %u\n", timer_select);
return ESP_ERR_INVALID_ARG;
}
esp_err_t ret = ESP_OK;
/*set channel parameters*/
/* channel parameters decide how the waveform looks like in one period*/
/* set channel duty, duty range is (0 ~ ((2 ** bit_num) - 1))*/
ledc_set_duty(speed_mode, ledc_channel, duty);
/*update duty settings*/
ledc_update_duty(speed_mode, ledc_channel);
/*bind the channel with the timer*/
ledc_bind_channel_timer(speed_mode, ledc_channel, timer_select);
/*set interrupt type*/
ledc_enable_intr_type(speed_mode, ledc_channel, intr_type);
LEDC_INFO("LEDC_PWM CHANNEL %1u|GPIO %02u|Duty %04u|Time %01u\n",
ledc_channel, gpio_num, duty, timer_select
);
/*set LEDC signal in gpio matrix*/
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0);
return ret;
}
esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_channel(channel)) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
LEDC.channel_group[speed_mode].channel[channel].conf0.sig_out_en = 1;
LEDC.channel_group[speed_mode].channel[channel].conf1.duty_start = 1;
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_channel(channel)) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
LEDC.channel_group[speed_mode].channel[channel].conf0.idle_lv = idle_level & 0x1;
LEDC.channel_group[speed_mode].channel[channel].conf0.sig_out_en = 0;
LEDC.channel_group[speed_mode].channel[channel].conf1.duty_start = 0;
portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK;
}
esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, ledc_duty_direction_t fade_direction,
uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_channel(channel)) {
return ESP_ERR_INVALID_ARG;
}
if(fade_direction > LEDC_DUTY_DIR_INCREASE) {
LEDC_ERROR("Duty direction err\n");
return ESP_ERR_INVALID_ARG;
}
if(step_num > LEDC_DUTY_NUM_HSCH0_V || duty_cyle_num > LEDC_DUTY_CYCLE_HSCH0_V || duty_scale > LEDC_DUTY_SCALE_HSCH0_V) {
LEDC_ERROR("step_num=%u duty_cyle_num=%u duty_scale=%u\n", step_num, duty_cyle_num, duty_scale);
return ESP_ERR_INVALID_ARG;
}
ledc_duty_config(speed_mode,
channel, //uint32_t chan_num,
0, //uint32_t hpoint_val,
duty << 4, //uint32_t duty_val,the least 4 bits are decimal part
fade_direction, //uint32_t increase,
step_num, //uint32_t duty_num,
duty_cyle_num, //uint32_t duty_cycle,
duty_scale //uint32_t duty_scale
);
return ESP_OK;
}
esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
if(!ledc_is_valid_channel(channel)) {
return ESP_ERR_INVALID_ARG;
}
ledc_duty_config(speed_mode,
channel, //uint32_t chan_num,
0, //uint32_t hpoint_val,
duty << 4, //uint32_t duty_val,the least 4 bits are decimal part
1, //uint32_t increase,
1, //uint32_t duty_num,
1, //uint32_t duty_cycle,
0 //uint32_t duty_scale
);
return ESP_OK;
}
int ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel)
{
if(!ledc_is_valid_mode(speed_mode)) {
return -1;
}
uint32_t duty = (LEDC.channel_group[speed_mode].channel[channel].duty_rd.duty_read >> 4);
return duty;
}
esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t freq_hz)
{
if(!ledc_is_valid_mode(speed_mode)) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&ledc_spinlock);
esp_err_t ret = ESP_OK;
uint32_t div_num = 0;
uint32_t bit_num = LEDC.timer_group[speed_mode].timer[timer_num].conf.bit_num;
uint32_t timer_source_clk = LEDC.timer_group[speed_mode].timer[timer_num].conf.tick_sel;
uint32_t precision = (0x1 << bit_num);
if(timer_source_clk == LEDC_APB_CLK) {
div_num = ((uint64_t) LEDC_APB_CLK_HZ << 8) / freq_hz / precision;
} else {
div_num = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision;
}
if(div_num <= 256 || div_num > LEDC_DIV_NUM_HSTIMER0) {
LEDC_ERROR("div param err,div_param=%u\n", div_num);
ret = ESP_FAIL;
}
LEDC.timer_group[speed_mode].timer[timer_num].conf.div_num = div_num;
portEXIT_CRITICAL(&ledc_spinlock);
return ret;
}
uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num)
{
if(!ledc_is_valid_mode(speed_mode)) {
return 0;
}
portENTER_CRITICAL(&ledc_spinlock);
uint32_t freq = 0;
uint32_t timer_source_clk = LEDC.timer_group[speed_mode].timer[timer_num].conf.tick_sel;
uint32_t bit_num = LEDC.timer_group[speed_mode].timer[timer_num].conf.bit_num;
uint32_t div_num = LEDC.timer_group[speed_mode].timer[timer_num].conf.div_num;
uint32_t precision = (0x1 << bit_num);
if(timer_source_clk == LEDC_APB_CLK) {
freq = ((uint64_t) LEDC_APB_CLK_HZ << 8) / precision / div_num;
} else {
freq = ((uint64_t) LEDC_REF_CLK_HZ << 8) / precision / div_num;
}
portEXIT_CRITICAL(&ledc_spinlock);
return freq;
}

170
components/driver/periph_ctrl.c Normal file
View File

@@ -0,0 +1,170 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include "esp_intr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "soc/dport_reg.h"
#include "driver/periph_ctrl.h"
static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
void periph_module_enable(periph_module_t periph)
{
portENTER_CRITICAL(&periph_spinlock);
switch(periph) {
case PERIPH_LEDC_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
break;
case PERIPH_UART0_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
break;
case PERIPH_UART1_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
break;
case PERIPH_UART2_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
break;
case PERIPH_I2C0_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST);
break;
case PERIPH_I2C1_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT1_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST);
break;
case PERIPH_I2S0_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
break;
case PERIPH_I2S1_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST);
break;
case PERIPH_TIMG0_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST);
break;
case PERIPH_TIMG1_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST);
break;
case PERIPH_PWM0_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST);
break;
case PERIPH_PWM1_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST);
break;
case PERIPH_PWM2_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST);
break;
case PERIPH_PWM3_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST);
break;
case PERIPH_UHCI0_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST);
break;
case PERIPH_UHCI1_MODULE:
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST);
break;
default:
break;
}
portEXIT_CRITICAL(&periph_spinlock);
}
void periph_module_disable(periph_module_t periph)
{
portENTER_CRITICAL(&periph_spinlock);
switch(periph) {
case PERIPH_LEDC_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
break;
case PERIPH_UART0_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
break;
case PERIPH_UART1_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
break;
case PERIPH_UART2_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
break;
case PERIPH_I2C0_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST);
break;
case PERIPH_I2C1_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST);
break;
case PERIPH_I2S0_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
break;
case PERIPH_I2S1_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST);
break;
case PERIPH_TIMG0_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST);
break;
case PERIPH_TIMG1_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST);
break;
case PERIPH_PWM0_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST);
break;
case PERIPH_PWM1_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST);
break;
case PERIPH_PWM2_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST);
break;
case PERIPH_PWM3_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST);
break;
case PERIPH_UHCI0_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST);
break;
case PERIPH_UHCI1_MODULE:
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN);
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST);
break;
default:
break;
}
portEXIT_CRITICAL(&periph_spinlock);
}

153
components/esp32/Kconfig
View File

@@ -1,52 +1,143 @@
menu "ESP32-specific config"
config WIFI_ENABLED
bool "Enable low-level WiFi stack"
choice ESP32_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP32_DEFAULT_CPU_FREQ_240
help
CPU frequency to be set on application startup.
config ESP32_DEFAULT_CPU_FREQ_80
bool "80 MHz"
config ESP32_DEFAULT_CPU_FREQ_160
bool "160 MHz"
config ESP32_DEFAULT_CPU_FREQ_240
bool "240 MHz"
endchoice
config ESP32_DEFAULT_CPU_FREQ_MHZ
int
default 80 if ESP32_DEFAULT_CPU_FREQ_80
default 160 if ESP32_DEFAULT_CPU_FREQ_160
default 240 if ESP32_DEFAULT_CPU_FREQ_240
choice ESP32_WIFI_OR_BT
prompt "Select stack to enable (WiFi or BT)"
default ESP32_ENABLE_WIFI
help
Temporarily, WiFi and BT stacks can not be used at the same time.
Select which stack to enable.
config ESP32_ENABLE_STACK_WIFI
bool "WiFi"
select WIFI_ENABLED if ESP32_ENABLE_STACK_WIFI
config ESP32_ENABLE_STACK_BT
bool "BT"
select MEMMAP_BT if ESP32_ENABLE_STACK_BT
select BT_ENABLED if ESP32_ENABLE_STACK_BT
config ESP32_ENABLE_STACK_NONE
bool "None"
endchoice
config MEMMAP_BT
bool
depends on ESP32_ENABLE_STACK_BT
help
The Bluetooth stack uses memory that cannot be used as generic memory anymore. This
reserves the space for that within the memory map of the compiled binary.
This option is required to enable BT stack.
Temporarily, this option is not compatible with WiFi stack.
config MEMMAP_SMP
bool "Reserve memory for two cores"
default "y"
help
The ESP32 contains two cores. If you plan to only use one, you can disable this item
to save some memory. (ToDo: Make this automatically depend on unicore support)
config MEMMAP_TRACEMEM
bool "Use TRAX tracing feature"
default "n"
help
The ESP32 contains a feature which allows you to trace the execution path the processor
has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
of memory that can't be used for general purposes anymore. Disable this if you do not know
what this is.
# Memory to reverse for trace, used in linker script
config TRACEMEM_RESERVE_DRAM
hex
default 0x8000 if MEMMAP_TRACEMEM
default 0x0
config MEMMAP_SPISRAM
bool "Use external SPI SRAM chip as main memory"
default "n"
help
The ESP32 can control an external SPI SRAM chip, adding the memory it contains to the
main memory map. Enable this if you have this hardware and want to use it in the same
way as on-chip RAM.
config WIFI_ENABLED
bool
default "y"
depends on ESP32_ENABLE_STACK_WIFI
help
This compiles in the low-level WiFi stack.
Temporarily, this option requires that FreeRTOS runs in single core mode.
config WIFI_AUTO_STARTUP
bool "Start WiFi with system startup"
default "y"
depends on WIFI_ENABLED
help
By default, WiFi is started with system startup, you can turn off this
feature and start by yourself.
config WIFI_AUTO_CONNECT
bool "Enable auto connect"
default "y"
depends on WIFI_ENABLED
help
If station is enabled, and station config is set, this will enable WiFi
station auto connect when WiFi startup.
Temporarily, this option is not compatible with BT stack.
config SYSTEM_EVENT_QUEUE_SIZE
int "system event queue size"
int "System event queue size"
default 32
depends on WIFI_ENABLED
help
Config system event queue size in different application.
config SYSTEM_EVENT_TASK_STACK_SIZE
int "system event task stack size"
int "Event loop task stack size"
default 2048
depends on WIFI_ENABLED
help
Config system event task stack size in different application.
config MAIN_TASK_STACK_SIZE
int "Main task stack size"
default 4096
help
Config system event task stack size in different application.
config NEWLIB_STDOUT_ADDCR
bool "Standard-out output adds carriage return before newline"
default y
help
Most people are used to end their printf strings with a newline. If this
is sent as is to the serial port, most terminal programs will only move the
cursor one line down, not also move it to the beginning of the line. This
is usually done by an added CR character. Enabling this will make the
standard output code automatically add a CR character before a LF.
bool "Standard-out output adds carriage return before newline"
default y
help
Most people are used to end their printf strings with a newline. If this
is sent as is to the serial port, most terminal programs will only move the
cursor one line down, not also move it to the beginning of the line. This
is usually done by an added CR character. Enabling this will make the
standard output code automatically add a CR character before a LF.
config ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default "n"
help
Set to 'y' if you plan to load a firmware for the coprocessor.
If this option is enabled, further coprocessor configuration will appear in the Components menu.
config ULP_COPROC_RESERVE_MEM
int "RTC slow memory reserved for coprocessor"
default 512
range 32 8192
depends on ULP_COPROC_ENABLED
help
Bytes of memory to reserve for ULP coprocessor firmware & data.
Data is reserved at the beginning of RTC slow memory.
# Set CONFIG_ULP_COPROC_RESERVE_MEM to 0 if ULP is disabled
config ULP_COPROC_RESERVE_MEM
int
default 0
depends on !ULP_COPROC_ENABLED
endmenu

31
components/esp32/component.mk
View File

@@ -10,23 +10,9 @@
COMPONENT_SRCDIRS := . hwcrypto
LIBS := crypto core net80211 phy rtc pp wpa wps
LIBS := crypto core net80211 phy rtc pp wpa smartconfig
ifeq ($(CONFIG_MEMMAP_BT),y)
ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
LINKER_SCRIPTS = -T esp32.bt.trace.ld
else
LINKER_SCRIPTS = -T esp32.bt.ld
endif
else
ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
LINKER_SCRIPTS = -T esp32.trace.ld
else
LINKER_SCRIPTS = -T esp32.ld
endif
endif
LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld
LINKER_SCRIPTS += -T esp32_out.ld -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld
COMPONENT_ADD_LDFLAGS := -lesp32 \
$(abspath libhal.a) \
@@ -41,7 +27,7 @@ ALL_LIB_FILES := $(patsubst %,$(COMPONENT_PATH)/lib/lib%.a,$(LIBS))
# automatically trigger a git submodule update
# if any libraries are missing
$(eval $(call SubmoduleRequiredForFiles,$(ALL_LIB_FILES)))
$(eval $(call SubmoduleCheck,$(ALL_LIB_FILES),$(COMPONENT_PATH)/lib))
# this is a hack to make sure the app is re-linked if the binary
# libraries change or are updated. If they change, the main esp32
@@ -51,3 +37,14 @@ $(eval $(call SubmoduleRequiredForFiles,$(ALL_LIB_FILES)))
# It would be better for components to be able to expose any of these
# non-standard dependencies via get_variable, but this will do for now.
$(COMPONENT_LIBRARY): $(ALL_LIB_FILES)
# Preprocess esp32.ld linker script into esp32_out.ld
#
# The library doesn't really depend on esp32_out.ld, but it
# saves us from having to add the target to a Makefile.projbuild
$(COMPONENT_LIBRARY): esp32_out.ld
esp32_out.ld: $(COMPONENT_PATH)/ld/esp32.ld ../include/sdkconfig.h
$(CC) -I ../include -C -P -x c -E $< -o $@
COMPONENT_EXTRA_CLEAN := esp32_out.ld

79
components/esp32/cpu_freq.c Normal file
View File

@@ -0,0 +1,79 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include "rom/ets_sys.h"
#include "rom/uart.h"
#include "sdkconfig.h"
typedef enum{
XTAL_40M = 40,
XTAL_26M = 26,
XTAL_24M = 24,
XTAL_AUTO = 0
} xtal_freq_t;
typedef enum{
CPU_80M = 1,
CPU_160M = 2,
CPU_240M = 3,
} cpu_freq_t;
extern void phy_get_romfunc_addr();
// TODO: these functions need to be moved from librtc to ESP-IDF
extern void rtc_init_lite();
extern void rtc_set_cpu_freq(xtal_freq_t xtal_freq, cpu_freq_t cpu_freq);
/*
* This function is not exposed as an API at this point,
* because FreeRTOS doesn't yet support dynamic changing of
* CPU frequency. Also we need to implement hooks for
* components which want to be notified of CPU frequency
* changes.
*/
void esp_set_cpu_freq(void)
{
uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
phy_get_romfunc_addr();
// freq will be changed to 40MHz in rtc_init_lite,
// wait uart tx finish, otherwise some uart output will be lost
uart_tx_wait_idle(0);
rtc_init_lite();
cpu_freq_t freq = CPU_80M;
switch(freq_mhz) {
case 240:
freq = CPU_240M;
break;
case 160:
freq = CPU_160M;
break;
default:
freq_mhz = 80;
/* no break */
case 80:
freq = CPU_80M;
break;
}
// freq will be changed to freq in rtc_set_cpu_freq,
// wait uart tx finish, otherwise some uart output will be lost
uart_tx_wait_idle(0);
rtc_set_cpu_freq(XTAL_AUTO, freq);
ets_update_cpu_frequency(freq_mhz);
}

288
components/esp32/cpu_start.c
View File

@@ -20,8 +20,10 @@
#include "rom/ets_sys.h"
#include "rom/uart.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
@@ -39,194 +41,132 @@
#include "esp_event.h"
#include "esp_spi_flash.h"
#include "esp_ipc.h"
#include "esp_log.h"
static void IRAM_ATTR user_start_cpu0(void);
static void IRAM_ATTR call_user_start_cpu1();
static void IRAM_ATTR user_start_cpu1(void);
void Cache_Read_Enable();
void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default")));
void start_cpu0_default(void) IRAM_ATTR;
#if !CONFIG_FREERTOS_UNICORE
static void IRAM_ATTR call_start_cpu1();
void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default")));
void start_cpu1_default(void) IRAM_ATTR;
static bool app_cpu_started = false;
#endif //!CONFIG_FREERTOS_UNICORE
static void do_global_ctors(void);
static void main_task(void* args);
extern void ets_setup_syscalls(void);
extern void app_main(void);
extern int __cpu1_entry_point;
extern int _bss_start;
extern int _bss_end;
extern int _init_start;
extern int _init_end;
extern int _iram_romjumptable_start;
extern int _iram_romjumptable_end;
extern int _iram_text_start;
extern int _iram_text_end;
/*
We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
*/
static bool app_cpu_started = false;
void IRAM_ATTR call_user_start_cpu0() {
//Kill wdt
REG_CLR_BIT(0x3ff4808c, BIT(10)); //RTCCNTL+8C RTC_WDTCONFIG0 RTC_
REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48
//Move exception vectors to IRAM
asm volatile (\
"wsr %0, vecbase\n" \
::"r"(&_init_start));
uartAttach();
ets_install_uart_printf();
//Make page 0 access raise an exception
//Also some other unused pages so we can catch weirdness
//ToDo: this but nicer.
asm volatile (\
"movi a4,0x00000000\n" \
"movi a5,0xf\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x80000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xa0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xc0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xe0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x20000000\n" \
"movi a5,0x0\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x40000000\n" \
"movi a5,0x2\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"isync\n" \
:::"a4","a5");
memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
//Initialize heap allocator
heap_alloc_caps_init();
ets_printf("Pro cpu up.\n");
#ifndef CONFIG_FREERTOS_UNICORE
ets_printf("Starting app cpu, entry point is %p\n", call_user_start_cpu1);
SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1);
while (!app_cpu_started) {
ets_delay_us(100);
}
#else
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
#endif
ets_printf("Pro cpu start user code\n");
user_start_cpu0();
}
extern int _init_start;
void IRAM_ATTR call_user_start_cpu1() {
asm volatile (\
"wsr %0, vecbase\n" \
::"r"(&_init_start));
//Make page 0 access raise an exception
//Also some other unused pages so we can catch weirdness
//ToDo: this but nicer.
asm volatile (\
"movi a4,0x00000000\n" \
"movi a5,0xf\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x80000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xa0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xc0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0xe0000000\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x20000000\n" \
"movi a5,0x0\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"movi a4,0x40000000\n" \
"movi a5,0x2\n" \
"wdtlb a5,a4\n" \
"witlb a5,a4\n" \
"isync\n" \
:::"a4","a5");
ets_printf("App cpu up.\n");
app_cpu_started = 1;
user_start_cpu1();
}
extern volatile int port_xSchedulerRunning[2];
void IRAM_ATTR user_start_cpu1(void) {
// Wait for FreeRTOS initialization to finish on PRO CPU
while (port_xSchedulerRunning[0] == 0) {
;
}
ets_printf("Starting scheduler on APP CPU.\n");
xPortStartScheduler();
}
extern void (*__init_array_start)(void);
extern void (*__init_array_end)(void);
extern volatile int port_xSchedulerRunning[2];
static void do_global_ctors(void) {
void (**p)(void);
for(p = &__init_array_start; p != &__init_array_end; ++p)
(*p)();
}
static const char* TAG = "cpu_start";
extern esp_err_t app_main(void *ctx);
/*
* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
*/
void user_start_cpu0(void) {
ets_setup_syscalls();
do_global_ctors();
esp_ipc_init();
spi_flash_init();
void IRAM_ATTR call_start_cpu0()
{
//Kill wdt
REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48
#if CONFIG_WIFI_ENABLED
esp_err_t ret = nvs_flash_init(5, 3);
if (ret != ESP_OK) {
printf("nvs_flash_init failed, ret=%d\n", ret);
cpu_configure_region_protection();
//Move exception vectors to IRAM
asm volatile (\
"wsr %0, vecbase\n" \
::"r"(&_init_start));
uartAttach();
ets_install_uart_printf();
memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
// Initialize heap allocator
heap_alloc_caps_init();
ESP_EARLY_LOGI(TAG, "Pro cpu up.");
#if !CONFIG_FREERTOS_UNICORE
ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
while (!app_cpu_started) {
ets_delay_us(100);
}
system_init();
esp_event_init(NULL, NULL);
tcpip_adapter_init();
#endif
#if CONFIG_WIFI_ENABLED && CONFIG_WIFI_AUTO_STARTUP
#include "esp_wifi.h"
esp_wifi_startup(app_main, NULL);
#else
app_main(NULL);
ESP_EARLY_LOGI(TAG, "Single core mode");
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
#endif
ets_printf("Starting scheduler on PRO CPU.\n");
vTaskStartScheduler();
ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
start_cpu0();
}
#if !CONFIG_FREERTOS_UNICORE
void IRAM_ATTR call_start_cpu1()
{
asm volatile (\
"wsr %0, vecbase\n" \
::"r"(&_init_start));
cpu_configure_region_protection();
ESP_EARLY_LOGI(TAG, "App cpu up.");
app_cpu_started = 1;
start_cpu1();
}
#endif //!CONFIG_FREERTOS_UNICORE
void start_cpu0_default(void)
{
esp_set_cpu_freq(); // set CPU frequency configured in menuconfig
uart_div_modify(0, (APB_CLK_FREQ << 4) / 115200);
ets_setup_syscalls();
do_global_ctors();
esp_ipc_init();
spi_flash_init();
xTaskCreatePinnedToCore(&main_task, "main",
ESP_TASK_MAIN_STACK, NULL,
ESP_TASK_MAIN_PRIO, NULL, 0);
ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
vTaskStartScheduler();
}
#if !CONFIG_FREERTOS_UNICORE
void start_cpu1_default(void)
{
// Wait for FreeRTOS initialization to finish on PRO CPU
while (port_xSchedulerRunning[0] == 0) {
;
}
ESP_LOGI(TAG, "Starting scheduler on APP CPU.");
xPortStartScheduler();
}
#endif //!CONFIG_FREERTOS_UNICORE
static void do_global_ctors(void)
{
void (**p)(void);
for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
(*p)();
}
}
static void main_task(void* args)
{
app_main();
vTaskDelete(NULL);
}

49
components/esp32/deepsleep.c Normal file
View File

@@ -0,0 +1,49 @@
/* Wake from deep sleep stub
See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
*/
#include <stddef.h>
#include <sys/lock.h>
#include "rom/cache.h"
#include "rom/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/dport_reg.h"
#include "esp_attr.h"
#include "esp_deepsleep.h"
/* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc()
is not thread-safe. */
static _lock_t lock_rtc_memory_crc;
esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
{
_lock_acquire(&lock_rtc_memory_crc);
uint32_t stored_crc = REG_READ(RTC_MEMORY_CRC_REG);
set_rtc_memory_crc();
uint32_t calc_crc = REG_READ(RTC_MEMORY_CRC_REG);
REG_WRITE(RTC_MEMORY_CRC_REG, stored_crc);
_lock_release(&lock_rtc_memory_crc);
if(stored_crc == calc_crc) {
return (esp_deep_sleep_wake_stub_fn_t)REG_READ(RTC_ENTRY_ADDR_REG);
} else {
return NULL;
}
}
void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
{
_lock_acquire(&lock_rtc_memory_crc);
REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
set_rtc_memory_crc();
_lock_release(&lock_rtc_memory_crc);
}
void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) {
//
//mmu_init(0);
REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR);
REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR);
}
void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);

162
components/esp32/event.c → components/esp32/event_default_handlers.c
View File

@@ -19,6 +19,7 @@
#include "esp_err.h"
#include "esp_wifi.h"
#include "esp_event.h"
#include "esp_event_loop.h"
#include "esp_task.h"
#include "freertos/FreeRTOS.h"
@@ -27,22 +28,15 @@
#include "freertos/semphr.h"
#include "tcpip_adapter.h"
#include "esp_log.h"
#define ESP32_WORKAROUND 1
const char* TAG = "event";
#if CONFIG_WIFI_ENABLED
static bool event_init_flag = false;
static xQueueHandle g_event_handler = NULL;
static system_event_cb_t g_event_handler_cb;
static void *g_event_ctx;
#define WIFI_DEBUG(...)
#define WIFI_API_CALL_CHECK(info, api_call, ret) \
do{\
esp_err_t __err = (api_call);\
if ((ret) != __err) {\
WIFI_DEBUG("%s %d %s ret=%d\n", __FUNCTION__, __LINE__, (info), __err);\
ESP_LOGE(TAG, "%s %d %s ret=%d", __FUNCTION__, __LINE__, (info), __err);\
return __err;\
}\
} while(0)
@@ -71,7 +65,7 @@ static system_event_handle_t g_system_event_handle_table[] = {
{SYSTEM_EVENT_STA_CONNECTED, system_event_sta_connected_handle_default},
{SYSTEM_EVENT_STA_DISCONNECTED, system_event_sta_disconnected_handle_default},
{SYSTEM_EVENT_STA_AUTHMODE_CHANGE, NULL},
{SYSTEM_EVENT_STA_GOT_IP, system_event_sta_got_ip_default},
{SYSTEM_EVENT_STA_GOT_IP, system_event_sta_got_ip_default},
{SYSTEM_EVENT_AP_START, system_event_ap_start_handle_default},
{SYSTEM_EVENT_AP_STOP, system_event_ap_stop_handle_default},
{SYSTEM_EVENT_AP_STACONNECTED, NULL},
@@ -85,7 +79,7 @@ static esp_err_t system_event_sta_got_ip_default(system_event_t *event)
extern esp_err_t esp_wifi_set_sta_ip(void);
WIFI_API_CALL_CHECK("esp_wifi_set_sta_ip", esp_wifi_set_sta_ip(), ESP_OK);
printf("ip: " IPSTR ", mask: " IPSTR ", gw: " IPSTR "\n",
ESP_LOGI(TAG, "ip: " IPSTR ", mask: " IPSTR ", gw: " IPSTR,
IP2STR(&event->event_info.got_ip.ip_info.ip),
IP2STR(&event->event_info.got_ip.ip_info.netmask),
IP2STR(&event->event_info.got_ip.ip_info.gw));
@@ -161,7 +155,7 @@ esp_err_t system_event_sta_connected_handle_default(system_event_t *event)
esp_event_send(&evt);
} else {
WIFI_DEBUG("invalid static ip\n");
ESP_LOGE(TAG, "invalid static ip");
}
}
@@ -175,104 +169,89 @@ esp_err_t system_event_sta_disconnected_handle_default(system_event_t *event)
return ESP_OK;
}
static esp_err_t esp_wifi_post_event_to_user(system_event_t *event)
{
if (g_event_handler_cb) {
return (*g_event_handler_cb)(g_event_ctx, event);
}
return ESP_OK;
}
static esp_err_t esp_system_event_debug(system_event_t *event)
{
if (event == NULL) {
printf("Error: event is null!\n");
ESP_LOGE(TAG, "event is null!");
return ESP_FAIL;
}
WIFI_DEBUG("received event: ");
switch (event->event_id) {
case SYSTEM_EVENT_WIFI_READY: {
WIFI_DEBUG("SYSTEM_EVENT_WIFI_READY\n");
ESP_LOGD(TAG, "SYSTEM_EVENT_WIFI_READY");
break;
}
case SYSTEM_EVENT_SCAN_DONE: {
system_event_sta_scan_done_t *scan_done;
scan_done = &event->event_info.scan_done;
WIFI_DEBUG("SYSTEM_EVENT_SCAN_DONE\nstatus:%d, number:%d\n", scan_done->status, scan_done->number);
system_event_sta_scan_done_t *scan_done = &event->event_info.scan_done;
ESP_LOGD(TAG, "SYSTEM_EVENT_SCAN_DONE, status:%d, number:%d", scan_done->status, scan_done->number);
break;
}
case SYSTEM_EVENT_STA_START: {
WIFI_DEBUG("SYSTEM_EVENT_STA_START\n");
ESP_LOGD(TAG, "SYSTEM_EVENT_STA_START");
break;
}
case SYSTEM_EVENT_STA_STOP: {
WIFI_DEBUG("SYSTEM_EVENT_STA_STOP\n");
ESP_LOGD(TAG, "SYSTEM_EVENT_STA_STOP");
break;
}
case SYSTEM_EVENT_STA_CONNECTED: {
system_event_sta_connected_t *connected;
connected = &event->event_info.connected;
WIFI_DEBUG("SYSTEM_EVENT_STA_CONNECTED\nssid:%s, ssid_len:%d, bssid:%02x:%02x:%02x:%02x:%02x:%02x, channel:%d, authmode:%d\n", \
system_event_sta_connected_t *connected = &event->event_info.connected;
ESP_LOGD(TAG, "SYSTEM_EVENT_STA_CONNECTED, ssid:%s, ssid_len:%d, bssid:%02x:%02x:%02x:%02x:%02x:%02x, channel:%d, authmode:%d", \
connected->ssid, connected->ssid_len, connected->bssid[0], connected->bssid[0], connected->bssid[1], \
connected->bssid[3], connected->bssid[4], connected->bssid[5], connected->channel, connected->authmode);
break;
}
case SYSTEM_EVENT_STA_DISCONNECTED: {
system_event_sta_disconnected_t *disconnected;
disconnected = &event->event_info.disconnected;
WIFI_DEBUG("SYSTEM_EVENT_STA_DISCONNECTED\nssid:%s, ssid_len:%d, bssid:%02x:%02x:%02x:%02x:%02x:%02x, reason:%d\n", \
system_event_sta_disconnected_t *disconnected = &event->event_info.disconnected;
ESP_LOGD(TAG, "SYSTEM_EVENT_STA_DISCONNECTED, ssid:%s, ssid_len:%d, bssid:%02x:%02x:%02x:%02x:%02x:%02x, reason:%d", \
disconnected->ssid, disconnected->ssid_len, disconnected->bssid[0], disconnected->bssid[0], disconnected->bssid[1], \
disconnected->bssid[3], disconnected->bssid[4], disconnected->bssid[5], disconnected->reason);
break;
}
case SYSTEM_EVENT_STA_AUTHMODE_CHANGE: {
system_event_sta_authmode_change_t *auth_change;
auth_change = &event->event_info.auth_change;
WIFI_DEBUG("SYSTEM_EVENT_STA_AUTHMODE_CHNAGE\nold_mode:%d, new_mode:%d\n", auth_change->old_mode, auth_change->new_mode);
system_event_sta_authmode_change_t *auth_change = &event->event_info.auth_change;
ESP_LOGD(TAG, "SYSTEM_EVENT_STA_AUTHMODE_CHNAGE, old_mode:%d, new_mode:%d", auth_change->old_mode, auth_change->new_mode);
break;
}
case SYSTEM_EVENT_STA_GOT_IP: {
system_event_sta_got_ip_t *got_ip;
got_ip = &event->event_info.got_ip;
WIFI_DEBUG("SYSTEM_EVENT_STA_GOTIP\n");
system_event_sta_got_ip_t *got_ip = &event->event_info.got_ip;
ESP_LOGD(TAG, "SYSTEM_EVENT_STA_GOTIP, ip:" IPSTR ", mask:" IPSTR ", gw:" IPSTR,
IP2STR(&got_ip->ip_info.ip),
IP2STR(&got_ip->ip_info.netmask),
IP2STR(&got_ip->ip_info.gw));
break;
}
case SYSTEM_EVENT_AP_START: {
WIFI_DEBUG("SYSTEM_EVENT_AP_START\n");
ESP_LOGD(TAG, "SYSTEM_EVENT_AP_START");
break;
}
case SYSTEM_EVENT_AP_STOP: {
WIFI_DEBUG("SYSTEM_EVENT_AP_STOP\n");
ESP_LOGD(TAG, "SYSTEM_EVENT_AP_STOP");
break;
}
case SYSTEM_EVENT_AP_STACONNECTED: {
system_event_ap_staconnected_t *staconnected;
staconnected = &event->event_info.sta_connected;
WIFI_DEBUG("SYSTEM_EVENT_AP_STACONNECTED\nmac:%02x:%02x:%02x:%02x:%02x:%02x, aid:%d\n", \
system_event_ap_staconnected_t *staconnected = &event->event_info.sta_connected;
ESP_LOGD(TAG, "SYSTEM_EVENT_AP_STACONNECTED, mac:%02x:%02x:%02x:%02x:%02x:%02x, aid:%d", \
staconnected->mac[0], staconnected->mac[0], staconnected->mac[1], \
staconnected->mac[3], staconnected->mac[4], staconnected->mac[5], staconnected->aid);
break;
}
case SYSTEM_EVENT_AP_STADISCONNECTED: {
system_event_ap_stadisconnected_t *stadisconnected;
stadisconnected = &event->event_info.sta_disconnected;
WIFI_DEBUG("SYSTEM_EVENT_AP_STADISCONNECTED\nmac:%02x:%02x:%02x:%02x:%02x:%02x, aid:%d\n", \
system_event_ap_stadisconnected_t *stadisconnected = &event->event_info.sta_disconnected;
ESP_LOGD(TAG, "SYSTEM_EVENT_AP_STADISCONNECTED, mac:%02x:%02x:%02x:%02x:%02x:%02x, aid:%d", \
stadisconnected->mac[0], stadisconnected->mac[0], stadisconnected->mac[1], \
stadisconnected->mac[3], stadisconnected->mac[4], stadisconnected->mac[5], stadisconnected->aid);
break;
}
case SYSTEM_EVENT_AP_PROBEREQRECVED: {
system_event_ap_probe_req_rx_t *ap_probereqrecved;
ap_probereqrecved = &event->event_info.ap_probereqrecved;
WIFI_DEBUG("SYSTEM_EVENT_AP_PROBEREQRECVED\nrssi:%d, mac:%02x:%02x:%02x:%02x:%02x:%02x\n", \
system_event_ap_probe_req_rx_t *ap_probereqrecved = &event->event_info.ap_probereqrecved;
ESP_LOGD(TAG, "SYSTEM_EVENT_AP_PROBEREQRECVED, rssi:%d, mac:%02x:%02x:%02x:%02x:%02x:%02x", \
ap_probereqrecved->rssi, ap_probereqrecved->mac[0], ap_probereqrecved->mac[0], ap_probereqrecved->mac[1], \
ap_probereqrecved->mac[3], ap_probereqrecved->mac[4], ap_probereqrecved->mac[5]);
break;
}
default: {
printf("Error: no such kind of event!\n");
ESP_LOGW(TAG, "no such kind of event!");
break;
}
}
@@ -280,88 +259,23 @@ static esp_err_t esp_system_event_debug(system_event_t *event)
return ESP_OK;
}
static esp_err_t esp_system_event_handler(system_event_t *event)
esp_err_t esp_event_process_default(system_event_t *event)
{
if (event == NULL) {
printf("Error: event is null!\n");
ESP_LOGE(TAG, "Error: event is null!");
return ESP_FAIL;
}
esp_system_event_debug(event);
if ((event->event_id < SYSTEM_EVENT_MAX) && (event->event_id == g_system_event_handle_table[event->event_id].event_id)) {
if (g_system_event_handle_table[event->event_id].event_handle) {
WIFI_DEBUG("enter default callback\n");
ESP_LOGV(TAG, "enter default callback");
g_system_event_handle_table[event->event_id].event_handle(event);
WIFI_DEBUG("exit default callback\n");
ESP_LOGV(TAG, "exit default callback");
}
} else {
printf("mismatch or invalid event, id=%d\n", event->event_id);
}
return esp_wifi_post_event_to_user(event);
}
static void esp_system_event_task(void *pvParameters)
{
system_event_t evt;
esp_err_t ret;
while (1) {
if (xQueueReceive(g_event_handler, &evt, portMAX_DELAY) == pdPASS) {
ret = esp_system_event_handler(&evt);
if (ret == ESP_FAIL) {
printf("esp wifi post event to user fail!\n");
}
}
}
}
system_event_cb_t esp_event_set_cb(system_event_cb_t cb, void *ctx)
{
system_event_cb_t old_cb = g_event_handler_cb;
g_event_handler_cb = cb;
g_event_ctx = ctx;
return old_cb;
}
esp_err_t esp_event_send(system_event_t *event)
{
portBASE_TYPE ret;
ret = xQueueSendToBack((xQueueHandle)g_event_handler, event, 0);
if (pdPASS != ret) {
if (event) {
printf("e=%d f\n", event->event_id);
} else {
printf("e null\n");
}
ESP_LOGE(TAG, "mismatch or invalid event, id=%d", event->event_id);
return ESP_FAIL;
}
return ESP_OK;
}
void *esp_event_get_handler(void)
{
return (void *)g_event_handler;
}
esp_err_t esp_event_init(system_event_cb_t cb, void *ctx)
{
if (event_init_flag) {
return ESP_FAIL;
}
g_event_handler_cb = cb;
g_event_ctx = ctx;
g_event_handler = xQueueCreate(CONFIG_SYSTEM_EVENT_QUEUE_SIZE, sizeof(system_event_t));
xTaskCreatePinnedToCore(esp_system_event_task, "eventTask", ESP_TASKD_EVENT_STACK, NULL, ESP_TASKD_EVENT_PRIO, NULL, 0);
return ESP_OK;
}
#endif

107
components/esp32/event_loop.c Normal file
View File

@@ -0,0 +1,107 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stddef.h>
#include <stdlib.h>
#include <string.h>
#include "esp_err.h"
#include "esp_wifi.h"
#include "esp_event.h"
#include "esp_event_loop.h"
#include "esp_task.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "freertos/semphr.h"
#include "esp_log.h"
#include "sdkconfig.h"
static const char* TAG = "event";
static bool s_event_init_flag = false;
static QueueHandle_t s_event_queue = NULL;
static system_event_cb_t s_event_handler_cb = NULL;
static void *s_event_ctx = NULL;
static esp_err_t esp_event_post_to_user(system_event_t *event)
{
if (s_event_handler_cb) {
return (*s_event_handler_cb)(s_event_ctx, event);
}
return ESP_OK;
}
static void esp_event_loop_task(void *pvParameters)
{
while (1) {
system_event_t evt;
if (xQueueReceive(s_event_queue, &evt, portMAX_DELAY) == pdPASS) {
esp_err_t ret = esp_event_process_default(&evt);
if (ret != ESP_OK) {
ESP_LOGE(TAG, "default event handler failed!");
}
ret = esp_event_post_to_user(&evt);
if (ret != ESP_OK) {
ESP_LOGE(TAG, "post event to user fail!");
}
}
}
}
system_event_cb_t esp_event_loop_set_cb(system_event_cb_t cb, void *ctx)
{
system_event_cb_t old_cb = s_event_handler_cb;
s_event_handler_cb = cb;
s_event_ctx = ctx;
return old_cb;
}
esp_err_t esp_event_send(system_event_t *event)
{
portBASE_TYPE ret = xQueueSendToBack(s_event_queue, event, 0);
if (ret != pdPASS) {
if (event) {
ESP_LOGE(TAG, "e=%d f", event->event_id);
} else {
ESP_LOGE(TAG, "e null");
}
return ESP_FAIL;
}
return ESP_OK;
}
QueueHandle_t esp_event_loop_get_queue(void)
{
return s_event_queue;
}
esp_err_t esp_event_loop_init(system_event_cb_t cb, void *ctx)
{
if (s_event_init_flag) {
return ESP_FAIL;
}
s_event_handler_cb = cb;
s_event_ctx = ctx;
s_event_queue = xQueueCreate(CONFIG_SYSTEM_EVENT_QUEUE_SIZE, sizeof(system_event_t));
xTaskCreatePinnedToCore(esp_event_loop_task, "eventTask",
ESP_TASKD_EVENT_STACK, NULL, ESP_TASKD_EVENT_PRIO, NULL, 0);
s_event_init_flag = true;
return ESP_OK;
}

296
components/esp32/heap_alloc_caps.c
View File

@@ -15,8 +15,11 @@
#include <freertos/heap_regions.h>
#include "heap_alloc_caps.h"
#include "esp_heap_alloc_caps.h"
#include "spiram.h"
#include "esp_log.h"
static const char* TAG = "heap_alloc_caps";
/*
This file, combined with a region allocator that supports tags, solves the problem that the ESP32 has RAM that's
@@ -37,23 +40,23 @@ Tag descriptors. These describe the capabilities of a bit of memory that's tagge
Each tag contains NO_PRIOS entries; later entries are only taken if earlier ones can't fulfill the memory request.
*/
static const uint32_t tagDesc[][NO_PRIOS]={
{ MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT, 0 }, //Tag 0: Plain ole D-port RAM
{ 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, //Tag 1: Plain ole D-port RAM which has an alias on the I-port
{ MALLOC_CAP_EXEC|MALLOC_CAP_32BIT, 0, 0 }, //Tag 2: IRAM
{ MALLOC_CAP_PID2, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //Tag 3-8: PID 2-7 IRAM
{ MALLOC_CAP_PID3, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID4, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID5, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID6, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID7, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID2, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //Tag 9-14: PID 2-7 DRAM
{ MALLOC_CAP_PID3, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID4, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID5, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID6, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID7, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_SPISRAM, 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, //Tag 15: SPI SRAM data
{ MALLOC_CAP_INVALID, MALLOC_CAP_INVALID, MALLOC_CAP_INVALID } //End
{ MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT, 0 }, //Tag 0: Plain ole D-port RAM
{ 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, //Tag 1: Plain ole D-port RAM which has an alias on the I-port
{ MALLOC_CAP_EXEC|MALLOC_CAP_32BIT, 0, 0 }, //Tag 2: IRAM
{ MALLOC_CAP_PID2, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //Tag 3-8: PID 2-7 IRAM
{ MALLOC_CAP_PID3, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID4, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID5, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID6, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID7, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID2, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //Tag 9-14: PID 2-7 DRAM
{ MALLOC_CAP_PID3, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID4, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID5, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID6, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_PID7, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //
{ MALLOC_CAP_SPISRAM, 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, //Tag 15: SPI SRAM data
{ MALLOC_CAP_INVALID, MALLOC_CAP_INVALID, MALLOC_CAP_INVALID } //End
};
/*
@@ -76,81 +79,81 @@ be sorted from low to high start address.
This array is *NOT* const because it gets modified depending on what pools are/aren't available.
*/
static HeapRegionTagged_t regions[]={
{ (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available
{ (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT
{ (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- can be used for BT
{ (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
{ (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
{ (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
{ (uint8_t *)0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
{ (uint8_t *)0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
{ (uint8_t *)0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
{ (uint8_t *)0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
{ (uint8_t *)0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
{ (uint8_t *)0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
{ (uint8_t *)0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
{ (uint8_t *)0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
{ (uint8_t *)0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
{ (uint8_t *)0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
{ (uint8_t *)0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
{ (uint8_t *)0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
{ (uint8_t *)0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
{ (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
{ (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
{ (uint8_t *)0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
{ (uint8_t *)0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
{ (uint8_t *)0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
{ (uint8_t *)0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
{ (uint8_t *)0x40070000, 0x8000, 2, 0}, //pool 0
{ (uint8_t *)0x40078000, 0x8000, 2, 0}, //pool 1
{ (uint8_t *)0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
{ (uint8_t *)0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
{ (uint8_t *)0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
{ (uint8_t *)0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
{ (uint8_t *)0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
{ (uint8_t *)0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
{ (uint8_t *)0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
{ (uint8_t *)0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
{ (uint8_t *)0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
{ (uint8_t *)0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
{ (uint8_t *)0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
{ (uint8_t *)0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
{ (uint8_t *)0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
{ (uint8_t *)0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
{ (uint8_t *)0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
{ (uint8_t *)0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
{ NULL, 0, 0, 0} //end
{ (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available
{ (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT
{ (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- can be used for BT
{ (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
{ (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
{ (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
{ (uint8_t *)0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
{ (uint8_t *)0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
{ (uint8_t *)0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
{ (uint8_t *)0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
{ (uint8_t *)0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
{ (uint8_t *)0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
{ (uint8_t *)0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
{ (uint8_t *)0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
{ (uint8_t *)0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
{ (uint8_t *)0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
{ (uint8_t *)0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
{ (uint8_t *)0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
{ (uint8_t *)0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
{ (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
{ (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
{ (uint8_t *)0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
{ (uint8_t *)0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
{ (uint8_t *)0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
{ (uint8_t *)0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
{ (uint8_t *)0x40070000, 0x8000, 2, 0}, //pool 0
{ (uint8_t *)0x40078000, 0x8000, 2, 0}, //pool 1
{ (uint8_t *)0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
{ (uint8_t *)0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
{ (uint8_t *)0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
{ (uint8_t *)0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
{ (uint8_t *)0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
{ (uint8_t *)0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
{ (uint8_t *)0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
{ (uint8_t *)0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
{ (uint8_t *)0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
{ (uint8_t *)0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
{ (uint8_t *)0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
{ (uint8_t *)0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
{ (uint8_t *)0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
{ (uint8_t *)0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
{ (uint8_t *)0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
{ (uint8_t *)0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
{ NULL, 0, 0, 0} //end
};
//Modify regions array to disable the given range of memory.
static void disable_mem_region(void *from, void *to) {
int i;
//Align from and to on word boundaries
from=(void*)((uint32_t)from&~3);
to=(void*)(((uint32_t)to+3)&~3);
for (i=0; regions[i].xSizeInBytes!=0; i++) {
void *regStart=regions[i].pucStartAddress;
void *regEnd=regions[i].pucStartAddress+regions[i].xSizeInBytes;
if (regStart>=from && regEnd<=to) {
//Entire region falls in the range. Disable entirely.
regions[i].xTag=-1;
} else if (regStart>=from && regEnd>to && regStart<to) {
//Start of the region falls in the range. Modify address/len.
int overlap=(uint8_t *)to-(uint8_t *)regStart;
regions[i].pucStartAddress+=overlap;
regions[i].xSizeInBytes-=overlap;
if (regions[i].xExecAddr) regions[i].xExecAddr+=overlap;
} else if (regStart<from && regEnd>from && regEnd<=to) {
//End of the region falls in the range. Modify length.
regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from;
} else if (regStart<from && regEnd>to) {
//Range punches a hole in the region! We do not support this.
ets_printf("%s: region %d: hole punching is not supported!\n", i);
regions[i].xTag=-1; //Just disable memory region. That'll teach them!
}
}
int i;
//Align from and to on word boundaries
from=(void*)((uint32_t)from&~3);
to=(void*)(((uint32_t)to+3)&~3);
for (i=0; regions[i].xSizeInBytes!=0; i++) {
void *regStart=regions[i].pucStartAddress;
void *regEnd=regions[i].pucStartAddress+regions[i].xSizeInBytes;
if (regStart>=from && regEnd<=to) {
//Entire region falls in the range. Disable entirely.
regions[i].xTag=-1;
} else if (regStart>=from && regEnd>to && regStart<to) {
//Start of the region falls in the range. Modify address/len.
int overlap=(uint8_t *)to-(uint8_t *)regStart;
regions[i].pucStartAddress+=overlap;
regions[i].xSizeInBytes-=overlap;
if (regions[i].xExecAddr) regions[i].xExecAddr+=overlap;
} else if (regStart<from && regEnd>from && regEnd<=to) {
//End of the region falls in the range. Modify length.
regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from;
} else if (regStart<from && regEnd>to) {
//Range punches a hole in the region! We do not support this.
ESP_EARLY_LOGE(TAG, "region %d: hole punching is not supported!", i);
regions[i].xTag=-1; //Just disable memory region. That'll teach them!
}
}
}
@@ -167,51 +170,52 @@ ToDo: The regions are different when stuff like trace memory, BT, ... is used. M
Same with loading of apps. Same with using SPI RAM.
*/
void heap_alloc_caps_init() {
int i;
//Disable the bits of memory where this code is loaded.
disable_mem_region(&_bss_start, &_heap_start);
disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region
disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region
disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region
disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5
int i;
//Disable the bits of memory where this code is loaded.
disable_mem_region(&_bss_start, &_heap_start);
disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region
disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region
disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region
disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5
// TODO: this region should be checked, since we don't need to knock out all region finally
disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region
// TODO: this region should be checked, since we don't need to knock out all region finally
disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region
#if CONFIG_MEMMAP_BT
disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region
disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region
#endif
#if CONFIG_MEMMAP_TRACEMEM
disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region
disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region
#endif
#if 0
enable_spi_sram();
enable_spi_sram();
#else
disable_mem_region((void*)0x3f800000, (void*)0x3f820000); //SPI SRAM not installed
disable_mem_region((void*)0x3f800000, (void*)0x3f820000); //SPI SRAM not installed
#endif
//The heap allocator will treat every region given to it as separate. In order to get bigger ranges of contiguous memory,
//it's useful to coalesce adjacent regions that have the same tag.
//The heap allocator will treat every region given to it as separate. In order to get bigger ranges of contiguous memory,
//it's useful to coalesce adjacent regions that have the same tag.
for (i=1; regions[i].xSizeInBytes!=0; i++) {
if (regions[i].pucStartAddress == (regions[i-1].pucStartAddress + regions[i-1].xSizeInBytes) &&
regions[i].xTag == regions[i-1].xTag ) {
regions[i-1].xTag=-1;
regions[i].pucStartAddress=regions[i-1].pucStartAddress;
regions[i].xSizeInBytes+=regions[i-1].xSizeInBytes;
}
}
for (i=1; regions[i].xSizeInBytes!=0; i++) {
if (regions[i].pucStartAddress == (regions[i-1].pucStartAddress + regions[i-1].xSizeInBytes) &&
regions[i].xTag == regions[i-1].xTag ) {
regions[i-1].xTag=-1;
regions[i].pucStartAddress=regions[i-1].pucStartAddress;
regions[i].xSizeInBytes+=regions[i-1].xSizeInBytes;
}
}
#if 1 //Change to 1 to show the regions the heap allocator is initialized with.
ets_printf("Initializing heap allocator:\n");
for (i=0; regions[i].xSizeInBytes!=0; i++) {
if ( regions[i].xTag != -1 ) ets_printf("Region %02d: %08X len %08X tag %d\n", i, (int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag);
}
#endif
//Initialize the malloc implementation.
vPortDefineHeapRegionsTagged( regions );
ESP_EARLY_LOGI(TAG, "Initializing heap allocator:");
for (i=0; regions[i].xSizeInBytes!=0; i++) {
if (regions[i].xTag != -1) {
ESP_EARLY_LOGI(TAG, "Region %02d: %08X len %08X tag %d", i,
(int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag);
}
}
//Initialize the malloc implementation.
vPortDefineHeapRegionsTagged( regions );
}
/*
@@ -219,7 +223,7 @@ Standard malloc() implementation. Will return ho-hum byte-accessible data memory
*/
void *pvPortMalloc( size_t xWantedSize )
{
return pvPortMallocCaps( xWantedSize, MALLOC_CAP_8BIT );
return pvPortMallocCaps( xWantedSize, MALLOC_CAP_8BIT );
}
/*
@@ -227,30 +231,30 @@ Routine to allocate a bit of memory with certain capabilities. caps is a bitfiel
*/
void *pvPortMallocCaps( size_t xWantedSize, uint32_t caps )
{
int prio;
int tag, j;
void *ret=NULL;
uint32_t remCaps;
for (prio=0; prio<NO_PRIOS; prio++) {
//Iterate over tag descriptors for this priority
for (tag=0; tagDesc[tag][prio]!=MALLOC_CAP_INVALID; tag++) {
if ((tagDesc[tag][prio]&caps)!=0) {
//Tag has at least one of the caps requested. If caps has other bits set that this prio
//doesn't cover, see if they're available in other prios.
remCaps=caps&(~tagDesc[tag][prio]); //Remaining caps to be fulfilled
j=prio+1;
while (remCaps!=0 && j<NO_PRIOS) {
remCaps=remCaps&(~tagDesc[tag][j]);
j++;
}
if (remCaps==0) {
//This tag can satisfy all the requested capabilities. See if we can grab some memory using it.
ret=pvPortMallocTagged(xWantedSize, tag);
if (ret!=NULL) return ret;
}
}
}
}
//Nothing usable found.
return NULL;
int prio;
int tag, j;
void *ret=NULL;
uint32_t remCaps;
for (prio=0; prio<NO_PRIOS; prio++) {
//Iterate over tag descriptors for this priority
for (tag=0; tagDesc[tag][prio]!=MALLOC_CAP_INVALID; tag++) {
if ((tagDesc[tag][prio]&caps)!=0) {
//Tag has at least one of the caps requested. If caps has other bits set that this prio
//doesn't cover, see if they're available in other prios.
remCaps=caps&(~tagDesc[tag][prio]); //Remaining caps to be fulfilled
j=prio+1;
while (remCaps!=0 && j<NO_PRIOS) {
remCaps=remCaps&(~tagDesc[tag][j]);
j++;
}
if (remCaps==0) {
//This tag can satisfy all the requested capabilities. See if we can grab some memory using it.
ret=pvPortMallocTagged(xWantedSize, tag);
if (ret!=NULL) return ret;
}
}
}
}
//Nothing usable found.
return NULL;
}

16
components/esp32/include/esp_attr.h
View File

@@ -17,8 +17,8 @@
#define ROMFN_ATTR
//Normally, the linker script will put all code and rodata in flash,
//and all variables in shared RAM. This can be redirected to IRAM if
//needed using these macros.
//and all variables in shared RAM. These macros can be used to redirect
//particular functions/variables to other memory regions.
// Forces code into IRAM instead of flash
#define IRAM_ATTR __attribute__((section(".iram1")))
@@ -26,4 +26,16 @@
// Forces data into DRAM instead of flash
#define DRAM_ATTR __attribute__((section(".dram1")))
// Forces code into RTC fast memory
#define RTC_IRAM_ATTR __attribute__((section(".rtc.text")))
// Forces data into RTC slow memory
// Any variable marked with this attribute will keep its value
// during a deep sleep / wake cycle.
#define RTC_DATA_ATTR __attribute__((section(".rtc.data")))
// Forces read-only data into RTC slow memory
// Makes constant data available to RTC wake stubs (see esp_deepsleep.h)
#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata")))
#endif /* __ESP_ATTR_H__ */

137
components/esp32/include/esp_deepsleep.h Normal file
View File

@@ -0,0 +1,137 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_DEEPSLEEP_H__
#define __ESP_DEEPSLEEP_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup Deep_Sleep_API Deep Sleep API
* @brief API for putting device into deep sleep
*/
/** @addtogroup Deep_Sleep_API
* @{
*/
/**
* @brief Set the chip to deep-sleep mode.
*
* The device will automatically wake up after the deep-sleep time set
* by the users. Upon waking up, the device boots up from user_init.
*
* @attention The parameter time_in_us to be "uint64" is for further development.
* Only the low 32 bits of parameter time_in_us are avalable now.
*
* @param uint64 time_in_us : deep-sleep time, only the low 32bits are avalable now. unit: microsecond
*
* @return null
*/
void system_deep_sleep(uint64_t time_in_us);
/**
* @brief Default stub to run on wake from deep sleep.
*
* Allows for executing code immediately on wake from sleep, before
* the software bootloader or esp-idf app has started up.
*
* This function is weak-linked, so you can implement your own version
* to run code immediately when the chip wakes from
* sleep.
*
* For example:
* @code
* void RTC_IRAM_ATTR esp_wake_deep_sleep(void) {
* esp_default_wake_deep_sleep();
* // Add additional functionality here
* }
*
* (Implementing this function is not required for normal operation,
* in the usual case your app will start normally when waking from
* deep sleep.)
*
* esp_wake_deep_sleep() functionality is limited:
*
* - Runs immediately on wake, so most of the SoC is freshly reset -
* flash is unmapped and hardware is otherwise uninitialised.
*
* - Can only call functions implemented in ROM, or marked RTC_IRAM_ATTR.
*
* - Static variables marked RTC_DATA_ATTR will have initial values on
* cold boot, and maintain these values between sleep/wake cycles.
*
* - Read-only data should be marked RTC_RODATA_ATTR. Strings must be
* declared as variables also using RTC_RODATA_ATTR, like this:
* RTC_RODATA_ATTR const char message[] = "Hello from very early boot!\n";
*
* - Any other static memory will not be initialised (either to zero,
* or to any predefined value).
*
*
* - If you implement your own stub, the first call the stub makes
should be to esp_default_wake_deep_sleep().
*/
void esp_wake_deep_sleep(void);
/**
* @brief Function type for stub to run on wake from sleep.
*
*/
typedef void (*esp_deep_sleep_wake_stub_fn_t)(void);
/**
* @brief Install a new stub at runtime to run on wake from deep sleep
*
* If implementing esp_wake_deep_sleep() then it is not necessary to
* call this function.
*
* However, it is possible to call this function to substitute a
* different deep sleep stub. Any function used as a deep sleep stub
* must be marked RTC_IRAM_ATTR, and must obey the same rules given
* for esp_wake_deep_sleep().
*/
void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub);
/**
* @brief Return current wake from deep sleep stub, or NULL if
* no stub is installed.
*/
esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void);
/* The default esp-idf-provided esp_wake_deep_sleep() stub.
If you replace esp_wake_deep_sleep() in your program, or use
esp_set_deep_sleep_wake_stub(), then it is recommended you call
esp_default_wake_deep_sleep() as the first function in your stub.
*/
void esp_default_wake_deep_sleep(void);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ESP_SYSTEM_H__ */

7
components/esp32/include/esp_err.h
View File

@@ -15,6 +15,7 @@
#define __ESP_ERR_H__
#include <stdint.h>
#include <assert.h>
#ifdef __cplusplus
extern "C" {
@@ -31,6 +32,12 @@ typedef int32_t esp_err_t;
#define ESP_ERR_INVALID_ARG 0x102
#define ESP_ERR_INVALID_STATE 0x103
/**
* Macro which can be used to check the error code,
* and terminate the program in case the code is not ESP_OK.
* Prints the failed statement to serial output.
*/
#define ESP_ERROR_CHECK(x) do { esp_err_t rc = (x); if (rc != ESP_OK) { assert(0 && #x);} } while(0);
#ifdef __cplusplus
}

55
components/esp32/include/esp_event.h
View File

@@ -19,8 +19,7 @@
#include <stdbool.h>
#include "esp_err.h"
#include "esp_wifi.h"
#include "esp_wifi_types.h"
#include "tcpip_adapter.h"
#ifdef __cplusplus
@@ -101,33 +100,11 @@ typedef union {
} system_event_info_t;
typedef struct {
system_event_id_t event_id; /**< even ID */
system_event_id_t event_id; /**< event ID */
system_event_info_t event_info; /**< event information */
} system_event_t;
/**
* @brief Application specified event callback function
*
* @param void *ctx : reserved for user
* @param system_event_t *event : event type defined in this file
*
* @return ESP_OK : succeed
* @return others : fail
*/
typedef esp_err_t (*system_event_cb_t)(void *ctx, system_event_t *event);
/**
* @brief Set application specified event callback function
*
* @attention 1. If cb is NULL, means application don't need to handle
* If cb is not NULL, it will be call when an event is received, after the default event callback is completed
*
* @param system_event_cb_t cb : callback
* @param void *ctx : reserved for user
*
* @return system_event_cb_t : old callback
*/
system_event_cb_t esp_event_set_cb(system_event_cb_t cb, void *ctx);
typedef esp_err_t (*system_event_handler_t)(system_event_t *event);
/**
* @brief Send a event to event task
@@ -142,28 +119,20 @@ system_event_cb_t esp_event_set_cb(system_event_cb_t cb, void *ctx);
esp_err_t esp_event_send(system_event_t *event);
/**
* @brief Get the event handler
* @brief Default event handler for system events
*
* @attention : currently this API returns event queue handler, by this event queue,
* users can notice when WiFi has done something like scanning done, connected to AP or disconnected from AP.
* This function performs default handling of system events.
* When using esp_event_loop APIs, it is called automatically before invoking the user-provided
* callback function.
*
* @param null
* Applications which implement a custom event loop must call this function
* as part of event processing.
*
* @return void * : event queue pointer
* @param event pointer to event to be handled
* @return ESP_OK if an event was handled successfully
*/
void *esp_event_get_handler(void);
esp_err_t esp_event_process_default(system_event_t *event);
/**
* @brief Init the event module
* Create the event handler and task
*
* @param system_event_cb_t cb : application specified event callback, it can be modified by call esp_event_set_cb
* @param void *ctx : reserved for user
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_event_init(system_event_cb_t cb, void *ctx);
#ifdef __cplusplus
}

81
components/esp32/include/esp_event_loop.h Normal file
View File

@@ -0,0 +1,81 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_EVENT_LOOP_H__
#define __ESP_EVENT_LOOP_H__
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "esp_event.h"
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Application specified event callback function
*
* @param void *ctx : reserved for user
* @param system_event_t *event : event type defined in this file
*
* @return ESP_OK : succeed
* @return others : fail
*/
typedef esp_err_t (*system_event_cb_t)(void *ctx, system_event_t *event);
/**
* @brief Initialize event loop
* Create the event handler and task
*
* @param system_event_cb_t cb : application specified event callback, it can be modified by call esp_event_set_cb
* @param void *ctx : reserved for user
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_event_loop_init(system_event_cb_t cb, void *ctx);
/**
* @brief Set application specified event callback function
*
* @attention 1. If cb is NULL, means application don't need to handle
* If cb is not NULL, it will be call when an event is received, after the default event callback is completed
*
* @param system_event_cb_t cb : callback
* @param void *ctx : reserved for user
*
* @return system_event_cb_t : old callback
*/
system_event_cb_t esp_event_loop_set_cb(system_event_cb_t cb, void *ctx);
/**
* @brief Get the queue used by event loop
*
* @attention : currently this API is used to initialize "q" parameter
* of wifi_init structure.
*
* @return QueueHandle_t : event queue handle
*/
QueueHandle_t esp_event_loop_get_queue(void);
#ifdef __cplusplus
}
#endif
#endif /* __ESP_EVENT_LOOP_H__ */

0
components/esp32/heap_alloc_caps.h → components/esp32/include/esp_heap_alloc_caps.h
View File

143
components/esp32/include/esp_smartconfig.h Normal file
View File

@@ -0,0 +1,143 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_SMARTCONFIG_H__
#define __ESP_SMARTCONFIG_H__
#include <stdint.h>
#include <esp_types.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SC_STATUS_WAIT = 0, /**< waiting, do not start connection in this phase */
SC_STATUS_FIND_CHANNEL, /**< find target channel, start connection by APP in this phase */
SC_STATUS_GETTING_SSID_PSWD, /**< getting SSID and password of target AP */
SC_STATUS_LINK, /**< connecting to target AP */
SC_STATUS_LINK_OVER, /**< got IP, connect to AP successfully */
} smartconfig_status_t;
typedef enum {
SC_TYPE_ESPTOUCH = 0, /**< protocol: ESPTouch */
SC_TYPE_AIRKISS, /**< protocol: AirKiss */
SC_TYPE_ESPTOUCH_AIRKISS, /**< protocol: ESPTouch and AirKiss */
} smartconfig_type_t;
/**
* @brief The callback of SmartConfig, executed when smart-config status changed.
*
* @param smartconfig_status_t status : status of SmartConfig:
* - if status == SC_STATUS_GETTING_SSID_PSWD, parameter void *pdata is a pointer
of smartconfig_type_t, means SmartConfig type: AirKiss or ESP-TOUCH.
* - if status == SC_STATUS_LINK, parameter void *pdata is a pointer of struct station_config;
* - if status == SC_STATUS_LINK_OVER, parameter void *pdata is a pointer of mobile
* phone's IP address, 4 bytes. This is only available in ESPTOUCH, otherwise,
* it is NULL.
* - otherwise, parameter void *pdata is NULL.
* @param void *pdata : data of SmartConfig
*
* @return null
*/
typedef void (*sc_callback_t)(smartconfig_status_t status, void *pdata);
/**
* @brief Get the version of SmartConfig.
*
* @param null
*
* @return SmartConfig version
*/
const char *esp_smartconfig_get_version(void);
/**
* @brief Start SmartConfig mode.
*
* Start SmartConfig mode, to connect ESP32 station to AP, by sniffing
* for special packets from the air, containing SSID and password of desired AP.
* You need to broadcast the SSID and password (e.g. from mobile device or computer)
* with the SSID and password encoded.
*
* @attention 1. This API can only be called in station mode.
* @attention 2. During SmartConfig, ESP32 station and soft-AP are disabled.
* @attention 3. Can not call esp_smartconfig_start twice before it finish, please call
* esp_smartconfig_stop first.
* @attention 4. Don't call any other APIs during SmartConfig, please call esp_smartconfig_stop first.
*
* @param sc_callback_t cb : SmartConfig callback; executed when SmartConfig status changed;
* @param uint8 log : 1, UART output logs; otherwise, UART only outputs the result.
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_smartconfig_start(sc_callback_t cb, ...);
/**
* @brief Stop SmartConfig, free the buffer taken by esp_smartconfig_start.
*
* @attention Whether connect to AP succeed or not, this API should be called to free
* memory taken by smartconfig_start.
*
* @param null
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_smartconfig_stop(void);
/**
* @brief Set timeout of SmartConfig.
*
* @attention SmartConfig timeout start at SC_STATUS_FIND_CHANNEL, SmartConfig will
* restart if timeout.
*
* @param uint8 time_s : range 15s~255s, offset:45s.
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_esptouch_set_timeout(uint8_t time_s);
/**
* @brief Set protocol type of SmartConfig.
*
* @attention If users need to set the SmartConfig type, please set it before calling
* esp_smartconfig_start.
*
* @param smartconfig_type_t type : AirKiss, ESP-TOUCH or both.
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_smartconfig_set_type(smartconfig_type_t type);
/**
* @brief Set mode of SmartConfig. default normal mode.
*
* @attention If users need to set the SmartConfig mode, please set it before calling
* esp_smartconfig_start. Different mode should match different APP(phone).
*
* @param bool enable : false-disable(default); true-enable;
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_smartconfig_fast_mode(bool enable);
#ifdef __cplusplus
}
#endif
#endif

16
components/esp32/include/esp_system.h
View File

@@ -18,6 +18,7 @@
#include <stdint.h>
#include "esp_err.h"
#include "esp_deepsleep.h"
#ifdef __cplusplus
extern "C" {
@@ -62,21 +63,6 @@ void system_restore(void);
*/
void system_restart(void);
/**
* @brief Set the chip to deep-sleep mode.
*
* The device will automatically wake up after the deep-sleep time set
* by the users. Upon waking up, the device boots up from user_init.
*
* @attention The parameter time_in_us to be "uint64" is for further development.
* Only the low 32 bits of parameter time_in_us are avalable now.
*
* @param uint64 time_in_us : deep-sleep time, only the low 32bits are avalable now. unit: microsecond
*
* @return null
*/
void system_deep_sleep(uint64_t time_in_us);
/**
* @brief Get system time, unit: microsecond.
*

15
components/esp32/include/esp_task.h
View File

@@ -15,10 +15,10 @@
/* Notes:
* 1. Put all task priority and stack size definition in this file
* 2. If the task priority is less than 10, use ESP_TASK_PRIO_MIN + X style,
* otherwise use ESP_TASK_PRIO_MIN - X style
* 3. If this is a daemon task, the macro prifix is ESP_TASKD_, otherwise
* otherwise use ESP_TASK_PRIO_MAX - X style
* 3. If this is a daemon task, the macro prefix is ESP_TASKD_, otherwise
* it's ESP_TASK_
* 4. If the configMAX_PRIORITIES is modified, please make all prority are
* 4. If the configMAX_PRIORITIES is modified, please make all priority are
* greater than 0
* 5. Make sure esp_task.h is consistent between wifi lib and idf
*/
@@ -43,12 +43,17 @@
#define ESP_TASK_WPS_PRIO (ESP_TASK_PRIO_MIN + 2)
#define ESP_TASK_WPS_STACK 2048
/* Bt contoller Task */
/* controller */
#define ESP_TASK_BT_CONTROLLER_PRIO (ESP_TASK_PRIO_MAX - 1)
#define ESP_TASK_BT_CONTROLLER_STACK 4096
/* idf task */
#define ESP_TASKD_EVENT_PRIO (ESP_TASK_PRIO_MAX - 5)
#define ESP_TASKD_EVENT_STACK CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE
#define ESP_TASK_WIFI_STARTUP_PRIO (ESP_TASK_PRIO_MAX - 7)
#define ESP_TASK_WIFI_STARTUP_STACK 4096
#define ESP_TASK_TCPIP_PRIO (ESP_TASK_PRIO_MAX - 7)
#define ESP_TASK_TCPIP_STACK 2048
#define ESP_TASK_MAIN_PRIO (ESP_TASK_PRIO_MIN + 1)
#define ESP_TASK_MAIN_STACK CONFIG_MAIN_TASK_STACK_SIZE
#endif

204
components/esp32/include/esp_wifi.h
View File

@@ -59,113 +59,26 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "rom/queue.h"
#include "esp_err.h"
#include "esp_wifi_types.h"
#include "esp_event.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WIFI_MODE_NULL = 0, /**< null mode */
WIFI_MODE_STA, /**< WiFi station mode */
WIFI_MODE_AP, /**< WiFi soft-AP mode */
WIFI_MODE_APSTA, /**< WiFi station + soft-AP mode */
WIFI_MODE_MAX
} wifi_mode_t;
typedef enum {
WIFI_IF_STA = 0, /**< ESP32 station interface */
WIFI_IF_AP, /**< ESP32 soft-AP interface */
WIFI_IF_MAX
} wifi_interface_t;
typedef enum {
WIFI_COUNTRY_CN = 0, /**< country China, channel range [1, 14] */
WIFI_COUNTRY_JP, /**< country Japan, channel range [1, 14] */
WIFI_COUNTRY_US, /**< country USA, channel range [1, 11] */
WIFI_COUNTRY_EU, /**< country Europe, channel range [1, 13] */
WIFI_COUNTRY_MAX
} wifi_country_t;
typedef enum {
WIFI_AUTH_OPEN = 0, /**< authenticate mode : open */
WIFI_AUTH_WEP, /**< authenticate mode : WEP */
WIFI_AUTH_WPA_PSK, /**< authenticate mode : WPA_PSK */
WIFI_AUTH_WPA2_PSK, /**< authenticate mode : WPA2_PSK */
WIFI_AUTH_WPA_WPA2_PSK, /**< authenticate mode : WPA_WPA2_PSK */
WIFI_AUTH_MAX
} wifi_auth_mode_t;
enum {
WIFI_REASON_UNSPECIFIED = 1,
WIFI_REASON_AUTH_EXPIRE = 2,
WIFI_REASON_AUTH_LEAVE = 3,
WIFI_REASON_ASSOC_EXPIRE = 4,
WIFI_REASON_ASSOC_TOOMANY = 5,
WIFI_REASON_NOT_AUTHED = 6,
WIFI_REASON_NOT_ASSOCED = 7,
WIFI_REASON_ASSOC_LEAVE = 8,
WIFI_REASON_ASSOC_NOT_AUTHED = 9,
WIFI_REASON_DISASSOC_PWRCAP_BAD = 10,
WIFI_REASON_DISASSOC_SUPCHAN_BAD = 11,
WIFI_REASON_IE_INVALID = 13,
WIFI_REASON_MIC_FAILURE = 14,
WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT = 16,
WIFI_REASON_IE_IN_4WAY_DIFFERS = 17,
WIFI_REASON_GROUP_CIPHER_INVALID = 18,
WIFI_REASON_PAIRWISE_CIPHER_INVALID = 19,
WIFI_REASON_AKMP_INVALID = 20,
WIFI_REASON_UNSUPP_RSN_IE_VERSION = 21,
WIFI_REASON_INVALID_RSN_IE_CAP = 22,
WIFI_REASON_802_1X_AUTH_FAILED = 23,
WIFI_REASON_CIPHER_SUITE_REJECTED = 24,
WIFI_REASON_BEACON_TIMEOUT = 200,
WIFI_REASON_NO_AP_FOUND = 201,
WIFI_REASON_AUTH_FAIL = 202,
WIFI_REASON_ASSOC_FAIL = 203,
WIFI_REASON_HANDSHAKE_TIMEOUT = 204,
};
typedef enum {
WIFI_SECOND_CHAN_NONE = 0, /**< the channel width is HT20 */
WIFI_SECOND_CHAN_ABOVE, /**< the channel width is HT40 and the second channel is above the primary channel */
WIFI_SECOND_CHAN_BELOW, /**< the channel width is HT40 and the second channel is below the primary channel */
} wifi_second_chan_t;
/**
* @brief startup WiFi driver and register application specific callback function
*
* @attention 1. This API should be called in application startup code to init WiFi driver
* @attention 2. The callback function is used to provide application specific WiFi configuration,
* such as, set the WiFi mode, register the event callback, set AP SSID etc before
* WiFi is startup
* @attention 3. Avoid to create application task in the callback, otherwise you may get wrong behavior
* @attention 4. If the callback return is not ESP_OK, the startup will fail!
* @attention 5. Before this API can be called, system_init()/esp_event_init()/tcpip_adapter_init() should
* be called firstly
*
* @param wifi_startup_cb_t cb : application specific callback function
* @param void *ctx : reserved for user
*
* @return ESP_OK : succeed
* @return others : fail
*/
typedef esp_err_t (* wifi_startup_cb_t)(void *ctx);
esp_err_t esp_wifi_startup(wifi_startup_cb_t cb, void *ctx);
typedef struct {
void *event_q; /**< WiFi event q handler, it's a freeRTOS queue */
uint8_t rx_ba_win; /**< TBC */
uint8_t tx_ba_win; /**< TBC */
uint8_t rx_buf_cnt; /**< TBC */
uint8_t tx_buf_cnt; /**< TBC */
system_event_handler_t event_handler; /**< WiFi event handler */
} wifi_init_config_t;
#define WIFI_INIT_CONFIG_DEFAULT() { \
.event_handler = &esp_event_send, \
};
/**
* @brief Init WiFi
* Alloc resource for WiFi driver, such as WiFi control structure, RX/TX buffer,
@@ -176,7 +89,6 @@ typedef struct {
* to this queue when event happens, such as, when station connects to WiFi, WiFi driver
* will post station connected event to this queue. If the queue is not initialized, WiFi
* will not post any events
* @attention 3. For other parameters, currently it's not ready, just ignore it.
*
* @param wifi_init_config_t *config : provide WiFi init configuration
*
@@ -288,13 +200,6 @@ esp_err_t esp_wifi_clear_fast_connect(void);
*/
esp_err_t esp_wifi_kick_station(uint16_t aid);
typedef struct {
char *ssid; /**< SSID of AP */
uint8_t *bssid; /**< MAC address of AP */
uint8_t channel; /**< channel, scan the specific channel */
bool show_hidden; /**< enable to scan AP whose SSID is hidden */
} wifi_scan_config_t;
/**
* @brief Scan all available APs.
*
@@ -332,15 +237,6 @@ esp_err_t esp_wifi_scan_stop(void);
*/
esp_err_t esp_wifi_get_ap_num(uint16_t *number);
typedef struct {
uint8_t bssid[6]; /**< MAC address of AP */
uint8_t ssid[32]; /**< SSID of AP */
uint8_t primary; /**< channel of AP */
wifi_second_chan_t second; /**< second channel of AP */
int8_t rssi; /**< signal strength of AP */
wifi_auth_mode_t authmode; /**< authmode of AP */
} wifi_ap_list_t;
/**
* @brief Get AP list found in last scan
*
@@ -353,13 +249,6 @@ typedef struct {
*/
esp_err_t esp_wifi_get_ap_list(uint16_t *number, wifi_ap_list_t *ap_list);
typedef enum {
WIFI_PS_NONE, /**< No power save */
WIFI_PS_MODEM, /**< Modem power save */
WIFI_PS_LIGHT, /**< Light power save */
WIFI_PS_MAC, /**< MAC power save */
} wifi_ps_type_t;
/**
* @brief Set current power save type
*
@@ -380,10 +269,6 @@ esp_err_t esp_wifi_set_ps(wifi_ps_type_t type);
*/
esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type);
#define WIFI_PROTOCOL_11B 1
#define WIFI_PROTOCOL_11G 2
#define WIFI_PROTOCOL_11N 4
/**
* @brief Set protocol type of specified interface
* The default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N)
@@ -409,11 +294,6 @@ esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol_bitmap);
*/
esp_err_t esp_wifi_get_protocol(wifi_interface_t ifx, uint8_t *protocol_bitmap);
typedef enum {
WIFI_BW_HT20 = 0, /* Bandwidth is HT20 */
WIFI_BW_HT40, /* Bandwidth is HT40 */
} wifi_bandwidth_t;
/**
* @brief Set the bandwidth of ESP32 specified interface
*
@@ -542,45 +422,22 @@ esp_err_t esp_wifi_set_promiscuous_rx_cb(wifi_promiscuous_cb_t cb);
/**
* @brief Enable the promiscuous mode.
*
* @param uint8 promiscuous : 0 - disable / 1 - enable
* @param bool promiscuous : false - disable / true - enable
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_set_promiscuous(uint8_t enable);
esp_err_t esp_wifi_set_promiscuous(bool en);
/**
* @brief Get the promiscuous mode.
*
* @param uint8 *enable : store the current status of promiscuous mode
* @param bool *enable : store the current status of promiscuous mode
*
* @return ESP_OK : succeed
* @return others : fail
*/
esp_err_t esp_wifi_get_promiscuous(uint8_t *enable);
typedef struct {
char ssid[32]; /**< SSID of ESP32 soft-AP */
char password[64]; /**< Password of ESP32 soft-AP */
uint8_t ssid_len; /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */
uint8_t channel; /**< Channel of ESP32 soft-AP */
wifi_auth_mode_t authmode; /**< Auth mode of ESP32 soft-AP. Do not support AUTH_WEP in soft-AP mode */
uint8_t ssid_hidden; /**< Broadcast SSID or not, default 0, broadcast the SSID */
uint8_t max_connection; /**< Max number of stations allowed to connect in, default 4, max 4 */
uint16_t beacon_interval; /**< Beacon interval, 100 ~ 60000 ms, default 100 ms */
} wifi_ap_config_t;
typedef struct {
char ssid[32]; /**< SSID of target AP*/
char password[64]; /**< password of target AP*/
bool bssid_set; /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
uint8_t bssid[6]; /**< MAC address of target AP*/
} wifi_sta_config_t;
typedef union {
wifi_ap_config_t ap; /**< configuration of AP */
wifi_sta_config_t sta; /**< configuration of STA */
} wifi_config_t;
esp_err_t esp_wifi_get_promiscuous(bool *en);
/**
* @brief Set the configuration of the ESP32 STA or AP
@@ -609,11 +466,6 @@ esp_err_t esp_wifi_set_config(wifi_interface_t ifx, wifi_config_t *conf);
*/
esp_err_t esp_wifi_get_config(wifi_interface_t ifx, wifi_config_t *conf);
struct station_info {
STAILQ_ENTRY(station_info) next;
uint8_t bssid[6];
};
/**
* @brief Get STAs associated with soft-AP
*
@@ -628,11 +480,6 @@ esp_err_t esp_wifi_get_station_list(struct station_info **station);
esp_err_t esp_wifi_free_station_list(void);
typedef enum {
WIFI_STORAGE_FLASH, /**< all configuration will strore in both memory and flash */
WIFI_STORAGE_RAM, /**< all configuration will only store in the memory */
} wifi_storage_t;
/**
* @brief Set the WiFi API configuration storage type
*
@@ -689,27 +536,6 @@ esp_err_t esp_wifi_set_auto_connect(bool en);
*/
esp_err_t esp_wifi_get_auto_connect(bool *en);
/**
* @brief Vendor IE type
*
*/
typedef enum {
WIFI_VND_IE_TYPE_BEACON,
WIFI_VND_IE_TYPE_PROBE_REQ,
WIFI_VND_IE_TYPE_PROBE_RESP,
WIFI_VND_IE_TYPE_ASSOC_REQ,
WIFI_VND_IE_TYPE_ASSOC_RESP,
} wifi_vendor_ie_type_t;
/**
* @brief Vendor IE index
*
*/
typedef enum {
WIFI_VND_IE_ID_0,
WIFI_VND_IE_ID_1,
} wifi_vendor_ie_id_t;
/**
* @brief Set vendor specific element
*

190
components/esp32/include/esp_wifi_types.h Normal file
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@@ -0,0 +1,190 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_WIFI_TYPES_H__
#define __ESP_WIFI_TYPES_H__
#include <stdint.h>
#include <stdbool.h>
#include "rom/queue.h"
#include "esp_err.h"
#include "esp_wifi_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WIFI_MODE_NULL = 0, /**< null mode */
WIFI_MODE_STA, /**< WiFi station mode */
WIFI_MODE_AP, /**< WiFi soft-AP mode */
WIFI_MODE_APSTA, /**< WiFi station + soft-AP mode */
WIFI_MODE_MAX
} wifi_mode_t;
typedef enum {
WIFI_IF_STA = 0, /**< ESP32 station interface */
WIFI_IF_AP, /**< ESP32 soft-AP interface */
WIFI_IF_MAX
} wifi_interface_t;
typedef enum {
WIFI_COUNTRY_CN = 0, /**< country China, channel range [1, 14] */
WIFI_COUNTRY_JP, /**< country Japan, channel range [1, 14] */
WIFI_COUNTRY_US, /**< country USA, channel range [1, 11] */
WIFI_COUNTRY_EU, /**< country Europe, channel range [1, 13] */
WIFI_COUNTRY_MAX
} wifi_country_t;
typedef enum {
WIFI_AUTH_OPEN = 0, /**< authenticate mode : open */
WIFI_AUTH_WEP, /**< authenticate mode : WEP */
WIFI_AUTH_WPA_PSK, /**< authenticate mode : WPA_PSK */
WIFI_AUTH_WPA2_PSK, /**< authenticate mode : WPA2_PSK */
WIFI_AUTH_WPA_WPA2_PSK, /**< authenticate mode : WPA_WPA2_PSK */
WIFI_AUTH_MAX
} wifi_auth_mode_t;
enum {
WIFI_REASON_UNSPECIFIED = 1,
WIFI_REASON_AUTH_EXPIRE = 2,
WIFI_REASON_AUTH_LEAVE = 3,
WIFI_REASON_ASSOC_EXPIRE = 4,
WIFI_REASON_ASSOC_TOOMANY = 5,
WIFI_REASON_NOT_AUTHED = 6,
WIFI_REASON_NOT_ASSOCED = 7,
WIFI_REASON_ASSOC_LEAVE = 8,
WIFI_REASON_ASSOC_NOT_AUTHED = 9,
WIFI_REASON_DISASSOC_PWRCAP_BAD = 10,
WIFI_REASON_DISASSOC_SUPCHAN_BAD = 11,
WIFI_REASON_IE_INVALID = 13,
WIFI_REASON_MIC_FAILURE = 14,
WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT = 16,
WIFI_REASON_IE_IN_4WAY_DIFFERS = 17,
WIFI_REASON_GROUP_CIPHER_INVALID = 18,
WIFI_REASON_PAIRWISE_CIPHER_INVALID = 19,
WIFI_REASON_AKMP_INVALID = 20,
WIFI_REASON_UNSUPP_RSN_IE_VERSION = 21,
WIFI_REASON_INVALID_RSN_IE_CAP = 22,
WIFI_REASON_802_1X_AUTH_FAILED = 23,
WIFI_REASON_CIPHER_SUITE_REJECTED = 24,
WIFI_REASON_BEACON_TIMEOUT = 200,
WIFI_REASON_NO_AP_FOUND = 201,
WIFI_REASON_AUTH_FAIL = 202,
WIFI_REASON_ASSOC_FAIL = 203,
WIFI_REASON_HANDSHAKE_TIMEOUT = 204,
};
typedef enum {
WIFI_SECOND_CHAN_NONE = 0, /**< the channel width is HT20 */
WIFI_SECOND_CHAN_ABOVE, /**< the channel width is HT40 and the second channel is above the primary channel */
WIFI_SECOND_CHAN_BELOW, /**< the channel width is HT40 and the second channel is below the primary channel */
} wifi_second_chan_t;
typedef struct {
char *ssid; /**< SSID of AP */
uint8_t *bssid; /**< MAC address of AP */
uint8_t channel; /**< channel, scan the specific channel */
bool show_hidden; /**< enable to scan AP whose SSID is hidden */
} wifi_scan_config_t;
typedef struct {
uint8_t bssid[6]; /**< MAC address of AP */
uint8_t ssid[32]; /**< SSID of AP */
uint8_t primary; /**< channel of AP */
wifi_second_chan_t second; /**< second channel of AP */
int8_t rssi; /**< signal strength of AP */
wifi_auth_mode_t authmode; /**< authmode of AP */
} wifi_ap_list_t;
typedef enum {
WIFI_PS_NONE, /**< No power save */
WIFI_PS_MODEM, /**< Modem power save */
WIFI_PS_LIGHT, /**< Light power save */
WIFI_PS_MAC, /**< MAC power save */
} wifi_ps_type_t;
#define WIFI_PROTOCOL_11B 1
#define WIFI_PROTOCOL_11G 2
#define WIFI_PROTOCOL_11N 4
typedef enum {
WIFI_BW_HT20 = 0, /* Bandwidth is HT20 */
WIFI_BW_HT40, /* Bandwidth is HT40 */
} wifi_bandwidth_t;
typedef struct {
char ssid[32]; /**< SSID of ESP32 soft-AP */
char password[64]; /**< Password of ESP32 soft-AP */
uint8_t ssid_len; /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */
uint8_t channel; /**< Channel of ESP32 soft-AP */
wifi_auth_mode_t authmode; /**< Auth mode of ESP32 soft-AP. Do not support AUTH_WEP in soft-AP mode */
uint8_t ssid_hidden; /**< Broadcast SSID or not, default 0, broadcast the SSID */
uint8_t max_connection; /**< Max number of stations allowed to connect in, default 4, max 4 */
uint16_t beacon_interval; /**< Beacon interval, 100 ~ 60000 ms, default 100 ms */
} wifi_ap_config_t;
typedef struct {
char ssid[32]; /**< SSID of target AP*/
char password[64]; /**< password of target AP*/
bool bssid_set; /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
uint8_t bssid[6]; /**< MAC address of target AP*/
} wifi_sta_config_t;
typedef union {
wifi_ap_config_t ap; /**< configuration of AP */
wifi_sta_config_t sta; /**< configuration of STA */
} wifi_config_t;
struct station_info {
STAILQ_ENTRY(station_info) next;
uint8_t bssid[6];
};
typedef enum {
WIFI_STORAGE_FLASH, /**< all configuration will strore in both memory and flash */
WIFI_STORAGE_RAM, /**< all configuration will only store in the memory */
} wifi_storage_t;
/**
* @brief Vendor IE type
*
*/
typedef enum {
WIFI_VND_IE_TYPE_BEACON,
WIFI_VND_IE_TYPE_PROBE_REQ,
WIFI_VND_IE_TYPE_PROBE_RESP,
WIFI_VND_IE_TYPE_ASSOC_REQ,
WIFI_VND_IE_TYPE_ASSOC_RESP,
} wifi_vendor_ie_type_t;
/**
* @brief Vendor IE index
*
*/
typedef enum {
WIFI_VND_IE_ID_0,
WIFI_VND_IE_ID_1,
} wifi_vendor_ie_id_t;
#ifdef __cplusplus
}
#endif
#endif /* __ESP_WIFI_TYPES_H__ */

131
components/esp32/include/esp_wps.h
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@@ -1,131 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_WPS_H__
#define __ESP_WPS_H__
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup WiFi_APIs WiFi Related APIs
* @brief WiFi APIs
*/
/** @addtogroup WiFi_APIs
* @{
*/
/** \defgroup WPS_APIs WPS APIs
* @brief ESP32 WPS APIs
*
* WPS can only be used when ESP32 station is enabled.
*
*/
/** @addtogroup WPS_APIs
* @{
*/
typedef enum wps_type {
WPS_TYPE_DISABLE = 0,
WPS_TYPE_PBC,
WPS_TYPE_PIN,
WPS_TYPE_DISPLAY,
WPS_TYPE_MAX,
} WPS_TYPE_t;
enum wps_cb_status {
WPS_CB_ST_SUCCESS = 0, /**< WPS succeed */
WPS_CB_ST_FAILED, /**< WPS fail */
WPS_CB_ST_TIMEOUT, /**< WPS timeout, fail */
WPS_CB_ST_WEP, /**< WPS failed because that WEP is not supported */
WPS_CB_ST_SCAN_ERR, /**< can not find the target WPS AP */
};
/**
* @brief Enable Wi-Fi WPS function.
*
* @attention WPS can only be used when ESP32 station is enabled.
*
* @param WPS_TYPE_t wps_type : WPS type, so far only WPS_TYPE_PBC is supported
*
* @return true : succeed
* @return false : fail
*/
bool wifi_wps_enable(WPS_TYPE_t wps_type);
/**
* @brief Disable Wi-Fi WPS function and release resource it taken.
*
* @param null
*
* @return true : succeed
* @return false : fail
*/
bool wifi_wps_disable(void);
/**
* @brief WPS starts to work.
*
* @attention WPS can only be used when ESP32 station is enabled.
*
* @param null
*
* @return true : WPS starts to work successfully, but does not mean WPS succeed.
* @return false : fail
*/
bool wifi_wps_start(void);
/**
* @brief WPS callback.
*
* @param int status : status of WPS, enum wps_cb_status.
* - If parameter status == WPS_CB_ST_SUCCESS in WPS callback, it means WPS got AP's
* information, user can call wifi_wps_disable to disable WPS and release resource,
* then call wifi_station_connect to connect to target AP.
* - Otherwise, it means that WPS fail, user can create a timer to retry WPS by
* wifi_wps_start after a while, or call wifi_wps_disable to disable WPS and release resource.
*
* @return null
*/
typedef void (*wps_st_cb_t)(int status);
/**
* @brief Set WPS callback.
*
* @attention WPS can only be used when ESP32 station is enabled.
*
* @param wps_st_cb_t cb : callback.
*
* @return true : WPS starts to work successfully, but does not mean WPS succeed.
* @return false : fail
*/
bool wifi_set_wps_cb(wps_st_cb_t cb);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ESP_WPS_H__ */

34
components/esp32/include/heap_alloc_caps.h Normal file
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@@ -0,0 +1,34 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef HEAP_ALLOC_CAPS_H
#define HEAP_ALLOC_CAPS_H
#define MALLOC_CAP_EXEC (1<<0) //Memory must be able to run executable code
#define MALLOC_CAP_32BIT (1<<1) //Memory must allow for aligned 32-bit data accesses
#define MALLOC_CAP_8BIT (1<<2) //Memory must allow for 8/16/...-bit data accesses
#define MALLOC_CAP_DMA (1<<3) //Memory must be able to accessed by DMA
#define MALLOC_CAP_PID2 (1<<4) //Memory must be mapped to PID2 memory space
#define MALLOC_CAP_PID3 (1<<5) //Memory must be mapped to PID3 memory space
#define MALLOC_CAP_PID4 (1<<6) //Memory must be mapped to PID4 memory space
#define MALLOC_CAP_PID5 (1<<7) //Memory must be mapped to PID5 memory space
#define MALLOC_CAP_PID6 (1<<8) //Memory must be mapped to PID6 memory space
#define MALLOC_CAP_PID7 (1<<9) //Memory must be mapped to PID7 memory space
#define MALLOC_CAP_SPISRAM (1<<10) //Memory must be in SPI SRAM
#define MALLOC_CAP_INVALID (1<<31) //Memory can't be used / list end marker
void heap_alloc_caps_init();
void *pvPortMallocCaps(size_t xWantedSize, uint32_t caps);
#endif

2
components/esp32/include/rom/gpio.h
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@@ -38,7 +38,7 @@ extern "C" {
#define GPIO_PIN_COUNT 40
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0 + i*4)
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))

26
components/esp32/include/rom/rtc.h
View File

@@ -44,25 +44,25 @@ extern "C" {
*************************************************************************************
* rtc memory addr type size usage
* 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
* 0x3ff61000+SIZE_CP Slow 6144-SIZE_CP
* 0x3ff62800 Slow 2048 Reserved
* 0x3ff61000+SIZE_CP Slow 4096-SIZE_CP
* 0x3ff62800 Slow 4096 Reserved
*
* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
*
*************************************************************************************
* Rtc store registers usage
* RTC_STORE0
* RTC_STORE1
* RTC_STORE2
* RTC_STORE3
* RTC_STORE4 Reserved
* RTC_STORE5 External Xtal Frequency
* RTC_STORE6 FAST_RTC_MEMORY_ENTRY
* RTC_STORE7 FAST_RTC_MEMORY_CRC
* RTC_CNTL_STORE0_REG
* RTC_CNTL_STORE1_REG
* RTC_CNTL_STORE2_REG
* RTC_CNTL_STORE3_REG
* RTC_CNTL_STORE4_REG Reserved
* RTC_CNTL_STORE5_REG External Xtal Frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
*************************************************************************************
*/
#define RTC_ENTRY_ADDR RTC_STORE6
#define RTC_MEMORY_CRC RTC_STORE7
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
typedef enum {
@@ -161,7 +161,7 @@ WAKEUP_REASON rtc_get_wakeup_cause(void);
*
* @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
*
* @param uint32_t crc_len : 0 - 0x7ff, 0 for 1 byte, 0x7ff for 0x800 byte.
* @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
*
* @return uint32_t : CRC32 result
*/

45
components/esp32/include/soc/cpu.h
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@@ -33,4 +33,49 @@ static inline bool cpu_in_interrupt_context(void)
return (ps & PS_UM) == 0;
}
/* Functions to set page attributes for Region Protection option in the CPU.
* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
*/
static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
{
asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
{
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
/* Make page 0 access raise an exception.
* Also protect some other unused pages so we can catch weirdness.
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection()
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
cpu_write_dtlb(pages_to_protect[i], 0xf);
cpu_write_itlb(pages_to_protect[i], 0xf);
}
cpu_write_dtlb(0x20000000, 0);
cpu_write_itlb(0x20000000, 0);
}
/*
* @brief Set CPU frequency to the value defined in menuconfig
*
* Called from cpu_start.c, not intended to be called from other places.
* This is a temporary function which will be replaced once dynamic
* CPU frequency changing is implemented.
*/
void esp_set_cpu_freq(void);
#endif

22
components/esp32/include/soc/gpio_reg.h
View File

@@ -280,6 +280,28 @@
#define GPIO_SDIO_INT_H_V 0xFF
#define GPIO_SDIO_INT_H_S 0
#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4)
#define GPIO_PIN_INT_ENA 0x0000001F
#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S))
#define GPIO_PIN_INT_ENA_V 0x0000001F
#define GPIO_PIN_INT_ENA_S 13
#define GPIO_PIN_CONFIG 0x00000003
#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S))
#define GPIO_PIN_CONFIG_V 0x00000003
#define GPIO_PIN_CONFIG_S 11
#define GPIO_PIN_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN_WAKEUP_ENABLE_S 10
#define GPIO_PIN_INT_TYPE 0x00000007
#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S))
#define GPIO_PIN_INT_TYPE_V 0x00000007
#define GPIO_PIN_INT_TYPE_S 7
#define GPIO_PIN_PAD_DRIVER (BIT(2))
#define GPIO_PIN_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN_PAD_DRIVER_V 0x1
#define GPIO_PIN_PAD_DRIVER_S 2
#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x0088)
/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt

48
components/esp32/include/soc/gpio_sd_struct.h Normal file
View File

@@ -0,0 +1,48 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SD_STRUCT_H_
#define _SOC_GPIO_SD_STRUCT_H_
typedef volatile struct {
union {
struct {
uint32_t duty: 8;
uint32_t prescale: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} channel[8];
union {
struct {
uint32_t reserved0: 31;
uint32_t clk_en: 1;
};
uint32_t val;
} cg;
union {
struct {
uint32_t reserved0: 31;
uint32_t spi_swap: 1;
};
uint32_t val;
} misc;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} version;
} gpio_sd_dev_t;
extern gpio_sd_dev_t SIGMADELTA;
#endif /* _SOC_GPIO_SD_STRUCT_H_ */

204
components/esp32/include/soc/gpio_struct.h Normal file
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@@ -0,0 +1,204 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_STRUCT_H_
#define _SOC_GPIO_STRUCT_H_
typedef volatile struct {
uint32_t bt_select; /*NA*/
uint32_t out; /*GPIO0~31 output value*/
uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/
uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/
union {
struct {
uint32_t data: 8; /*GPIO32~39 output value*/
uint32_t reserved8: 24;
};
uint32_t val;
} out1;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
} out1_w1ts;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
} out1_w1tc;
union {
struct {
uint32_t sel: 8; /*SDIO PADS on/off control from outside*/
uint32_t reserved8: 24;
};
uint32_t val;
} sdio_select;
uint32_t enable; /*GPIO0~31 output enable*/
uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/
uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/
union {
struct {
uint32_t data: 8; /*GPIO32~39 output enable*/
uint32_t reserved8: 24;
};
uint32_t val;
} enable1;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
} enable1_w1ts;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
} enable1_w1tc;
union {
struct {
uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]} . Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3} . vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */
uint32_t reserved16:16;
};
uint32_t val;
} strap;
uint32_t in; /*GPIO0~31 input value*/
union {
struct {
uint32_t data: 8; /*GPIO32~39 input value*/
uint32_t reserved8: 24;
};
uint32_t val;
} in1;
uint32_t status; /*GPIO0~31 interrupt status*/
uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/
uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/
union {
struct {
uint32_t intr_st: 8; /*GPIO32~39 interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} status1;
union {
struct {
uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
} status1_w1ts;
union {
struct {
uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
} status1_w1tc;
uint32_t reserved_5c;
uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/
uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/
uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/
uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/
uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/
union {
struct {
uint32_t intr: 8; /*GPIO32~39 APP CPU interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} acpu_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} acpu_nmi_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} pcpu_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
} pcpu_nmi_int1;
union {
struct {
uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/
uint32_t reserved8: 24;
};
uint32_t val;
} cpusdio_int1;
union {
struct {
uint32_t reserved0: 2;
uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
uint32_t reserved3: 4;
uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/
uint32_t config: 2; /*NA*/
uint32_t int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
uint32_t reserved18: 14;
};
uint32_t val;
} pin[40];
union {
struct {
uint32_t rtc_max: 10;
uint32_t reserved10: 21;
uint32_t start: 1;
};
uint32_t val;
} cali_conf;
union {
struct {
uint32_t value_sync2: 20;
uint32_t reserved20: 10;
uint32_t rdy_real: 1;
uint32_t rdy_sync2: 1;
};
uint32_t val;
} cali_data;
union {
struct {
uint32_t func_sel: 6; /*select one of the 256 inputs*/
uint32_t sig_in_inv: 1; /*revert the value of the input if you want to revert please set the value to 1*/
uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/
uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/
};
uint32_t val;
} func_in_sel_cfg[256];
union {
struct {
uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/
uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/
uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/
uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/
uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
};
uint32_t val;
} func_out_sel_cfg[40];
} gpio_dev_t;
extern gpio_dev_t GPIO;
#endif /* _SOC_GPIO_STRUCT_H_ */

289
components/esp32/include/soc/i2c_struct.h Normal file
View File

@@ -0,0 +1,289 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2C_STRUCT_H_
#define _SOC_I2C_STRUCT_H_
typedef volatile struct {
union {
struct {
uint32_t scl_low_period:14; /*This register is used to configure the low level width of SCL clock.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_low_period;
union {
struct {
uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/
uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/
uint32_t reserved3: 1;
uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/
uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/
uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/
uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/
uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/
uint32_t reserved9: 23;
};
uint32_t val;
} ctr;
union {
struct {
uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/
uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/
uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/
uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/
uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/
uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/
uint32_t reserved7: 1;
uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/
uint32_t reserved14: 4;
uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/
uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
uint32_t reserved27: 1;
uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/
uint32_t reserved31: 1;
};
uint32_t val;
} status_reg;
union {
struct {
uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data.*/
uint32_t reserved20:12;
};
uint32_t val;
} timeout;
union {
struct {
uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/
uint32_t reserved15: 16;
uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/
};
uint32_t val;
} slave_addr;
union {
struct {
uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/
uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/
uint32_t reserved20: 12;
};
uint32_t val;
} fifo_st;
union {
struct {
uint32_t rx_fifo_full_thrhd: 5;
uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/
uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/
uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/
uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/
uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/
uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
uint32_t reserved26: 6;
};
uint32_t val;
} fifo_conf;
union {
struct {
uint8_t data; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
uint8_t reserved[3];
};
uint32_t val;
} fifo_data;
union {
struct {
uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/
uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/
uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/
uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/
uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/
uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/
uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_status;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
uint32_t reserved10: 22;
};
uint32_t val;
} sda_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
uint32_t reserved10: 22;
};
uint32_t val;
} sda_sample;
union {
struct {
uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_high_period;
uint32_t reserved_3c;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_start_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_rstart_setup;
union {
struct {
uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_stop_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_stop_setup;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
uint32_t en: 1; /*This is the filter enable bit for SCL.*/
uint32_t reserved4: 28;
};
uint32_t val;
} scl_filter_cfg;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
uint32_t en: 1; /*This is the filter enable bit for SDA.*/
uint32_t reserved4: 28;
};
uint32_t val;
} sda_filter_cfg;
union {
struct {
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
uint32_t reserved14: 17;
uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
};
uint32_t val;
} command[16];
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t date; /**/
uint32_t reserved_fc;
uint32_t fifo_start_addr; /*This the start address for ram when use apb nonfifo access.*/
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#endif /* _SOC_I2C_STRUCT_H_ */

461
components/esp32/include/soc/i2s_struct.h Normal file
View File

@@ -0,0 +1,461 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2S_STRUCT_H_
#define _SOC_I2S_STRUCT_H_
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
union {
struct {
uint32_t tx_reset: 1;
uint32_t rx_reset: 1;
uint32_t tx_fifo_reset: 1;
uint32_t rx_fifo_reset: 1;
uint32_t tx_start: 1;
uint32_t rx_start: 1;
uint32_t tx_slave_mod: 1;
uint32_t rx_slave_mod: 1;
uint32_t tx_right_first: 1;
uint32_t rx_right_first: 1;
uint32_t tx_msb_shift: 1;
uint32_t rx_msb_shift: 1;
uint32_t tx_short_sync: 1;
uint32_t rx_short_sync: 1;
uint32_t tx_mono: 1;
uint32_t rx_mono: 1;
uint32_t tx_msb_right: 1;
uint32_t rx_msb_right: 1;
uint32_t sig_loopback: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} conf;
union {
struct {
uint32_t rx_take_data: 1;
uint32_t tx_put_data: 1;
uint32_t rx_wfull: 1;
uint32_t rx_rempty: 1;
uint32_t tx_wfull: 1;
uint32_t tx_rempty: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t out_total_eof: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_take_data: 1;
uint32_t tx_put_data: 1;
uint32_t rx_wfull: 1;
uint32_t rx_rempty: 1;
uint32_t tx_wfull: 1;
uint32_t tx_rempty: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t out_total_eof: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_take_data: 1;
uint32_t tx_put_data: 1;
uint32_t rx_wfull: 1;
uint32_t rx_rempty: 1;
uint32_t tx_wfull: 1;
uint32_t tx_rempty: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t out_total_eof: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t take_data: 1;
uint32_t put_data: 1;
uint32_t rx_wfull: 1;
uint32_t rx_rempty: 1;
uint32_t tx_wfull: 1;
uint32_t tx_rempty: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t out_total_eof: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t tx_bck_in_delay: 2;
uint32_t tx_ws_in_delay: 2;
uint32_t rx_bck_in_delay: 2;
uint32_t rx_ws_in_delay: 2;
uint32_t rx_sd_in_delay: 2;
uint32_t tx_bck_out_delay: 2;
uint32_t tx_ws_out_delay: 2;
uint32_t tx_sd_out_delay: 2;
uint32_t rx_ws_out_delay: 2;
uint32_t rx_bck_out_delay: 2;
uint32_t tx_dsync_sw: 1;
uint32_t rx_dsync_sw: 1;
uint32_t data_enable_delay: 2;
uint32_t tx_bck_in_inv: 1;
uint32_t reserved25: 7;
};
uint32_t val;
} timing;
union {
struct {
uint32_t rx_data_num: 6;
uint32_t tx_data_num: 6;
uint32_t dscr_en: 1;
uint32_t tx_fifo_mod: 3;
uint32_t rx_fifo_mod: 3;
uint32_t tx_fifo_mod_force_en: 1;
uint32_t rx_fifo_mod_force_en: 1;
uint32_t reserved21: 11;
};
uint32_t val;
} fifo_conf;
uint32_t rx_eof_num;
uint32_t conf_single_data;
union {
struct {
uint32_t tx_chan_mod: 3;
uint32_t rx_chan_mod: 2;
uint32_t reserved5: 27;
};
uint32_t val;
} conf_chan;
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t park: 1;
};
uint32_t val;
} out_link;
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t park: 1;
};
uint32_t val;
} in_link;
uint32_t out_eof_des_addr;
uint32_t in_eof_des_addr;
uint32_t out_eof_bfr_des_addr;
union {
struct {
uint32_t mode: 3;
uint32_t reserved3: 1;
uint32_t addr: 2;
uint32_t reserved6: 26;
};
uint32_t val;
} ahb_test;
uint32_t in_link_dscr;
uint32_t in_link_dscr_bf0;
uint32_t in_link_dscr_bf1;
uint32_t out_link_dscr;
uint32_t out_link_dscr_bf0;
uint32_t out_link_dscr_bf1;
union {
struct {
uint32_t in_rst: 1;
uint32_t out_rst: 1;
uint32_t ahbm_fifo_rst: 1;
uint32_t ahbm_rst: 1;
uint32_t out_loop_test: 1;
uint32_t in_loop_test: 1;
uint32_t out_auto_wrback: 1;
uint32_t out_no_restart_clr: 1;
uint32_t out_eof_mode: 1;
uint32_t outdscr_burst_en: 1;
uint32_t indscr_burst_en: 1;
uint32_t out_data_burst_en: 1;
uint32_t check_owner: 1;
uint32_t mem_trans_en: 1;
uint32_t reserved14: 18;
};
uint32_t val;
} lc_conf;
union {
struct {
uint32_t wdata: 9;
uint32_t reserved9: 7;
uint32_t push: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} out_fifo_push;
union {
struct {
uint32_t rdata: 12;
uint32_t reserved12: 4;
uint32_t pop: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} in_fifo_pop;
uint32_t lc_state0;
uint32_t lc_state1;
union {
struct {
uint32_t fifo_timeout: 8;
uint32_t fifo_timeout_shift: 3;
uint32_t fifo_timeout_ena: 1;
uint32_t reserved12: 20;
};
uint32_t val;
} lc_hung_conf;
uint32_t reserved_78;
uint32_t reserved_7c;
union {
struct {
uint32_t y_max:16;
uint32_t y_min:16;
};
uint32_t val;
} cvsd_conf0;
union {
struct {
uint32_t sigma_max:16;
uint32_t sigma_min:16;
};
uint32_t val;
} cvsd_conf1;
union {
struct {
uint32_t cvsd_k: 3;
uint32_t cvsd_j: 3;
uint32_t cvsd_beta: 10;
uint32_t cvsd_h: 3;
uint32_t reserved19:13;
};
uint32_t val;
} cvsd_conf2;
union {
struct {
uint32_t good_pack_max: 6;
uint32_t n_err_seg: 3;
uint32_t shift_rate: 3;
uint32_t max_slide_sample: 8;
uint32_t pack_len_8k: 5;
uint32_t n_min_err: 3;
uint32_t reserved28: 4;
};
uint32_t val;
} plc_conf0;
union {
struct {
uint32_t bad_cef_atten_para: 8;
uint32_t bad_cef_atten_para_shift: 4;
uint32_t bad_ola_win2_para_shift: 4;
uint32_t bad_ola_win2_para: 8;
uint32_t slide_win_len: 8;
};
uint32_t val;
} plc_conf1;
union {
struct {
uint32_t cvsd_seg_mod: 2;
uint32_t min_period: 5;
uint32_t reserved7: 25;
};
uint32_t val;
} plc_conf2;
union {
struct {
uint32_t en: 1;
uint32_t chan_mod: 1;
uint32_t cvsd_dec_pack_err: 1;
uint32_t cvsd_pack_len_8k: 5;
uint32_t cvsd_inf_en: 1;
uint32_t cvsd_dec_start: 1;
uint32_t cvsd_dec_reset: 1;
uint32_t plc_en: 1;
uint32_t plc2dma_en: 1;
uint32_t reserved13: 19;
};
uint32_t val;
} esco_conf0;
union {
struct {
uint32_t with_en: 1;
uint32_t no_en: 1;
uint32_t cvsd_enc_start: 1;
uint32_t cvsd_enc_reset: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} sco_conf0;
union {
struct {
uint32_t tx_pcm_conf: 3;
uint32_t tx_pcm_bypass: 1;
uint32_t rx_pcm_conf: 3;
uint32_t rx_pcm_bypass: 1;
uint32_t tx_stop_en: 1;
uint32_t tx_zeros_rm_en: 1;
uint32_t reserved10: 22;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t fifo_force_pd: 1;
uint32_t fifo_force_pu: 1;
uint32_t plc_mem_force_pd: 1;
uint32_t plc_mem_force_pu: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} pd_conf;
union {
struct {
uint32_t camera_en: 1;
uint32_t lcd_tx_wrx2_en: 1;
uint32_t lcd_tx_sdx2_en: 1;
uint32_t data_enable_test_en: 1;
uint32_t data_enable: 1;
uint32_t lcd_en: 1;
uint32_t ext_adc_start_en: 1;
uint32_t inter_valid_en: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} conf2;
union {
struct {
uint32_t clkm_div_num: 8;
uint32_t clkm_div_b: 6;
uint32_t clkm_div_a: 6;
uint32_t clk_en: 1;
uint32_t clka_en: 1;
uint32_t reserved22: 10;
};
uint32_t val;
} clkm_conf;
union {
struct {
uint32_t tx_bck_div_num: 6;
uint32_t rx_bck_div_num: 6;
uint32_t tx_bits_mod: 6;
uint32_t rx_bits_mod: 6;
uint32_t reserved24: 8;
};
uint32_t val;
} sample_rate_conf;
union {
struct {
uint32_t tx_pdm_en: 1;
uint32_t rx_pdm_en: 1;
uint32_t pcm2pdm_conv_en: 1;
uint32_t pdm2pcm_conv_en: 1;
uint32_t tx_sinc_osr2: 4;
uint32_t tx_prescale: 8;
uint32_t tx_hp_in_shift: 2;
uint32_t tx_lp_in_shift: 2;
uint32_t tx_sinc_in_shift: 2;
uint32_t tx_sigmadelta_in_shift: 2;
uint32_t rx_sinc_dsr_16_en: 1;
uint32_t txhp_bypass: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} pdm_conf;
union {
struct {
uint32_t tx_pdm_fs: 10;
uint32_t tx_pdm_fp: 10;
uint32_t reserved20:12;
};
uint32_t val;
} pdm_freq_conf;
union {
struct {
uint32_t tx_idle: 1;
uint32_t tx_fifo_reset_back: 1;
uint32_t rx_fifo_reset_back: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} state;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
#endif /* _SOC_I2S_STRUCT_H_ */

268
components/esp32/include/soc/io_mux_reg.h
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@@ -40,6 +40,8 @@
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_FUNC_GPIO 2
#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00)
#define CLK_OUT3 0xf
#define CLK_OUT3_S 8
@@ -48,84 +50,17 @@
#define CLK_OUT1 0xf
#define CLK_OUT1_S 0
#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04)
#define FUNC_GPIO36_GPIO36 2
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44)
#define FUNC_GPIO0_EMAC_TX_CLK 5
#define FUNC_GPIO0_GPIO0 2
#define FUNC_GPIO0_CLK_OUT1 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08)
#define FUNC_GPIO37_GPIO37 2
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c)
#define FUNC_GPIO38_GPIO38 2
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10)
#define FUNC_GPIO39_GPIO39 2
#define FUNC_GPIO39_GPIO39_0 0
#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14)
#define FUNC_GPIO34_GPIO34 2
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18)
#define FUNC_GPIO35_GPIO35 2
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c)
#define FUNC_GPIO32_GPIO32 2
#define FUNC_GPIO32_GPIO32_0 0
#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20)
#define FUNC_GPIO33_GPIO33 2
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24)
#define FUNC_GPIO25_EMAC_RXD0 5
#define FUNC_GPIO25_GPIO25 2
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28)
#define FUNC_GPIO26_EMAC_RXD1 5
#define FUNC_GPIO26_GPIO26 2
#define FUNC_GPIO26_GPIO26_0 0
#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c)
#define FUNC_GPIO27_EMAC_RX_DV 5
#define FUNC_GPIO27_GPIO27 2
#define FUNC_GPIO27_GPIO27_0 0
#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30)
#define FUNC_MTMS_EMAC_TXD2 5
#define FUNC_MTMS_SD_CLK 4
#define FUNC_MTMS_HS2_CLk 3
#define FUNC_MTMS_GPIO14 2
#define FUNC_MTMS_HSPICLK 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34)
#define FUNC_MTDI_EMAC_TXD3 5
#define FUNC_MTDI_SD_DATA2 4
#define FUNC_MTDI_HS2_DATA2 3
#define FUNC_MTDI_GPIO12 2
#define FUNC_MTDI_HSPIQ 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38)
#define FUNC_MTCK_EMAC_RX_ER 5
#define FUNC_MTCK_SD_DATA3 4
#define FUNC_MTCK_HS2_DATA3 3
#define FUNC_MTCK_GPIO13 2
#define FUNC_MTCK_HSPID 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c)
#define FUNC_MTDO_EMAC_RXD3 5
#define FUNC_MTDO_SD_CMD 4
#define FUNC_MTDO_HS2_CMD 3
#define FUNC_MTDO_GPIO15 2
#define FUNC_MTDO_HSPICS0 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88)
#define FUNC_U0TXD_EMAC_RXD2 3
#define FUNC_U0TXD_GPIO1 2
#define FUNC_U0TXD_CLK_OUT3 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40)
#define FUNC_GPIO2_SD_DATA0 4
@@ -134,11 +69,10 @@
#define FUNC_GPIO2_HSPIWP 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44)
#define FUNC_GPIO0_EMAC_TX_CLK 5
#define FUNC_GPIO0_GPIO0 2
#define FUNC_GPIO0_CLK_OUT1 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84)
#define FUNC_U0RXD_GPIO3 2
#define FUNC_U0RXD_CLK_OUT2 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48)
#define FUNC_GPIO4_EMAC_TX_ER 5
@@ -148,40 +82,12 @@
#define FUNC_GPIO4_HSPIHD 1
#define FUNC_GPIO4_GPIO4_0 0
#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c)
#define FUNC_GPIO16_EMAC_CLK_OUT 5
#define FUNC_GPIO16_U2RXD 4
#define FUNC_GPIO16_HS1_DATA4 3
#define FUNC_GPIO16_GPIO16 2
#define FUNC_GPIO16_GPIO16_0 0
#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50)
#define FUNC_GPIO17_EMAC_CLK_OUT_180 5
#define FUNC_GPIO17_U2TXD 4
#define FUNC_GPIO17_HS1_DATA5 3
#define FUNC_GPIO17_GPIO17 2
#define FUNC_GPIO17_GPIO17_0 0
#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54)
#define FUNC_SD_DATA2_U1RXD 4
#define FUNC_SD_DATA2_HS1_DATA2 3
#define FUNC_SD_DATA2_GPIO9 2
#define FUNC_SD_DATA2_SPIHD 1
#define FUNC_SD_DATA2_SD_DATA2 0
#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58)
#define FUNC_SD_DATA3_U1TXD 4
#define FUNC_SD_DATA3_HS1_DATA3 3
#define FUNC_SD_DATA3_GPIO10 2
#define FUNC_SD_DATA3_SPIWP 1
#define FUNC_SD_DATA3_SD_DATA3 0
#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c)
#define FUNC_SD_CMD_U1RTS 4
#define FUNC_SD_CMD_HS1_CMD 3
#define FUNC_SD_CMD_GPIO11 2
#define FUNC_SD_CMD_SPICS0 1
#define FUNC_SD_CMD_SD_CMD 0
#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c)
#define FUNC_GPIO5_EMAC_RX_CLK 5
#define FUNC_GPIO5_HS1_DATA6 3
#define FUNC_GPIO5_GPIO5 2
#define FUNC_GPIO5_VSPICS0 1
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60)
#define FUNC_SD_CLK_U1CTS 4
@@ -204,12 +110,72 @@
#define FUNC_SD_DATA1_SPID 1
#define FUNC_SD_DATA1_SD_DATA1 0
#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c)
#define FUNC_GPIO5_EMAC_RX_CLK 5
#define FUNC_GPIO5_HS1_DATA6 3
#define FUNC_GPIO5_GPIO5 2
#define FUNC_GPIO5_VSPICS0 1
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54)
#define FUNC_SD_DATA2_U1RXD 4
#define FUNC_SD_DATA2_HS1_DATA2 3
#define FUNC_SD_DATA2_GPIO9 2
#define FUNC_SD_DATA2_SPIHD 1
#define FUNC_SD_DATA2_SD_DATA2 0
#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58)
#define FUNC_SD_DATA3_U1TXD 4
#define FUNC_SD_DATA3_HS1_DATA3 3
#define FUNC_SD_DATA3_GPIO10 2
#define FUNC_SD_DATA3_SPIWP 1
#define FUNC_SD_DATA3_SD_DATA3 0
#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c)
#define FUNC_SD_CMD_U1RTS 4
#define FUNC_SD_CMD_HS1_CMD 3
#define FUNC_SD_CMD_GPIO11 2
#define FUNC_SD_CMD_SPICS0 1
#define FUNC_SD_CMD_SD_CMD 0
#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34)
#define FUNC_MTDI_EMAC_TXD3 5
#define FUNC_MTDI_SD_DATA2 4
#define FUNC_MTDI_HS2_DATA2 3
#define FUNC_MTDI_GPIO12 2
#define FUNC_MTDI_HSPIQ 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38)
#define FUNC_MTCK_EMAC_RX_ER 5
#define FUNC_MTCK_SD_DATA3 4
#define FUNC_MTCK_HS2_DATA3 3
#define FUNC_MTCK_GPIO13 2
#define FUNC_MTCK_HSPID 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30)
#define FUNC_MTMS_EMAC_TXD2 5
#define FUNC_MTMS_SD_CLK 4
#define FUNC_MTMS_HS2_CLk 3
#define FUNC_MTMS_GPIO14 2
#define FUNC_MTMS_HSPICLK 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c)
#define FUNC_MTDO_EMAC_RXD3 5
#define FUNC_MTDO_SD_CMD 4
#define FUNC_MTDO_HS2_CMD 3
#define FUNC_MTDO_GPIO15 2
#define FUNC_MTDO_HSPICS0 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c)
#define FUNC_GPIO16_EMAC_CLK_OUT 5
#define FUNC_GPIO16_U2RXD 4
#define FUNC_GPIO16_HS1_DATA4 3
#define FUNC_GPIO16_GPIO16 2
#define FUNC_GPIO16_GPIO16_0 0
#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50)
#define FUNC_GPIO17_EMAC_CLK_OUT_180 5
#define FUNC_GPIO17_U2TXD 4
#define FUNC_GPIO17_HS1_DATA5 3
#define FUNC_GPIO17_GPIO17 2
#define FUNC_GPIO17_GPIO17_0 0
#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70)
#define FUNC_GPIO18_HS1_DATA7 3
@@ -241,17 +207,6 @@
#define FUNC_GPIO22_VSPIWP 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84)
#define FUNC_U0RXD_GPIO3 2
#define FUNC_U0RXD_CLK_OUT2 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88)
#define FUNC_U0TXD_EMAC_RXD2 3
#define FUNC_U0TXD_GPIO1 2
#define FUNC_U0TXD_CLK_OUT3 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO23_HS1_STROBE 3
#define FUNC_GPIO23_GPIO23 2
@@ -262,4 +217,51 @@
#define FUNC_GPIO24_GPIO24 2
#define FUNC_GPIO24_GPIO24_0 0
#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24)
#define FUNC_GPIO25_EMAC_RXD0 5
#define FUNC_GPIO25_GPIO25 2
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28)
#define FUNC_GPIO26_EMAC_RXD1 5
#define FUNC_GPIO26_GPIO26 2
#define FUNC_GPIO26_GPIO26_0 0
#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c)
#define FUNC_GPIO27_EMAC_RX_DV 5
#define FUNC_GPIO27_GPIO27 2
#define FUNC_GPIO27_GPIO27_0 0
#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c)
#define FUNC_GPIO32_GPIO32 2
#define FUNC_GPIO32_GPIO32_0 0
#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20)
#define FUNC_GPIO33_GPIO33 2
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14)
#define FUNC_GPIO34_GPIO34 2
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18)
#define FUNC_GPIO35_GPIO35 2
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04)
#define FUNC_GPIO36_GPIO36 2
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08)
#define FUNC_GPIO37_GPIO37 2
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c)
#define FUNC_GPIO38_GPIO38 2
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10)
#define FUNC_GPIO39_GPIO39 2
#define FUNC_GPIO39_GPIO39_0 0
#endif /* _SOC_IO_MUX_REG_H_ */

240
components/esp32/include/soc/ledc_struct.h Normal file
View File

@@ -0,0 +1,240 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_LEDC_STRUCT_H_
#define _SOC_LEDC_STRUCT_H_
typedef volatile struct {
struct {
struct {
union {
struct {
uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/
uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/
uint32_t reserved4: 27;
uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
uint32_t reserved20: 12;
};
uint32_t val;
} hpoint;
union {
struct {
uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
uint32_t reserved25: 7;
};
uint32_t val;
} duty;
union {
struct {
uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/
uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/
uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/
uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/
uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/
uint32_t reserved25: 7;
};
uint32_t val;
} duty_rd;
} channel[8];
} channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
struct {
struct {
union {
struct {
uint32_t bit_num: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/
uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/
uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/
uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/
uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/
uint32_t reserved26: 5;
};
uint32_t val;
} conf;
union {
struct {
uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/
uint32_t reserved20: 12;
};
uint32_t val;
} value;
} timer[4];
} timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/
uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/
uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/
uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/
uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/
uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/
uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/
uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/
uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/
uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/
uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/
uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/
uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/
uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/
uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/
uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/
uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/
uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/
uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/
uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/
uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/
uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/
uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/
uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/
uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/
uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/
uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/
uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/
uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/
uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/
uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/
uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/
uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t apb_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/
uint32_t reserved1: 31;
};
uint32_t val;
} conf;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t date; /*This register represents the version .*/
} ledc_dev_t;
extern ledc_dev_t LEDC;
#endif /* _SOC_LEDC_STRUCT_H_ */

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components/esp32/include/soc/pcnt_struct.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_PCNT_STRUCT_H_
#define _SOC_PCNT_STRUCT_H_
typedef volatile struct {
struct{
union {
struct {
uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/
uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/
uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/
uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/
uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/
uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/
uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/
uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/
uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/
};
uint32_t val;
} conf2;
} conf_unit[8];
union {
struct {
uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/
uint32_t reserved16: 16;
};
uint32_t val;
} cnt_unit[8];
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/
uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/
uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/
uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/
uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/
uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/
uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/
uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_clr;
uint32_t status_unit[8];
union {
struct {
uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/
uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/
uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/
uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/
uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/
uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/
uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/
uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/
uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/
uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/
uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/
uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/
uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/
uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/
uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/
uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/
uint32_t clk_en: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} ctrl;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#endif /* _SOC_PCNT_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RMT_STRUCT_H_
#define _SOC_RMT_STRUCT_H_
typedef volatile struct {
uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/
struct{
union {
struct {
uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/
uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/
uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/
uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/
uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/
uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/
uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/
uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/
uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/
uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/
uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/
uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/
uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/
uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/
uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/
uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/
uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/
uint32_t reserved20: 12;
};
uint32_t val;
} conf1;
} conf_ch[8];
uint32_t status_ch[8]; /*The status for channel0-7*/
uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/
union {
struct {
uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/
uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
uint32_t ch1_rx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/
uint32_t ch1_err: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/
uint32_t ch2_tx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/
uint32_t ch2_rx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/
uint32_t ch2_err: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/
uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
uint32_t ch3_err: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/
uint32_t ch4_tx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/
uint32_t ch4_rx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/
uint32_t ch4_err: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/
uint32_t ch5_tx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/
uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
uint32_t ch6_tx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/
uint32_t ch6_rx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/
uint32_t ch6_err: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/
uint32_t ch7_tx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/
uint32_t ch7_rx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/
uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch1_tx_thr_event: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch2_tx_thr_event: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch3_tx_thr_event: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch5_tx_thr_event: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch6_tx_thr_event: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/
uint32_t ch0_err: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/
uint32_t ch1_tx_end: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/
uint32_t ch1_rx_end: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/
uint32_t ch1_err: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/
uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/
uint32_t ch2_err: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/
uint32_t ch3_tx_end: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/
uint32_t ch3_rx_end: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/
uint32_t ch3_err: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/
uint32_t ch4_tx_end: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/
uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/
uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/
uint32_t ch5_tx_end: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/
uint32_t ch5_rx_end: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/
uint32_t ch5_err: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/
uint32_t ch6_tx_end: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/
uint32_t ch6_rx_end: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/
uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/
uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/
uint32_t ch7_rx_end: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/
uint32_t ch7_err: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/
uint32_t ch0_tx_thr_event: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/
uint32_t ch1_tx_thr_event: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/
uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/
uint32_t ch4_tx_thr_event: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/
uint32_t ch5_tx_thr_event: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/
uint32_t ch6_tx_thr_event: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/
uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
uint32_t ch0_err: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/
uint32_t ch1_tx_end: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/
uint32_t ch1_rx_end: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/
uint32_t ch1_err: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/
uint32_t ch2_tx_end: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/
uint32_t ch2_rx_end: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/
uint32_t ch2_err: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/
uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/
uint32_t ch4_tx_end: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/
uint32_t ch4_rx_end: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/
uint32_t ch4_err: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/
uint32_t ch5_tx_end: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/
uint32_t ch5_rx_end: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/
uint32_t ch5_err: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/
uint32_t ch6_tx_end: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/
uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/
uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
uint32_t ch7_rx_end: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/
uint32_t ch7_err: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/
uint32_t ch0_tx_thr_event: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
uint32_t ch1_tx_thr_event: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
uint32_t ch2_tx_thr_event: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
uint32_t ch3_tx_thr_event: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
uint32_t ch4_tx_thr_event: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
uint32_t ch0_err: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/
uint32_t ch1_tx_end: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
uint32_t ch1_rx_end: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
uint32_t ch1_err: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/
uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/
uint32_t ch3_tx_end: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
uint32_t ch3_rx_end: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
uint32_t ch3_err: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/
uint32_t ch4_tx_end: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
uint32_t ch4_rx_end: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
uint32_t ch4_err: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/
uint32_t ch5_tx_end: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/
uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
uint32_t ch6_rx_end: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
uint32_t ch6_err: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/
uint32_t ch7_tx_end: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
uint32_t ch7_rx_end: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
uint32_t ch7_err: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/
uint32_t ch0_tx_thr_event: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/
uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/
uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/
uint32_t ch3_tx_thr_event: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/
uint32_t ch4_tx_thr_event: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/
uint32_t ch5_tx_thr_event: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/
uint32_t ch6_tx_thr_event: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/
uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/
uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/
};
uint32_t val;
} carrier_duty_ch[8];
union {
struct {
uint32_t limit: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/
uint32_t reserved9: 23;
};
uint32_t val;
} tx_lim_ch[8];
union {
struct {
uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/
uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
uint32_t reserved2: 30;
};
uint32_t val;
} apb_conf;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /*This is the version register.*/
} rmt_dev_t;
extern rmt_dev_t RMT;
//Allow access to RMT memory using RMTMEM.chan[0].data[8]
typedef volatile struct {
struct {
union {
struct {
uint32_t level1: 1;
uint32_t duration1: 15;
uint32_t level0: 1;
uint32_t duration0: 15;
};
uint32_t val;
} data[64];
} chan[8];
} rmt_mem_t;
extern rmt_mem_t RMTMEM;
#endif /* _SOC_RMT_STRUCT_H_ */

6
components/esp32/include/soc/soc.h
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@@ -260,14 +260,14 @@
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host Reserved
* 1 1 extern level BT/BLE Host VHCI Reserved
* 2 1 extern level FROM_CPU FROM_CPU
* 3 1 extern level TG0_WDT Reserved
* 4 1 extern level WBB
* 5 1 extern level Reserved
* 5 1 extern level BT Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software Reserved Reserved
* 8 1 extern level Reserved
* 8 1 extern level BLE Controller
* 9 1 extern level
* 10 1 extern edge Internal Timer
* 11 3 profiling

677
components/esp32/include/soc/spi_struct.h Normal file
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@@ -0,0 +1,677 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
typedef volatile struct {
union {
struct {
uint32_t reserved0: 16; /*reserved*/
uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
};
uint32_t val;
} cmd;
union {
struct {
uint32_t reserved : 8;
uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/
};
uint32_t val;
} addr;
union {
struct {
uint32_t reserved0: 10; /*reserved*/
uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/
uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/
uint32_t reserved16: 4; /*reserved*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/
uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
uint32_t reserved27: 5; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t reserved0: 16; /*reserved*/
uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/
uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/
};
uint32_t val;
} rd_status;
union {
struct {
uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/
uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/
uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/
uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/
uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/
uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/
uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/
uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/
uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
};
uint32_t val;
} clock;
union {
struct {
uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/
uint32_t reserved1: 3; /*reserved*/
uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/
uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/
uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_t reserved8: 2; /*reserved*/
uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/
uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t reserved8: 18; /*reserved*/
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value: 16; /*The value of command.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} miso_dlen;
uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/
union {
struct {
uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/
uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/
uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
uint32_t reserved3: 2; /*reserved*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/
uint32_t master_cs_pol: 5; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
uint32_t master_ck_sel: 5; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
uint32_t reserved16: 13; /*reserved*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} pin;
union {
struct {
uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/
uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/
uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/
uint32_t reserved12: 5; /*reserved*/
uint32_t last_command: 3; /*In the slave mode it is the value of command.*/
uint32_t last_state: 3; /*In the slave mode it is the state of spi state machine.*/
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/
uint32_t cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
uint32_t wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/
uint32_t wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/
uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/
uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/
uint32_t wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/
uint32_t rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/
uint32_t wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/
uint32_t wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/
uint32_t rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/
uint32_t reserved16: 9; /*reserved*/
uint32_t status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/
uint32_t status_fast_en: 1; /*In the slave mode enable fast read status.*/
uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/
};
uint32_t val;
} slave1;
union {
struct {
uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/
uint32_t wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/
uint32_t rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/
uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
};
uint32_t val;
} slave2;
union {
struct {
uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/
uint32_t wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/
uint32_t rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/
uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/
};
uint32_t val;
} slave3;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} slv_wrbuf_dlen;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} slv_rdbuf_dlen;
union {
struct {
uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
uint32_t flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/
uint32_t reserved4: 28; /*reserved*/
};
uint32_t val;
} cache_fctrl;
union {
struct {
uint32_t reserved0: 1; /*reserved*/
uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/
uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/
uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/
uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/
uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/
uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/
uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/
uint32_t reserved29: 3; /*reserved*/
};
uint32_t val;
} cache_sctrl;
union {
struct {
uint32_t dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
uint32_t qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/
uint32_t rst_io: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/
uint32_t reserved5:27; /*reserved*/
};
uint32_t val;
} sram_cmd;
union {
struct {
uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_dwr_cmd;
union {
struct {
uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} slv_rd_bit;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t data_buf[16]; /*data buffer*/
uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
union {
struct {
uint32_t t_pp_time: 12; /*page program delay time by system clock.*/
uint32_t reserved12: 4; /*reserved*/
uint32_t t_pp_shift: 4; /*page program delay time shift .*/
uint32_t reserved20:11; /*reserved*/
uint32_t t_pp_ena: 1; /*page program delay enable.*/
};
uint32_t val;
} ext0;
union {
struct {
uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/
uint32_t reserved12: 4; /*reserved*/
uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/
uint32_t reserved20: 11; /*reserved*/
uint32_t t_erase_ena: 1; /*erase flash delay enable.*/
};
uint32_t val;
} ext1;
union {
struct {
uint32_t st: 3; /*The status of spi state machine .*/
uint32_t reserved3: 29; /*reserved*/
};
uint32_t val;
} ext2;
union {
struct {
uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/
uint32_t reserved2: 30; /*reserved*/
};
uint32_t val;
} ext3;
union {
struct {
uint32_t reserved0: 2; /*reserved*/
uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/
uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/
uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/
uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/
uint32_t in_loop_test: 1; /*Set bit to test in link.*/
uint32_t out_loop_test: 1; /*Set bit to test out link.*/
uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/
uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/
uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/
uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/
uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/
uint32_t reserved13: 1; /*reserved*/
uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/
uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/
uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/
uint32_t reserved17: 15; /*reserved*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t addr: 20; /*The address of the first outlink descriptor.*/
uint32_t reserved20: 8; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*The address of the first inlink descriptor.*/
uint32_t auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/
uint32_t reserved21: 7; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t rx_en: 1; /*spi dma read data status bit.*/
uint32_t tx_en: 1; /*spi dma write data status bit.*/
uint32_t reserved2: 30; /*spi dma read data from memory count.*/
};
uint32_t val;
} dma_status;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_raw;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The status bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_clr;
uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/
uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/
uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/
uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/
uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/
uint32_t dma_rx_status; /*spi dma read data from memory status.*/
uint32_t dma_tx_status; /*spi dma write data to memory status.*/
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
union {
struct {
uint32_t date: 28; /*SPI register version.*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/
extern spi_dev_t SPI1;
extern spi_dev_t SPI2;
extern spi_dev_t SPI3;
#endif /* _SOC_SPI_STRUCT_H_ */

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components/esp32/include/soc/timer_group_struct.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_STRUCT_H_
#define _SOC_TIMG_STRUCT_H_
typedef volatile struct {
struct{
union {
struct {
uint32_t reserved0: 10;
uint32_t alarm_en: 1; /*When set alarm is enabled*/
uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/
uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/
uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/
uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/
uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/
uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
};
uint32_t val;
} config;
uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/
} hw_timer[2];
union {
struct {
uint32_t reserved0: 14;
uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/
uint32_t sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
uint32_t cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/
uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/
uint32_t stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
uint32_t stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
uint32_t stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
uint32_t stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
uint32_t en: 1; /*When set SWDT is enabled*/
};
uint32_t val;
} wdt_config0;
union {
struct {
uint32_t reserved0: 16;
uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
};
uint32_t val;
} wdt_config1;
uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/
uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/
uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/
uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/
uint32_t wdt_feed; /*Write any value will feed SWDT*/
uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/
union {
struct {
uint32_t reserved0: 12;
uint32_t start_cycling: 1;
uint32_t clk_sel: 2;
uint32_t rdy: 1;
uint32_t max: 15;
uint32_t start: 1;
};
uint32_t val;
} rtc_cali_cfg;
union {
struct {
uint32_t reserved0: 7;
uint32_t value:25;
};
uint32_t val;
} rtc_cali_cfg1;
union {
struct {
uint32_t reserved0: 7;
uint32_t rtc_only: 1;
uint32_t cpst_en: 1;
uint32_t lac_en: 1;
uint32_t alarm_en: 1;
uint32_t level_int_en: 1;
uint32_t edge_int_en: 1;
uint32_t divider: 16;
uint32_t autoreload: 1;
uint32_t increase: 1;
uint32_t en: 1;
};
uint32_t val;
} lactconfig;
union {
struct {
uint32_t reserved0: 6;
uint32_t step_len:26;
};
uint32_t val;
} lactrtc;
uint32_t lactlo; /**/
uint32_t lacthi; /**/
uint32_t lactupdate; /**/
uint32_t lactalarmlo; /**/
uint32_t lactalarmhi; /**/
uint32_t lactloadlo; /**/
uint32_t lactloadhi; /**/
uint32_t lactload; /**/
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
uint32_t t1: 1; /*interrupt when timer1 alarm*/
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
uint32_t t1: 1; /*interrupt when timer1 alarm*/
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
uint32_t lact: 1;
uint32_t reserved4:28;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
uint32_t t1: 1; /*interrupt when timer1 alarm*/
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_st_timers;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
uint32_t t1: 1; /*interrupt when timer1 alarm*/
uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_clr_timers;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
union {
struct {
uint32_t date:28; /*Version of this regfile*/
uint32_t reserved28: 4;
};
uint32_t val;
} timg_date;
union {
struct {
uint32_t reserved0: 31;
uint32_t en: 1; /*Force clock enable for this regfile*/
};
uint32_t val;
} clk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#endif /* _SOC_TIMG_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_UART_STRUCT_H_
#define _SOC_UART_STRUCT_H_
typedef volatile struct {
union {
struct {
uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
uint8_t reserved[3];
};
uint32_t val;
} fifo;
union {
struct {
uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/
uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/
uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/
uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/
uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/
uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/
uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/
uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/
uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/
uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/
uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/
uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/
uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/
uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/
uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/
uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/
uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/
uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/
uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/
uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/
uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/
uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/
uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/
uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/
uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/
uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/
uint32_t reserved24: 8;
};
uint32_t val;
} clk_div;
union {
struct {
uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/
uint32_t reserved1: 7;
uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/
uint32_t reserved16: 16;
};
uint32_t val;
} auto_baud;
union {
struct {
uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/
uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/
uint32_t reserved12: 1;
uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/
uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/
uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/
uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/
uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/
uint32_t reserved28: 1;
uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/
uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/
uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/
};
uint32_t val;
} status;
union {
struct {
uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/
uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/
uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/
uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/
uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/
uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/
uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/
uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/
uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/
uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/
uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/
uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/
uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/
uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/
uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/
uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/
uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/
uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/
uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/
uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/
uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/
uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/
uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/
uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/
uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/
uint32_t reserved28: 4;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/
uint32_t reserved7: 1;
uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/
uint32_t reserved15: 1;
uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/
uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/
uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/
uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} lowpulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
uint32_t reserved10: 22;
};
uint32_t val;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/
uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/
uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/
uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/
uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/
uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/
uint32_t reserved6: 26;
};
uint32_t val;
} flow_conf;
union {
struct {
uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/
uint32_t reserved10: 22;
};
uint32_t val;
} sleep_conf;
union {
struct {
uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/
uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/
uint32_t xon_char: 8; /*This register stores the xon flow control char.*/
uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/
};
uint32_t val;
} swfc_conf;
union {
struct {
uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/
uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/
uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/
uint32_t reserved28: 4;
};
uint32_t val;
} idle_conf;
union {
struct {
uint32_t en: 1; /*Set this bit to choose rs485 mode.*/
uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/
uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/
uint32_t reserved10: 22;
};
uint32_t val;
} rs485_conf;
union {
struct {
uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_gaptout;
union {
struct {
uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/
uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/
uint32_t reserved1: 1;
uint32_t reserved2: 1;
uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/
uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/
uint32_t reserved11: 4;
uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/
uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/
uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/
uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/
uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/
uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/
uint32_t reserved31: 1;
};
uint32_t val;
} mem_conf;
union {
struct {
uint32_t status:24;
uint32_t reserved24: 8;
};
uint32_t val;
} mem_tx_status;
union {
struct {
uint32_t status:24;
uint32_t reserved24: 8;
};
uint32_t val;
} mem_rx_status;
union {
struct {
uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/
uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/
uint32_t reserved6: 26;
};
uint32_t val;
} mem_cnt_status;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} pospulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} negpulse;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t date; /**/
uint32_t id; /**/
} uart_dev_t;
extern uart_dev_t UART0;
extern uart_dev_t UART1;
extern uart_dev_t UART2;
#endif /* _SOC_UART_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_UHCI_STRUCT_H_
#define _SOC_UHCI_STRUCT_H_
typedef volatile struct {
union {
struct {
uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/
uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/
uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/
uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/
uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/
uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/
uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/
uint32_t out_no_restart_clr: 1; /*don't use*/
uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/
uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/
uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/
uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/
uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/
uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/
uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/
uint32_t mem_trans_en: 1;
uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/
uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/
uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/
uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/
uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/
uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/
uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/
uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/
uint32_t reserved24: 8;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/
uint32_t tx_start: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/
uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/
uint32_t in_done: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/
uint32_t in_suc_eof: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/
uint32_t in_err_eof: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/
uint32_t out_done: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/
uint32_t out_eof: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/
uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/
uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/
uint32_t in_dscr_empty: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/
uint32_t outlink_eof_err: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/
uint32_t out_total_eof: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/
uint32_t send_s_q: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/
uint32_t send_a_q: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/
uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/
uint32_t reserved2: 30;
};
uint32_t val;
} dma_out_status;
union {
struct {
uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/
uint32_t reserved9: 7;
uint32_t fifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/
uint32_t reserved17:15;
};
uint32_t val;
} dma_out_push;
union {
struct {
uint32_t full: 1;
uint32_t empty: 1;
uint32_t reserved2: 2;
uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/
uint32_t reserved7: 25;
};
uint32_t val;
} dma_in_status;
union {
struct {
uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/
uint32_t reserved12: 4;
uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/
uint32_t reserved17: 15;
};
uint32_t val;
} dma_in_pop;
union {
struct {
uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/
uint32_t reserved20: 8;
uint32_t stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/
uint32_t start: 1; /*Set this bit to start dealing with the out link descriptors.*/
uint32_t restart: 1; /*Set this bit to mount on new out link descriptors*/
uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/
uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/
uint32_t reserved21: 7;
uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/
uint32_t start: 1; /*Set this bit to start dealing with the in link descriptors.*/
uint32_t restart: 1; /*Set this bit to mount on new in link descriptors*/
uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/
uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/
uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/
uint32_t save_head: 1; /*Set this bit to save packet header .*/
uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/
uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/
uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/
uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/
uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/
uint32_t dma_in_fifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/
uint32_t reserved21: 11;
};
uint32_t val;
} conf1;
uint32_t state0; /**/
uint32_t state1; /**/
uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/
uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/
uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/
uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/
union {
struct {
uint32_t test_mode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
uint32_t reserved3: 1;
uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/
uint32_t reserved6: 26;
};
uint32_t val;
} ahb_test;
uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/
uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/
uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/
uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/
uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/
uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/
union {
struct {
uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/
uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/
uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/
uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/
uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/
uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/
uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/
uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/
uint32_t reserved8: 24;
};
uint32_t val;
} escape_conf;
union {
struct {
uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/
uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/
uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/
uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/
uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/
uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/
uint32_t reserved24: 8;
};
uint32_t val;
} hung_conf;
uint32_t ack_num; /**/
uint32_t rx_head; /*This register stores the packet header received by DMA*/
union {
struct {
uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/
uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/
uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/
uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/
uint32_t reserved8: 24;
};
uint32_t val;
} quick_sent;
struct{
uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
} q_data[7];
union {
struct {
uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/
uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/
uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf0;
union {
struct {
uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/
uint32_t seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/
uint32_t seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf1;
union {
struct {
uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/
uint32_t seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/
uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf2;
union {
struct {
uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/
uint32_t seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/
uint32_t seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf3;
union {
struct {
uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/
uint32_t reserved13:19;
};
uint32_t val;
} pkt_thres;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /*version information*/
} uhci_dev_t;
extern uhci_dev_t UHCI0;
extern uhci_dev_t UHCI1;
#endif /* _SOC_UHCI_STRUCT_H_ */

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components/esp32/ld/esp32.bt.ld
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x40000 /* Shared RAM, minus rom bss/data/stack.*/
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
}
_heap_end = 0x40000000;

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components/esp32/ld/esp32.bt.trace.ld
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x38000 /* Shared RAM, minus rom bss/data/stack.*/
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
}
_heap_end = 0x3FFF8000;

18
components/esp32/ld/esp32.common.ld
View File

@@ -1,5 +1,5 @@
/* Default entry point: */
ENTRY(call_user_start_cpu0);
ENTRY(call_start_cpu0);
SECTIONS
{
@@ -102,7 +102,7 @@ SECTIONS
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
@@ -132,7 +132,7 @@ SECTIONS
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
@@ -153,4 +153,16 @@ SECTIONS
_text_end = ABSOLUTE(.);
_etext = .;
} >iram0_2_seg
.rtc.text :
{
. = ALIGN(4);
*(.rtc.literal .rtc.text)
} >rtc_iram_seg
.rtc.data :
{
*(.rtc.data)
*(.rtc.rodata)
} > rtc_slow_seg
}

53
components/esp32/ld/esp32.ld
View File

@@ -1,14 +1,55 @@
/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
/* ESP32 Linker Script Memory Layout
This file describes the memory layout (memory blocks) as virtual
memory addresses.
esp32.common.ld contains output sections to link compiler output
into these memory blocks.
***
This linker script is passed through the C preprocessor to include
configuration options.
Please use preprocessor features sparingly! Restrict
to simple macros with numeric values, and/or #if/#endif blocks.
*/
#include "sdkconfig.h"
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x50000 /* Shared RAM, minus rom bss/data/stack.*/
/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
/* Even though the segment name is iram, it is actually mapped to flash */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
Enabling Bluetooth & Trace Memory features in menuconfig will decrease
the amount of RAM available.
*/
dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM
/* Flash mapped constant data */
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
/* RTC fast memory (executable). Persists over deep sleep.
*/
rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
/* RTC slow memory (data accessible). Persists over deep sleep.
Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
}
_heap_end = 0x40000000;
/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;

21
components/esp32/ld/esp32.peripherals.ld Normal file
View File

@@ -0,0 +1,21 @@
PROVIDE ( UART0 = 0x3ff40000 );
PROVIDE ( SPI1 = 0x3ff42000 );
PROVIDE ( SPI0 = 0x3ff43000 );
PROVIDE ( GPIO = 0x3ff44000 );
PROVIDE ( SIGMADELTA = 0x3ff44f00 );
PROVIDE ( UHCI1 = 0x3ff4C000 );
PROVIDE ( I2S0 = 0x3ff4F000 );
PROVIDE ( UART1 = 0x3ff50000 );
PROVIDE ( I2C0 = 0x3ff53000 );
PROVIDE ( UHCI0 = 0x3ff54000 );
PROVIDE ( RMT = 0x3ff56000 );
PROVIDE ( RMTMEM = 0x3ff56800 );
PROVIDE ( PCNT = 0x3ff57000 );
PROVIDE ( LEDC = 0x3ff59000 );
PROVIDE ( TIMERG0 = 0x3ff5F000 );
PROVIDE ( TIMERG1 = 0x3ff60000 );
PROVIDE ( SPI2 = 0x3ff64000 );
PROVIDE ( SPI3 = 0x3ff65000 );
PROVIDE ( I2C1 = 0x3ff67000 );
PROVIDE ( I2S1 = 0x3ff6D000 );
PROVIDE ( UART2 = 0x3ff6E000 );

8
components/esp32/ld/esp32.rom.ld
View File

@@ -99,6 +99,10 @@ PROVIDE ( _data_end = 0x4000d5c8 );
PROVIDE ( _data_end_btdm_rom = 0x4000d4f8 );
PROVIDE ( _data_start = 0x4000d4f8 );
PROVIDE ( _data_start_btdm_rom = 0x4000d4f4 );
PROVIDE ( _data_start_btdm = 0x3ffae6e0);
PROVIDE ( _data_end_btdm = 0x3ffaff10);
PROVIDE ( _bss_start_btdm = 0x3ffb8000);
PROVIDE ( _bss_end_btdm = 0x3ffbff70);
PROVIDE ( _daylight = 0x3ffae0a4 );
PROVIDE ( dbg_default_handler = 0x3ff97218 );
PROVIDE ( dbg_state = 0x3ffb8d5d );
@@ -445,7 +449,6 @@ PROVIDE ( _lseek_r = 0x4000bd8c );
PROVIDE ( __lshrdi3 = 0x4000c84c );
PROVIDE ( __ltdf2 = 0x40063790 );
PROVIDE ( __ltsf2 = 0x4006342c );
PROVIDE ( main = 0x400076c4 );
PROVIDE ( malloc = 0x4000bea0 );
PROVIDE ( _malloc_r = 0x4000bbb4 );
PROVIDE ( maxSecretKey_256 = 0x3ff97448 );
@@ -1378,6 +1381,7 @@ PROVIDE ( rom_iq_est_disable = 0x40005590 );
PROVIDE ( rom_iq_est_enable = 0x40005514 );
PROVIDE ( rom_linear_to_db = 0x40005f64 );
PROVIDE ( rom_loopback_mode_en = 0x400030f8 );
PROVIDE ( rom_main = 0x400076c4 );
PROVIDE ( rom_meas_tone_pwr_db = 0x40006004 );
PROVIDE ( rom_mhz2ieee = 0x4000404c );
PROVIDE ( rom_noise_floor_auto_set = 0x40003bdc );
@@ -1835,5 +1839,3 @@ PROVIDE ( _xtos_syscall_handler = 0x40000790 );
PROVIDE ( _xtos_unhandled_exception = 0x4000c024 );
PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c );
PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 );
PROVIDE ( I2S0 = 0x6000F000 );

14
components/esp32/ld/esp32.trace.ld
View File

@@ -1,14 +0,0 @@
/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x48000 /* Shared RAM, minus rom bss/data/stack.*/
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
}
_heap_end = 0x3FFF8000;

2
components/esp32/lib

Submodule components/esp32/lib updated: 1303c92c10...a1e5f8b953

30
components/esp32/syscalls.c
View File

@@ -142,8 +142,12 @@ int _open_r(struct _reent *r, const char * path, int flags, int mode) {
return 0;
}
void _exit(int __status) {
abort();
}
ssize_t _write_r(struct _reent *r, int fd, const void * data, size_t size) {
const char* p = (const char*) data;
const char *data_c = (const char *)data;
if (fd == STDOUT_FILENO) {
static _lock_t stdout_lock; /* lazily initialised */
/* Even though newlib does stream locking on stdout, we need
@@ -160,14 +164,13 @@ ssize_t _write_r(struct _reent *r, int fd, const void * data, size_t size) {
which aren't fully valid.)
*/
_lock_acquire_recursive(&stdout_lock);
while(size--) {
for (size_t i = 0; i < size; i++) {
#if CONFIG_NEWLIB_STDOUT_ADDCR
if (*p=='\n') {
if (data_c[i]=='\n') {
uart_tx_one_char('\r');
}
#endif
uart_tx_one_char(*p);
++p;
uart_tx_one_char(data_c[i]);
}
_lock_release_recursive(&stdout_lock);
}
@@ -367,6 +370,23 @@ void IRAM_ATTR _lock_release_recursive(_lock_t *lock) {
lock_release_generic(lock, queueQUEUE_TYPE_RECURSIVE_MUTEX);
}
// This function is not part on newlib API, it is defined in libc/stdio/local.h
// It is called as part of _reclaim_reent via a pointer in __cleanup member
// of struct _reent.
// This function doesn't call _fclose_r for _stdin, _stdout, _stderr members
// of struct reent. Not doing so causes a memory leak each time a task is
// terminated. We replace __cleanup member with _extra_cleanup_r (below) to work
// around this.
extern void _cleanup_r(struct _reent* r);
void _extra_cleanup_r(struct _reent* r)
{
_cleanup_r(r);
_fclose_r(r, r->_stdout);
_fclose_r(r, r->_stderr);
_fclose_r(r, r->_stdin);
}
static struct _reent s_reent;
/*

115
components/esp32/wifi.c
View File

@@ -1,115 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stddef.h>
#include <stdlib.h>
#include <stdio.h>
#include "esp_err.h"
#include "esp_wifi.h"
#include "esp_event.h"
#include "esp_task.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "freertos/semphr.h"
#if CONFIG_WIFI_ENABLED
static bool wifi_startup_flag = false;
static wifi_startup_cb_t startup_cb;
static void *startup_ctx;
#define WIFI_DEBUG(...)
#define WIFI_API_CALL_CHECK(info, api_call, ret) \
do{\
esp_err_t __err = (api_call);\
if ((ret) != __err) {\
WIFI_DEBUG("%s %d %s ret=%d\n", __FUNCTION__, __LINE__, (info), __err);\
return __err;\
}\
} while(0)
static void esp_wifi_task(void *pvParameters)
{
esp_err_t err;
wifi_init_config_t cfg;
cfg.event_q = (xQueueHandle)esp_event_get_handler();
do {
err = esp_wifi_init(&cfg);
if (err != ESP_OK) {
WIFI_DEBUG("esp_wifi_init fail, ret=%d\n", err);
break;
}
if (startup_cb) {
err = (*startup_cb)(startup_ctx);
if (err != ESP_OK) {
WIFI_DEBUG("startup_cb fail, ret=%d\n", err);
break;
}
}
err = esp_wifi_start();
if (err != ESP_OK) {
WIFI_DEBUG("esp_wifi_start fail, ret=%d\n", err);
break;
}
#if CONFIG_WIFI_AUTO_CONNECT
wifi_mode_t mode;
bool auto_connect;
err = esp_wifi_get_mode(&mode);
if (err != ESP_OK) {
WIFI_DEBUG("esp_wifi_get_mode fail, ret=%d\n", err);
}
err = esp_wifi_get_auto_connect(&auto_connect);
if ((mode == WIFI_MODE_STA || mode == WIFI_MODE_APSTA) && auto_connect) {
err = esp_wifi_connect();
if (err != ESP_OK) {
WIFI_DEBUG("esp_wifi_connect fail, ret=%d\n", err);
break;
}
}
#endif
} while (0);
if (err != ESP_OK) {
WIFI_DEBUG("wifi startup fail, deinit\n");
esp_wifi_deinit();
}
vTaskDelete(NULL);
}
esp_err_t esp_wifi_startup(wifi_startup_cb_t cb, void *ctx)
{
if (wifi_startup_flag) {
return ESP_FAIL;
}
startup_cb = cb;
startup_ctx = ctx;
xTaskCreatePinnedToCore(esp_wifi_task, "wifiTask", ESP_TASK_WIFI_STARTUP_STACK, NULL, ESP_TASK_WIFI_STARTUP_PRIO, NULL, 0);
return ESP_OK;
}
#endif

7
components/esptool_py/Makefile.projbuild
View File

@@ -16,7 +16,7 @@ ESPTOOLPY := $(PYTHON) $(ESPTOOLPY_SRC) --chip esp32
ESPTOOLPY_SERIAL := $(ESPTOOLPY) --port $(ESPPORT) --baud $(ESPBAUD)
# the no-stub argument is temporary until esptool.py fully supports compressed uploads
ESPTOOLPY_WRITE_FLASH=$(ESPTOOLPY_SERIAL) $(if $(CONFIG_ESPTOOLPY_COMPRESSED),--no-stub) write_flash $(if $(CONFIG_ESPTOOLPY_COMPRESSED),-z) --flash_mode $(ESPFLASHMODE) --flash_freq $(ESPFLASHFREQ)
ESPTOOLPY_WRITE_FLASH=$(ESPTOOLPY_SERIAL) write_flash $(if $(CONFIG_ESPTOOLPY_COMPRESSED),-z) --flash_mode $(ESPFLASHMODE) --flash_freq $(ESPFLASHFREQ)
ESPTOOL_ALL_FLASH_ARGS += $(CONFIG_APP_OFFSET) $(APP_BIN)
@@ -24,10 +24,11 @@ $(APP_BIN): $(APP_ELF) $(ESPTOOLPY_SRC)
$(Q) $(ESPTOOLPY) elf2image --flash_mode $(ESPFLASHMODE) --flash_freq $(ESPFLASHFREQ) -o $@ $<
flash: all_binaries $(ESPTOOLPY_SRC)
@echo "Flashing project app to $(CONFIG_APP_OFFSET)..."
@echo "Flashing binaries to serial port $(ESPPORT) (app at offset $(CONFIG_APP_OFFSET))..."
$(Q) $(ESPTOOLPY_WRITE_FLASH) $(ESPTOOL_ALL_FLASH_ARGS)
app-flash: $(APP_BIN) $(ESPTOOLPY_SRC)
@echo "Flashing app to serial port $(ESPPORT), offset $(CONFIG_APP_OFFSET)..."
$(Q) $(ESPTOOLPY_WRITE_FLASH) $(CONFIG_APP_OFFSET) $(APP_BIN)
$(eval $(call SubmoduleRequiredForFiles,$(ESPTOOLPY_SRC)))
$(eval $(call SubmoduleCheck,$(ESPTOOLPY_SRC),$(COMPONENT_PATH)/esptool))

2
components/esptool_py/esptool

Submodule components/esptool_py/esptool updated: 7c84dd4335...197ba605fe

2
components/expat/component.mk
View File

@@ -10,6 +10,6 @@ COMPONENT_ADD_INCLUDEDIRS := port/include include/expat
COMPONENT_SRCDIRS := library port
CFLAGS += -Wno-error=address -Waddress -DHAVE_EXPAT_CONFIG_H
CFLAGS += -Wno-unused-function -DHAVE_EXPAT_CONFIG_H
include $(IDF_PATH)/make/component_common.mk

22
components/expat/expat.rst Normal file
View File

@@ -0,0 +1,22 @@
The Expat XML Parse Instruction
=============================
Expat is an XML parser library written in C which be used for parse XML documents.
It is a stream-oriented parser in which an application registers handlers for things the parser might find in the XML document.
It can parse some larger files.
- Expat XML Parser support many different processor, but for the most part function you only need the following functions:
**XML_ParserCreate**: Create a new parser object
**XML_SetElementHandler**: Set handlers for start and end tags
**XML_SetCharacterDataHandler**: Set handler for text
**XML_Parse**: Pass a buffer full of document to the parser
More information about Expat library can be found on http://expat.sourceforge.net
An introductory article on using Expat is available on http://xml.com

256
components/freertos/Kconfig
View File

@@ -2,192 +2,200 @@ menu "FreeRTOS"
# This is actually also handled in the ESP32 startup code, not only in FreeRTOS.
config FREERTOS_UNICORE
bool "Run FreeRTOS only on first core"
default n
help
This version of FreeRTOS normally takes control of all cores of
the CPU. Select this if you only want to start it on the first core.
This is needed when e.g. another process needs complete control
over the second core.
bool "Run FreeRTOS only on first core"
default n
help
This version of FreeRTOS normally takes control of all cores of
the CPU. Select this if you only want to start it on the first core.
This is needed when e.g. another process needs complete control
over the second core.
choice FREERTOS_CORETIMER
prompt "Xtensa timer to use as the FreeRTOS tick source"
default CONFIG_FREERTOS_CORETIMER_0
help
FreeRTOS needs a timer with an associated interrupt to use as
the main tick source to increase counters, run timers and do
pre-emptive multitasking with. There are multiple timers available
to do this, with different interrupt priorities. Check
prompt "Xtensa timer to use as the FreeRTOS tick source"
default CONFIG_FREERTOS_CORETIMER_0
help
FreeRTOS needs a timer with an associated interrupt to use as
the main tick source to increase counters, run timers and do
pre-emptive multitasking with. There are multiple timers available
to do this, with different interrupt priorities. Check
config FREERTOS_CORETIMER_0
bool "Timer 0 (int 6, level 1)"
help
Select this to use timer 0
bool "Timer 0 (int 6, level 1)"
help
Select this to use timer 0
config FREERTOS_CORETIMER_1
bool "Timer 1 (int 15, level 3)"
help
Select this to use timer 1
bool "Timer 1 (int 15, level 3)"
help
Select this to use timer 1
config FREERTOS_CORETIMER_2
bool "Timer 2 (int 16, level 5)"
help
Select this to use timer 2
bool "Timer 2 (int 16, level 5)"
help
Select this to use timer 2
endchoice
config FREERTOS_HZ
int "Tick rate (Hz)"
range 1 10000
default 100
int "Tick rate (Hz)"
range 1 1000
default 100
help
Select the tick rate at which FreeRTOS does pre-emptive context switching.
config FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
bool "Halt when an SMP-untested function is called"
default y
help
Select the tick rate at which FreeRTOS does pre-emptive context switching.
Some functions in FreeRTOS have not been thoroughly tested yet when moving to
the SMP implementation of FreeRTOS. When this option is enabled, these fuctions
will throw an assert().
choice FREERTOS_CHECK_STACKOVERFLOW
prompt "Check for stack overflow"
default FREERTOS_CHECK_STACKOVERFLOW_QUICK
help
FreeRTOS can check for stack overflows in threads and trigger an user function
called vApplicationStackOverflowHook when this happens.
prompt "Check for stack overflow"
default FREERTOS_CHECK_STACKOVERFLOW_QUICK
help
FreeRTOS can check for stack overflows in threads and trigger an user function
called vApplicationStackOverflowHook when this happens.
config FREERTOS_CHECK_STACKOVERFLOW_NONE
bool "No checking"
help
Do not check for stack overflows (configCHECK_FOR_STACK_OVERFLOW=0)
bool "No checking"
help
Do not check for stack overflows (configCHECK_FOR_STACK_OVERFLOW=0)
config FREERTOS_CHECK_STACKOVERFLOW_PTRVAL
bool "Check by stack pointer value"
help
Check for stack overflows on each context switch by checking if
the stack pointer is in a valid range. Quick but does not detect
stack overflows that happened between context switches
(configCHECK_FOR_STACK_OVERFLOW=1)
bool "Check by stack pointer value"
help
Check for stack overflows on each context switch by checking if
the stack pointer is in a valid range. Quick but does not detect
stack overflows that happened between context switches
(configCHECK_FOR_STACK_OVERFLOW=1)
config FREERTOS_CHECK_STACKOVERFLOW_CANARY
bool "Check using canary bytes"
help
Places some magic bytes at the end of the stack area and on each
context switch, check if these bytes are still intact. More thorough
than just checking the pointer, but also slightly slower.
(configCHECK_FOR_STACK_OVERFLOW=2)
bool "Check using canary bytes"
help
Places some magic bytes at the end of the stack area and on each
context switch, check if these bytes are still intact. More thorough
than just checking the pointer, but also slightly slower.
(configCHECK_FOR_STACK_OVERFLOW=2)
endchoice
config FREERTOS_THREAD_LOCAL_STORAGE_POINTERS
int "Amount of thread local storage pointers"
range 0 256 if !WIFI_ENABLED
range 1 256 if WIFI_ENABLED
default 1
help
FreeRTOS has the ability to store per-thread pointers in the task
control block. This controls the amount of pointers available;
0 turns off this functionality.
int "Amount of thread local storage pointers"
range 0 256 if !WIFI_ENABLED
range 1 256 if WIFI_ENABLED
default 1
help
FreeRTOS has the ability to store per-thread pointers in the task
control block. This controls the amount of pointers available;
0 turns off this functionality.
If using the WiFi stack, this value must be at least 1.
If using the WiFi stack, this value must be at least 1.
#This still needs to be implemented.
choice FREERTOS_PANIC
prompt "Panic handler behaviour"
default FREERTOS_PANIC_PRINT_REBOOT
help
If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
invoked. Configure the panic handlers action here.
prompt "Panic handler behaviour"
default FREERTOS_PANIC_PRINT_REBOOT
help
If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
invoked. Configure the panic handlers action here.
config FREERTOS_PANIC_PRINT_HALT
bool "Print registers and halt"
help
Outputs the relevant registers over the serial port and halt the
processor. Needs a manual reset to restart.
bool "Print registers and halt"
help
Outputs the relevant registers over the serial port and halt the
processor. Needs a manual reset to restart.
config FREERTOS_PANIC_PRINT_REBOOT
bool "Print registers and reboot"
help
Outputs the relevant registers over the serial port and immediately
reset the processor.
bool "Print registers and reboot"
help
Outputs the relevant registers over the serial port and immediately
reset the processor.
config FREERTOS_PANIC_SILENT_REBOOT
bool "Silent reboot"
help
Just resets the processor without outputting anything
bool "Silent reboot"
help
Just resets the processor without outputting anything
config FREERTOS_PANIC_GDBSTUB
bool "Invoke GDBStub"
help
Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
of the crash.
bool "Invoke GDBStub"
help
Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
of the crash.
endchoice
config FREERTOS_DEBUG_OCDAWARE
bool "Make exception and panic handlers JTAG/OCD aware"
default y
help
The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
instead of panicking, have the debugger stop on the offending instruction.
bool "Make exception and panic handlers JTAG/OCD aware"
default y
help
The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
instead of panicking, have the debugger stop on the offending instruction.
choice FREERTOS_ASSERT
prompt "FreeRTOS assertions"
default FREERTOS_ASSERT_FAIL_ABORT
help
Failed FreeRTOS configASSERT() assertions can be configured to
behave in different ways.
prompt "FreeRTOS assertions"
default FREERTOS_ASSERT_FAIL_ABORT
help
Failed FreeRTOS configASSERT() assertions can be configured to
behave in different ways.
config FREERTOS_ASSERT_FAIL_ABORT
bool "abort() on failed assertions"
help
If a FreeRTOS configASSERT() fails, FreeRTOS will abort() and
halt execution. The panic handler can be configured to handle
the outcome of an abort() in different ways.
bool "abort() on failed assertions"
help
If a FreeRTOS configASSERT() fails, FreeRTOS will abort() and
halt execution. The panic handler can be configured to handle
the outcome of an abort() in different ways.
config FREERTOS_ASSERT_FAIL_PRINT_CONTINUE
bool "Print and continue failed assertions"
help
If a FreeRTOS assertion fails, print it out and continue.
bool "Print and continue failed assertions"
help
If a FreeRTOS assertion fails, print it out and continue.
config FREERTOS_ASSERT_DISABLE
bool "Disable FreeRTOS assertions"
help
FreeRTOS configASSERT() will not be compiled into the binary.
bool "Disable FreeRTOS assertions"
help
FreeRTOS configASSERT() will not be compiled into the binary.
endchoice
config FREERTOS_BREAK_ON_SCHEDULER_START_JTAG
bool "Stop program on scheduler start when JTAG/OCD is detected"
depends on FREERTOS_DEBUG_OCDAWARE
default y
help
If JTAG/OCD is connected, stop execution when the scheduler is started and the first
task is executed.
bool "Stop program on scheduler start when JTAG/OCD is detected"
depends on FREERTOS_DEBUG_OCDAWARE
default y
help
If JTAG/OCD is connected, stop execution when the scheduler is started and the first
task is executed.
menuconfig ENABLE_MEMORY_DEBUG
bool "Enable heap memory debug"
default n
help
Enable this option to show malloc heap block and memory crash detect
bool "Enable heap memory debug"
default n
help
Enable this option to show malloc heap block and memory crash detect
menuconfig FREERTOS_DEBUG_INTERNALS
bool "Debug FreeRTOS internals"
default n
help
Enable this option to show the menu with internal FreeRTOS debugging features.
This option does not change any code by itself, it just shows/hides some options.
bool "Debug FreeRTOS internals"
default n
help
Enable this option to show the menu with internal FreeRTOS debugging features.
This option does not change any code by itself, it just shows/hides some options.
if FREERTOS_DEBUG_INTERNALS
config FREERTOS_PORTMUX_DEBUG
bool "Debug portMUX portENTER_CRITICAL/portEXIT_CRITICAL"
depends on FREERTOS_DEBUG_INTERNALS
default n
help
If enabled, debug information (including integrity checks) will be printed
to UART for the port-specific MUX implementation.
bool "Debug portMUX portENTER_CRITICAL/portEXIT_CRITICAL"
depends on FREERTOS_DEBUG_INTERNALS
default n
help
If enabled, debug information (including integrity checks) will be printed
to UART for the port-specific MUX implementation.
config FREERTOS_PORTMUX_DEBUG_RECURSIVE
bool "Debug portMUX Recursion"
depends on FREERTOS_PORTMUX_DEBUG
default n
help
If enabled, additional debug information will be printed for recursive
portMUX usage.
bool "Debug portMUX Recursion"
depends on FREERTOS_PORTMUX_DEBUG
default n
help
If enabled, additional debug information will be printed for recursive
portMUX usage.
endif # FREERTOS_DEBUG_INTERNALS

1
components/freertos/croutine.c
View File

@@ -143,6 +143,7 @@ BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPri
BaseType_t xReturn;
CRCB_t *pxCoRoutine;
UNTESTED_FUNCTION(); //Actually, coroutines are entirely unsupported
/* Allocate the memory that will store the co-routine control block. */
pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
if( pxCoRoutine )

7
components/freertos/event_groups.c
View File

@@ -124,7 +124,6 @@ typedef struct xEventGroupDefinition
/* Again: one mux for all events. Maybe this can be made more granular. ToDo: look into that. -JD */
static portMUX_TYPE xEventGroupMux = portMUX_INITIALIZER_UNLOCKED;
static BaseType_t xMuxInitialized = pdFALSE;
/*-----------------------------------------------------------*/
@@ -145,12 +144,6 @@ EventGroupHandle_t xEventGroupCreate( void )
{
EventGroup_t *pxEventBits;
//Initialize mux, if needed
if ( xMuxInitialized == pdFALSE ) {
vPortCPUInitializeMutex( & xEventGroupMux );
xMuxInitialized = pdTRUE;
}
pxEventBits = pvPortMalloc( sizeof( EventGroup_t ) );
if( pxEventBits != NULL )
{

18
components/freertos/include/freertos/FreeRTOSConfig.h
View File

@@ -100,7 +100,7 @@
#define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1
/* TODO: config freq by menuconfig */
#define XT_CLOCK_FREQ 80000000
#define XT_CLOCK_FREQ (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000)
/* Required for configuration-dependent settings */
#include "xtensa_config.h"
@@ -124,6 +124,16 @@
abort(); \
}
#endif
#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
#include <stdlib.h>
#include "rom/ets_sys.h"
#define UNTESTED_FUNCTION() { ets_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
#else
#define UNTESTED_FUNCTION()
#endif
#endif /* def __ASSEMBLER__ */
@@ -222,7 +232,9 @@
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#ifndef configENABLE_MEMORY_DEBUG
#if CONFIG_ENABLE_MEMORY_DEBUG
#define configENABLE_MEMORY_DEBUG 1
#else
#define configENABLE_MEMORY_DEBUG 0
#endif
@@ -261,5 +273,7 @@
#define configXT_SIMULATOR 0
#endif /* FREERTOS_CONFIG_H */

206
components/freertos/include/freertos/ringbuf.h Normal file
View File

@@ -0,0 +1,206 @@
#ifndef FREERTOS_RINGBUF_H
#define FREERTOS_RINGBUF_H
/*
Header definitions for a FreeRTOS ringbuffer object
A ringbuffer instantiated by these functions essentially acts like a FreeRTOS queue, with the
difference that it's strictly FIFO and with the main advantage that you can put in randomly-sized
items. The capacity, accordingly, isn't measured in the amount of items, but the amount of memory
that is used for storing the items. Dependent on the size of the items, more or less of them will
fit in the ring buffer.
This ringbuffer tries to be efficient with memory: when inserting an item, the item data will
be copied to the ringbuffer memory. When retrieving an item, however, a reference to ringbuffer
memory will be returned. The returned memory is guaranteed to be 32-bit aligned and contiguous.
The application can use this memory, but as long as it does, ringbuffer writes that would write
to this bit of memory will block.
The requirement for items to be contiguous is slightly problematic when the only way to place
the next item would involve a wraparound from the end to the beginning of the ringbuffer. This can
be solved in two ways:
- allow_split_items = pdTRUE: The insertion code will split the item in two items; one which fits
in the space left at the end of the ringbuffer, one that contains the remaining data which is placed
in the beginning. Two xRingbufferReceive calls will be needed to retrieve the data.
- allow_split_items = pdFALSE: The insertion code will leave the room at the end of the ringbuffer
unused and instead will put the entire item at the start of the ringbuffer, as soon as there is
enough free space.
The maximum size of an item will be affected by this decision. When split items are allowed, it's
acceptable to push items of (buffer_size)-16 bytes into the buffer. When it's not allowed, the
maximum size is (buffer_size/2)-8 bytes.
*/
//An opaque handle for a ringbuff object.
typedef void * RingbufHandle_t;
/**
* @brief Create a ring buffer
*
* @param buf_length : Length of circular buffer, in bytes. Each entry will take up its own length, plus a header
* that at the moment is equal to sizeof(size_t).
* @param allow_split_items : pdTRUE if it is acceptable that item data is inserted as two
* items instead of one.
*
* @return A RingbufHandle_t handle to the created ringbuffer, or NULL in case of error.
*/
RingbufHandle_t xRingbufferCreate(size_t buf_length, BaseType_t allow_split_items);
/**
* @brief Delete a ring buffer
*
* @param ringbuf - Ring buffer to delete
*
* @return void
*/
void vRingbufferDelete(RingbufHandle_t ringbuf);
/**
* @brief Get maximum size of an item that can be placed in the ring buffer
*
* @param ringbuf - Ring buffer to query
*
* @return Maximum size, in bytes, of an item that can be placed in a ring buffer.
*/
size_t xRingbufferGetMaxItemSize(RingbufHandle_t ringbuf);
/**
* @brief Insert an item into the ring buffer
*
* @param ringbuf - Ring buffer to insert the item into
* @param data - Pointer to data to insert. NULL is allowed if data_size is 0.
* @param data_size - Size of data to insert. A value of 0 is allowed.
* @param xTicksToWait - Ticks to wait for room in the ringbuffer.
*
* @return pdTRUE if succeeded, pdFALSE on time-out or when the buffer is larger
* than indicated by xRingbufferGetMaxItemSize(ringbuf).
*/
BaseType_t xRingbufferSend(RingbufHandle_t ringbuf, void *data, size_t data_size, TickType_t ticks_to_wait);
/**
* @brief Insert an item into the ring buffer from an ISR
*
* @param ringbuf - Ring buffer to insert the item into
* @param data - Pointer to data to insert. NULL is allowed if data_size is 0.
* @param data_size - Size of data to insert. A value of 0 is allowed.
* @param higher_prio_task_awoken - Value pointed to will be set to pdTRUE if the push woke up a higher
* priority task.
*
* @return pdTRUE if succeeded, pdFALSE when the ring buffer does not have space.
*/
BaseType_t xRingbufferSendFromISR(RingbufHandle_t ringbuf, void *data, size_t data_size, BaseType_t *higher_prio_task_awoken);
/**
* @brief Retrieve an item from the ring buffer
*
* @param ringbuf - Ring buffer to retrieve the item from
* @param item_size - Pointer to a variable to which the size of the retrieved item will be written.
* @param xTicksToWait - Ticks to wait for items in the ringbuffer.
*
* @return Pointer to the retrieved item on success; *item_size filled with the length of the
* item. NULL on timeout, *item_size is untouched in that case.
*/
void *xRingbufferReceive(RingbufHandle_t ringbuf, size_t *item_size, TickType_t ticks_to_wait);
/**
* @brief Retrieve an item from the ring buffer from an ISR
*
* @param ringbuf - Ring buffer to retrieve the item from
* @param item_size - Pointer to a variable to which the size of the retrieved item will be written.
*
* @return Pointer to the retrieved item on success; *item_size filled with the length of the
* item. NULL when the ringbuffer is empty, *item_size is untouched in that case.
*/
void *xRingbufferReceiveFromISR(RingbufHandle_t ringbuf, size_t *item_size);
/**
* @brief Return a previously-retrieved item to the ringbuffer
*
* @param ringbuf - Ring buffer the item was retrieved from
* @param item - Item that was received earlier
*
* @return void
*/
void vRingbufferReturnItem(RingbufHandle_t ringbuf, void *item);
/**
* @brief Return a previously-retrieved item to the ringbuffer from an ISR
*
* @param ringbuf - Ring buffer the item was retrieved from
* @param item - Item that was received earlier
* @param higher_prio_task_awoken - Value pointed to will be set to pdTRUE if the push woke up a higher
* priority task.
*
* @return void
*/
void vRingbufferReturnItemFromISR(RingbufHandle_t ringbuf, void *item, BaseType_t *higher_prio_task_awoken);
/**
* @brief Add the ringbuffer to a queue set. This specifically adds the semaphore that indicates
* more space has become available in the ringbuffer.
*
* @param ringbuf - Ring buffer to add to the queue set
* @param xQueueSet - Queue set to add the ringbuffer to
*
* @return pdTRUE on success, pdFALSE otherwise
*/
BaseType_t xRingbufferAddToQueueSetRead(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet);
/**
* @brief Add the ringbuffer to a queue set. This specifically adds the semaphore that indicates
* something has been written into the ringbuffer.
*
* @param ringbuf - Ring buffer to add to the queue set
* @param xQueueSet - Queue set to add the ringbuffer to
*
* @return pdTRUE on success, pdFALSE otherwise
*/
BaseType_t xRingbufferAddToQueueSetWrite(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet);
/**
* @brief Remove the ringbuffer from a queue set. This specifically removes the semaphore that indicates
* more space has become available in the ringbuffer.
*
* @param ringbuf - Ring buffer to remove from the queue set
* @param xQueueSet - Queue set to remove the ringbuffer from
*
* @return pdTRUE on success, pdFALSE otherwise
*/
BaseType_t xRingbufferRemoveFromQueueSetRead(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet);
/**
* @brief Remove the ringbuffer from a queue set. This specifically removes the semaphore that indicates
* something has been written to the ringbuffer.
*
* @param ringbuf - Ring buffer to remove from the queue set
* @param xQueueSet - Queue set to remove the ringbuffer from
*
* @return pdTRUE on success, pdFALSE otherwise
*/
BaseType_t xRingbufferRemoveFromQueueSetWrite(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet);
/**
* @brief Debugging function to print the internal pointers in the ring buffer
*
* @param ringbuf - Ring buffer to show
*
* @return void
*/
void xRingbufferPrintInfo(RingbufHandle_t ringbuf);
#endif

6
components/freertos/include/freertos/task.h
View File

@@ -1979,6 +1979,12 @@ BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcN
*/
UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
/*
* Get the current core affinity of a task
*/
BaseType_t xTaskGetAffinity( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
/*
* Set the uxTaskNumber of the task referenced by the xTask parameter to
* uxHandle.

6
components/freertos/panic.c
View File

@@ -79,9 +79,9 @@ inline static void panicPutDec(int a) { }
int xPortGetCoreID();
void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName ) {
panicPutStr("***ERROR*** A stack overflow in task");
panicPutStr("***ERROR*** A stack overflow in task ");
panicPutStr((char*)pcTaskName);
panicPutStr("has been detected.\n");
panicPutStr(" has been detected.\r\n");
}
static const char *edesc[]={
@@ -160,7 +160,7 @@ void xt_unhandled_exception(XtExcFrame *frame) {
panicPutStr("Guru Meditation Error of type ");
x=regs[20];
if (x<40) panicPutStr(edesc[x]); else panicPutStr("Unknown");
panicPutStr(" occured on core ");
panicPutStr(" occurred on core ");
panicPutDec(xPortGetCoreID());
if (inOCDMode()) {
panicPutStr(" at pc=");

394
components/freertos/queue.c
View File

@@ -100,11 +100,6 @@ header files above, but not in this file, in order to generate the correct
privileged Vs unprivileged linkage and placement. */
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
/* Constants used with the xRxLock and xTxLock structure members. */
#define queueUNLOCKED ( ( BaseType_t ) -1 )
#define queueLOCKED_UNMODIFIED ( ( BaseType_t ) 0 )
/* When the Queue_t structure is used to represent a base queue its pcHead and
pcTail members are used as pointers into the queue storage area. When the
Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
@@ -163,9 +158,6 @@ typedef struct QueueDefinition
UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */
volatile BaseType_t xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
volatile BaseType_t xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
#if ( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxQueueNumber;
uint8_t ucQueueType;
@@ -212,15 +204,6 @@ typedef xQUEUE Queue_t;
#endif /* configQUEUE_REGISTRY_SIZE */
/*
* Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not
* prevent an ISR from adding or removing items to the queue, but does prevent
* an ISR from removing tasks from the queue event lists. If an ISR finds a
* queue is locked it will instead increment the appropriate queue lock count
* to indicate that a task may require unblocking. When the queue in unlocked
* these lock counts are inspected, and the appropriate action taken.
*/
static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
/*
* Uses a critical section to determine if there is any data in a queue.
@@ -255,27 +238,6 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer
static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
#endif
/*-----------------------------------------------------------*/
/*
* Macro to mark a queue as locked. Locking a queue prevents an ISR from
* accessing the queue event lists.
*/
#define prvLockQueue( pxQueue ) \
taskENTER_CRITICAL(&pxQueue->mux); \
{ \
if( ( pxQueue )->xRxLock == queueUNLOCKED ) \
{ \
( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED; \
} \
if( ( pxQueue )->xTxLock == queueUNLOCKED ) \
{ \
( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED; \
} \
} \
taskEXIT_CRITICAL(&pxQueue->mux)
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
Queue_t * const pxQueue = ( Queue_t * ) xQueue;
@@ -292,8 +254,6 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
pxQueue->pcWriteTo = pxQueue->pcHead;
pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
pxQueue->xRxLock = queueUNLOCKED;
pxQueue->xTxLock = queueUNLOCKED;
if( xNewQueue == pdFALSE )
{
@@ -441,8 +401,6 @@ int8_t *pcAllocatedBuffer;
pxNewQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
pxNewQueue->uxLength = ( UBaseType_t ) 1U;
pxNewQueue->uxItemSize = ( UBaseType_t ) 0U;
pxNewQueue->xRxLock = queueUNLOCKED;
pxNewQueue->xTxLock = queueUNLOCKED;
#if ( configUSE_TRACE_FACILITY == 1 )
{
@@ -787,7 +745,6 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
now the critical section has been exited. */
taskENTER_CRITICAL(&pxQueue->mux);
// prvLockQueue( pxQueue );
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
@@ -797,13 +754,6 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
// prvUnlockQueue( pxQueue );
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
@@ -816,14 +766,12 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
else
{
/* Try again. */
// prvUnlockQueue( pxQueue );
taskEXIT_CRITICAL(&pxQueue->mux);
}
}
else
{
/* The timeout has expired. */
// prvUnlockQueue( pxQueue );
taskEXIT_CRITICAL(&pxQueue->mux);
/* Return to the original privilege level before exiting the
@@ -940,7 +888,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
configASSERT( pxQueue );
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
ets_printf("Not Supported: %s\n", __FUNCTION__);
UNTESTED_FUNCTION();
for( ;; )
{
taskENTER_CRITICAL();
@@ -1129,27 +1077,18 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
disinheritance here or to clear the mutex holder TCB member. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( pxQueue->xTxLock == queueUNLOCKED )
#if ( configUSE_QUEUE_SETS == 1 )
{
#if ( configUSE_QUEUE_SETS == 1 )
if( pxQueue->pxQueueSetContainer != NULL )
{
if( pxQueue->pxQueueSetContainer != NULL )
if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )
{
if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )
/* The queue is a member of a queue set, and posting
to the queue set caused a higher priority task to
unblock. A context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
/* The queue is a member of a queue set, and posting
to the queue set caused a higher priority task to
unblock. A context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
@@ -1158,40 +1097,17 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
}
else
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so
record that a context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
mtCOVERAGE_TEST_MARKER();
}
mtCOVERAGE_TEST_MARKER();
}
}
#else /* configUSE_QUEUE_SETS */
else
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so record that a
context switch is required. */
/* The task waiting has a higher priority so
record that a context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
@@ -1211,15 +1127,35 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
}
else
#else /* configUSE_QUEUE_SETS */
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
++( pxQueue->xTxLock );
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
xReturn = pdPASS;
}
else
@@ -1285,27 +1221,18 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
++( pxQueue->uxMessagesWaiting );
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( pxQueue->xTxLock == queueUNLOCKED )
#if ( configUSE_QUEUE_SETS == 1 )
{
#if ( configUSE_QUEUE_SETS == 1 )
if( pxQueue->pxQueueSetContainer != NULL )
{
if( pxQueue->pxQueueSetContainer != NULL )
if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )
{
if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )
/* The semaphore is a member of a queue set, and
posting to the queue set caused a higher priority
task to unblock. A context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
/* The semaphore is a member of a queue set, and
posting to the queue set caused a higher priority
task to unblock. A context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
@@ -1314,40 +1241,17 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
}
else
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so
record that a context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
mtCOVERAGE_TEST_MARKER();
}
mtCOVERAGE_TEST_MARKER();
}
}
#else /* configUSE_QUEUE_SETS */
else
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so record that a
context switch is required. */
/* The task waiting has a higher priority so
record that a context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
@@ -1367,14 +1271,35 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
}
else
#else /* configUSE_QUEUE_SETS */
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
++( pxQueue->xTxLock );
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
xReturn = pdPASS;
}
@@ -1525,7 +1450,6 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
now the critical section has been exited. */
taskENTER_CRITICAL(&pxQueue->mux);
// prvLockQueue( pxQueue );
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
@@ -1548,20 +1472,17 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
#endif
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
// prvUnlockQueue( pxQueue );
taskEXIT_CRITICAL(&pxQueue->mux);
portYIELD_WITHIN_API();
}
else
{
/* Try again. */
// prvUnlockQueue( pxQueue );
taskEXIT_CRITICAL(&pxQueue->mux);
}
}
else
{
// prvUnlockQueue( pxQueue );
taskEXIT_CRITICAL(&pxQueue->mux);
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
@@ -1606,26 +1527,15 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
prvCopyDataFromQueue( pxQueue, pvBuffer );
--( pxQueue->uxMessagesWaiting );
/* If the queue is locked the event list will not be modified.
Instead update the lock count so the task that unlocks the queue
will know that an ISR has removed data while the queue was
locked. */
if( pxQueue->xRxLock == queueUNLOCKED )
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
/* The task waiting has a higher priority than us so
force a context switch. */
if( pxHigherPriorityTaskWoken != NULL )
{
/* The task waiting has a higher priority than us so
force a context switch. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
*pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
@@ -1639,9 +1549,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was removed while it was locked. */
++( pxQueue->xRxLock );
mtCOVERAGE_TEST_MARKER();
}
xReturn = pdPASS;
@@ -1902,129 +1810,7 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
}
}
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL(&pxQueue->mux);
{
/* See if data was added to the queue while it was locked. */
while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )
{
/* Data was posted while the queue was locked. Are any tasks
blocked waiting for data to become available? */
#if ( configUSE_QUEUE_SETS == 1 )
{
if( pxQueue->pxQueueSetContainer != NULL )
{
if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )
{
/* The queue is a member of a queue set, and posting to
the queue set caused a higher priority task to unblock.
A context switch is required. */
taskEXIT_CRITICAL(&pxQueue->mux); //ToDo: Is aquire/release needed around any of the bTaskMissedYield calls?
vTaskMissedYield();
taskENTER_CRITICAL(&pxQueue->mux);
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so record that a
context switch is required. */
taskEXIT_CRITICAL(&pxQueue->mux);
vTaskMissedYield();
taskENTER_CRITICAL(&pxQueue->mux);
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
break;
}
}
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so record that a
context switch is required. */
taskEXIT_CRITICAL(&pxQueue->mux);
vTaskMissedYield();
taskENTER_CRITICAL(&pxQueue->mux);
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else
{
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--( pxQueue->xTxLock );
}
pxQueue->xTxLock = queueUNLOCKED;
}
taskEXIT_CRITICAL(&pxQueue->mux);
/* Do the same for the Rx lock. */
taskENTER_CRITICAL(&pxQueue->mux);
{
while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
{
taskEXIT_CRITICAL(&pxQueue->mux);
vTaskMissedYield();
taskENTER_CRITICAL(&pxQueue->mux);
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--( pxQueue->xRxLock );
}
else
{
break;
}
}
pxQueue->xRxLock = queueUNLOCKED;
}
taskEXIT_CRITICAL(&pxQueue->mux);
}
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( Queue_t *pxQueue )
@@ -2117,6 +1903,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
BaseType_t xReturn;
Queue_t * const pxQueue = ( Queue_t * ) xQueue;
UNTESTED_FUNCTION();
/* If the queue is already full we may have to block. A critical section
is required to prevent an interrupt removing something from the queue
between the check to see if the queue is full and blocking on the queue. */
@@ -2390,7 +2177,8 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
{
UBaseType_t ux;
UNTESTED_FUNCTION();
/* See if there is an empty space in the registry. A NULL name denotes
a free slot. */
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
@@ -2458,10 +2246,8 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
/* Only do anything if there are no messages in the queue. This function
will not actually cause the task to block, just place it on a blocked
list. It will not block until the scheduler is unlocked - at which
time a yield will be performed. If an item is added to the queue while
the queue is locked, and the calling task blocks on the queue, then the
calling task will be immediately unblocked when the queue is unlocked. */
// prvLockQueue( pxQueue );
time a yield will be performed. */
taskENTER_CRITICAL(&pxQueue->mux);
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
{
/* There is nothing in the queue, block for the specified period. */
@@ -2471,7 +2257,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
{
mtCOVERAGE_TEST_MARKER();
}
// prvUnlockQueue( pxQueue );
taskEXIT_CRITICAL(&pxQueue->mux);
}
#endif /* configUSE_TIMERS */

474
components/freertos/ringbuf.c Normal file
View File

@@ -0,0 +1,474 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/xtensa_api.h"
#include "freertos/ringbuf.h"
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
typedef enum {
flag_allowsplit = 1,
} rbflag_t;
typedef enum {
iflag_free = 1, //Buffer is not read and given back by application, free to overwrite
iflag_dummydata = 2, //Data from here to end of ringbuffer is dummy. Restart reading at start of ringbuffer.
} itemflag_t;
//The ringbuffer structure
typedef struct {
SemaphoreHandle_t free_space_sem; //Binary semaphore, wakes up writing threads when there's more free space
SemaphoreHandle_t items_buffered_sem; //Binary semaphore, indicates there are new packets in the circular buffer. See remark.
size_t size; //Size of the data storage
uint8_t *write_ptr; //Pointer where the next item is written
uint8_t *read_ptr; //Pointer from where the next item is read
uint8_t *free_ptr; //Pointer to the last block that hasn't been given back to the ringbuffer yet
uint8_t *data; //Data storage
portMUX_TYPE mux; //Spinlock for actual data/ptr/struct modification
rbflag_t flags;
} ringbuf_t;
/*
Remark: A counting semaphore for items_buffered_sem would be more logical, but counting semaphores in
FreeRTOS need a maximum count, and allocate more memory the larger the maximum count is. Here, we
would need to set the maximum to the maximum amount of times a null-byte unit firs in the buffer,
which is quite high and so would waste a fair amount of memory.
*/
//The header prepended to each ringbuffer entry. Size is assumed to be a multiple of 32bits.
typedef struct {
size_t len;
itemflag_t flags;
} buf_entry_hdr_t;
//Calculate space free in the buffer
static int ringbufferFreeMem(ringbuf_t *rb)
{
int free_size = rb->free_ptr-rb->write_ptr;
if (free_size <= 0) free_size += rb->size;
//Reserve one byte. If we do not do this and the entire buffer is filled, we get a situation
//where read_ptr == free_ptr, messing up the next calculation.
return free_size-1;
}
//Copies a single item to the ring buffer. Assumes there is space in the ringbuffer and
//the ringbuffer is locked. Increases write_ptr to the next item. Returns pdTRUE on
//success, pdFALSE if it can't make the item fit and the calling routine needs to retry
//later or fail.
//This function by itself is not threadsafe, always call from within a muxed section.
static BaseType_t copyItemToRingbuf(ringbuf_t *rb, uint8_t *buffer, size_t buffer_size)
{
size_t rbuffer_size=(buffer_size+3)&~3; //Payload length, rounded to next 32-bit value
configASSERT(((int)rb->write_ptr&3)==0); //write_ptr needs to be 32-bit aligned
configASSERT(rb->write_ptr-(rb->data+rb->size) >= sizeof(buf_entry_hdr_t)); //need to have at least the size
//of a header to the end of the ringbuff
size_t rem_len=(rb->data + rb->size) - rb->write_ptr; //length remaining until end of ringbuffer
//See if we have enough contiguous space to write the buffer.
if (rem_len < rbuffer_size + sizeof(buf_entry_hdr_t)) {
//The buffer can't be contiguously written to the ringbuffer, but needs special handling. Do
//that depending on how the ringbuffer is configured.
//The code here is also expected to check if the buffer, mangled in whatever way is implemented,
//will still fit, and return pdFALSE if that is not the case.
if (rb->flags & flag_allowsplit) {
//Buffer plus header is not going to fit in the room from wr_pos to the end of the
//ringbuffer... we need to split the write in two.
//First, see if this will fit at all.
if (ringbufferFreeMem(rb) < (sizeof(buf_entry_hdr_t)*2)+rbuffer_size) {
//Will not fit.
return pdFALSE;
}
//Because the code at the end of the function makes sure we always have
//room for a header, this should never assert.
configASSERT(rem_len>=sizeof(buf_entry_hdr_t));
//Okay, it should fit. Write everything.
//First, place bit of buffer that does fit. Write header first...
buf_entry_hdr_t *hdr=(buf_entry_hdr_t *)rb->write_ptr;
hdr->flags=0;
hdr->len=rem_len-sizeof(buf_entry_hdr_t);
rb->write_ptr+=sizeof(buf_entry_hdr_t);
rem_len-=sizeof(buf_entry_hdr_t);
if (rem_len!=0) {
//..then write the data bit that fits.
memcpy(rb->write_ptr, buffer, rem_len);
//Update vars so the code later on will write the rest of the data.
buffer+=rem_len;
rbuffer_size-=rem_len;
buffer_size-=rem_len;
} else {
//Huh, only the header fit. Mark as dummy so the receive function doesn't receive
//an useless zero-byte packet.
hdr->flags|=iflag_dummydata;
}
rb->write_ptr=rb->data;
} else {
//Buffer plus header is not going to fit in the room from wr_pos to the end of the
//ringbuffer... but we're not allowed to split the buffer. We need to fill the
//rest of the ringbuffer with a dummy item so we can place the data at the _start_ of
//the ringbuffer..
//First, find out if we actually have enough space at the start of the ringbuffer to
//make this work (Again, we need 4 bytes extra because otherwise read_ptr==free_ptr)
if (rb->free_ptr-rb->data < rbuffer_size+sizeof(buf_entry_hdr_t)+4) {
//Will not fit.
return pdFALSE;
}
//If the read buffer hasn't wrapped around yet, there's no way this will work either.
if (rb->free_ptr > rb->write_ptr) {
//No luck.
return pdFALSE;
}
//Okay, it will fit. Mark the rest of the ringbuffer space with a dummy packet.
buf_entry_hdr_t *hdr=(buf_entry_hdr_t *)rb->write_ptr;
hdr->flags=iflag_dummydata;
//Reset the write pointer to the start of the ringbuffer so the code later on can
//happily write the data.
rb->write_ptr=rb->data;
}
} else {
//No special handling needed. Checking if it's gonna fit probably still is a good idea.
if (ringbufferFreeMem(rb) < sizeof(buf_entry_hdr_t)+rbuffer_size) {
//Buffer is not going to fit, period.
return pdFALSE;
}
}
//If we are here, the buffer is guaranteed to fit in the space starting at the write pointer.
buf_entry_hdr_t *hdr=(buf_entry_hdr_t *)rb->write_ptr;
hdr->len=buffer_size;
hdr->flags=0;
rb->write_ptr+=sizeof(buf_entry_hdr_t);
memcpy(rb->write_ptr, buffer, buffer_size);
rb->write_ptr+=rbuffer_size;
//The buffer will wrap around if we don't have room for a header anymore.
if ((rb->data+rb->size)-rb->write_ptr < sizeof(buf_entry_hdr_t)) {
//'Forward' the write buffer until we are at the start of the ringbuffer.
//The read pointer will always be at the start of a full header, which cannot
//exist at the point of the current write pointer, so there's no chance of overtaking
//that.
rb->write_ptr=rb->data;
}
return pdTRUE;
}
//Retrieves a pointer to the data of the next item, or NULL if this is not possible.
//This function by itself is not threadsafe, always call from within a muxed section.
static uint8_t *getItemFromRingbuf(ringbuf_t *rb, size_t *length)
{
uint8_t *ret;
configASSERT(((int)rb->read_ptr&3)==0);
if (rb->read_ptr == rb->write_ptr) {
//No data available.
return NULL;
}
//The item written at the point of the read pointer may be a dummy item.
//We need to skip past it first, if that's the case.
buf_entry_hdr_t *hdr=(buf_entry_hdr_t *)rb->read_ptr;
configASSERT((hdr->len < rb->size) || (hdr->flags & iflag_dummydata));
if (hdr->flags & iflag_dummydata) {
//Hdr is dummy data. Reset to start of ringbuffer.
rb->read_ptr=rb->data;
//Get real header
hdr=(buf_entry_hdr_t *)rb->read_ptr;
configASSERT(hdr->len < rb->size);
//No need to re-check if the ringbuffer is empty: the write routine will
//always write a dummy item plus the real data item in one go, so now we must
//be at the real data item by definition.
}
//Okay, pass the data back.
ret=rb->read_ptr+sizeof(buf_entry_hdr_t);
*length=hdr->len;
//...and move the read pointer past the data.
rb->read_ptr+=sizeof(buf_entry_hdr_t)+((hdr->len+3)&~3);
//The buffer will wrap around if we don't have room for a header anymore.
if ((rb->data + rb->size) - rb->read_ptr < sizeof(buf_entry_hdr_t)) {
rb->read_ptr=rb->data;
}
return ret;
}
//Returns an item to the ringbuffer. Will mark the item as free, and will see if the free pointer
//can be increase.
//This function by itself is not threadsafe, always call from within a muxed section.
static void returnItemToRingbuf(ringbuf_t *rb, void *item) {
uint8_t *data=(uint8_t*)item;
configASSERT(((int)rb->free_ptr&3)==0);
configASSERT(data >= rb->data);
configASSERT(data < rb->data+rb->size);
//Grab the buffer entry that preceeds the buffer
buf_entry_hdr_t *hdr=(buf_entry_hdr_t*)(data-sizeof(buf_entry_hdr_t));
configASSERT(hdr->len < rb->size);
configASSERT((hdr->flags & iflag_dummydata)==0);
configASSERT((hdr->flags & iflag_free)==0);
//Mark the buffer as free.
hdr->flags|=iflag_free;
//Do a cleanup pass.
hdr=(buf_entry_hdr_t *)rb->free_ptr;
//basically forward free_ptr until we run into either a block that is still in use or the write pointer.
while (((hdr->flags & iflag_free) || (hdr->flags & iflag_dummydata)) && rb->free_ptr != rb->write_ptr) {
if (hdr->flags & iflag_dummydata) {
//Rest is dummy data. Reset to start of ringbuffer.
rb->free_ptr=rb->data;
} else {
//Skip past item
size_t len=(hdr->len+3)&~3;
rb->free_ptr+=len+sizeof(buf_entry_hdr_t);
configASSERT(rb->free_ptr<=rb->data+rb->size);
}
//The buffer will wrap around if we don't have room for a header anymore.
if ((rb->data+rb->size)-rb->free_ptr < sizeof(buf_entry_hdr_t)) {
rb->free_ptr=rb->data;
}
//Next header
hdr=(buf_entry_hdr_t *)rb->free_ptr;
}
}
void xRingbufferPrintInfo(RingbufHandle_t ringbuf)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
configASSERT(rb);
ets_printf("Rb size %d free %d rptr %d freeptr %d wptr %d\n",
rb->size, ringbufferFreeMem(rb), rb->read_ptr-rb->data, rb->free_ptr-rb->data, rb->write_ptr-rb->data);
}
RingbufHandle_t xRingbufferCreate(size_t buf_length, BaseType_t allow_split_items)
{
ringbuf_t *rb = malloc(sizeof(ringbuf_t));
if (rb==NULL) goto err;
memset(rb, 0, sizeof(ringbuf_t));
rb->data = malloc(buf_length);
if (rb->data == NULL) goto err;
rb->size = buf_length;
rb->free_ptr = rb->data;
rb->read_ptr = rb->data;
rb->write_ptr = rb->data;
rb->free_space_sem = xSemaphoreCreateBinary();
rb->items_buffered_sem = xSemaphoreCreateBinary();
rb->flags=0;
if (allow_split_items) rb->flags|=flag_allowsplit;
if (rb->free_space_sem == NULL || rb->items_buffered_sem == NULL) goto err;
vPortCPUInitializeMutex(&rb->mux);
return (RingbufHandle_t)rb;
err:
//Some error has happened. Free/destroy all allocated things and return NULL.
if (rb) {
free(rb->data);
if (rb->free_space_sem) vSemaphoreDelete(rb->free_space_sem);
if (rb->items_buffered_sem) vSemaphoreDelete(rb->items_buffered_sem);
}
free(rb);
return NULL;
}
void vRingbufferDelete(RingbufHandle_t ringbuf) {
ringbuf_t *rb=(ringbuf_t *)ringbuf;
if (rb) {
free(rb->data);
if (rb->free_space_sem) vSemaphoreDelete(rb->free_space_sem);
if (rb->items_buffered_sem) vSemaphoreDelete(rb->items_buffered_sem);
}
free(rb);
}
size_t xRingbufferGetMaxItemSize(RingbufHandle_t ringbuf)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
configASSERT(rb);
//In both cases, we return 4 bytes less than what we actually can have. If the ringbuffer is
//indeed entirely filled, read_ptr==free_ptr, which throws off the free space calculation.
if (rb->flags & flag_allowsplit) {
//Worst case, we need to split an item into two, which means two headers of overhead.
return rb->size-(sizeof(buf_entry_hdr_t)*2)-4;
} else {
//Worst case, we have the write ptr in such a position that we are lacking four bytes of free
//memory to put an item into the rest of the memory. If this happens, we have to dummy-fill
//(item_data-4) bytes of buffer, then we only have (size-(item_data-4) bytes left to fill
//with the real item. (item size being header+data)
return (rb->size/2)-sizeof(buf_entry_hdr_t)-4;
}
}
BaseType_t xRingbufferSend(RingbufHandle_t ringbuf, void *data, size_t dataSize, TickType_t ticks_to_wait)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
size_t needed_size=dataSize+sizeof(buf_entry_hdr_t);
BaseType_t done=pdFALSE;
portTickType ticks_end=xTaskGetTickCount() + ticks_to_wait;
configASSERT(rb);
if (dataSize > xRingbufferGetMaxItemSize(ringbuf)) {
//Data will never ever fit in the queue.
return pdFALSE;
}
while (!done) {
//Check if there is enough room in the buffer. If not, wait until there is.
do {
if (ringbufferFreeMem(rb) < needed_size) {
//Data does not fit yet. Wait until the free_space_sem is given, then re-evaluate.
BaseType_t r = xSemaphoreTake(rb->free_space_sem, ticks_to_wait);
if (r == pdFALSE) {
//Timeout.
return pdFALSE;
}
//Adjust ticks_to_wait; we may have waited less than that and in the case the free memory still is not enough,
//we will need to wait some more.
ticks_to_wait = ticks_end - xTaskGetTickCount();
}
} while (ringbufferFreeMem(rb) < needed_size && ticks_to_wait>=0);
//Lock the mux in order to make sure no one else is messing with the ringbuffer and do the copy.
portENTER_CRITICAL(&rb->mux);
//Another thread may have been able to sneak its write first. Check again now we locked the ringbuff, and retry
//everything if this is the case. Otherwise, we can write and are done.
done=copyItemToRingbuf(rb, data, dataSize);
portEXIT_CRITICAL(&rb->mux);
}
xSemaphoreGive(rb->items_buffered_sem);
return pdTRUE;
}
BaseType_t xRingbufferSendFromISR(RingbufHandle_t ringbuf, void *data, size_t dataSize, BaseType_t *higher_prio_task_awoken)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
BaseType_t write_succeeded;
configASSERT(rb);
size_t needed_size=dataSize+sizeof(buf_entry_hdr_t);
portENTER_CRITICAL_ISR(&rb->mux);
if (needed_size>ringbufferFreeMem(rb)) {
//Does not fit in the remaining space in the ringbuffer.
write_succeeded=pdFALSE;
} else {
copyItemToRingbuf(rb, data, dataSize);
write_succeeded=pdTRUE;
}
portEXIT_CRITICAL_ISR(&rb->mux);
if (write_succeeded) {
xSemaphoreGiveFromISR(rb->items_buffered_sem, higher_prio_task_awoken);
}
return write_succeeded;
}
void *xRingbufferReceive(RingbufHandle_t ringbuf, size_t *item_size, TickType_t ticks_to_wait)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
uint8_t *itemData;
BaseType_t done=pdFALSE;
configASSERT(rb);
while(!done) {
//See if there's any data available. If not, wait until there is.
while (rb->read_ptr == rb->write_ptr) {
BaseType_t r=xSemaphoreTake(rb->items_buffered_sem, ticks_to_wait);
if (r == pdFALSE) {
//Timeout.
return NULL;
}
}
//Okay, we seem to have data in the buffer. Grab the mux and copy it out if it's still there.
portENTER_CRITICAL(&rb->mux);
itemData=getItemFromRingbuf(rb, item_size);
portEXIT_CRITICAL(&rb->mux);
if (itemData) {
//We managed to get an item.
done=pdTRUE;
}
}
return (void*)itemData;
}
void *xRingbufferReceiveFromISR(RingbufHandle_t ringbuf, size_t *item_size)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
uint8_t *itemData;
configASSERT(rb);
portENTER_CRITICAL_ISR(&rb->mux);
itemData=getItemFromRingbuf(rb, item_size);
portEXIT_CRITICAL_ISR(&rb->mux);
return (void*)itemData;
}
void vRingbufferReturnItem(RingbufHandle_t ringbuf, void *item)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
portENTER_CRITICAL_ISR(&rb->mux);
returnItemToRingbuf(rb, item);
portEXIT_CRITICAL_ISR(&rb->mux);
xSemaphoreGive(rb->free_space_sem);
}
void vRingbufferReturnItemFromISR(RingbufHandle_t ringbuf, void *item, BaseType_t *higher_prio_task_awoken)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
portENTER_CRITICAL_ISR(&rb->mux);
returnItemToRingbuf(rb, item);
portEXIT_CRITICAL_ISR(&rb->mux);
xSemaphoreGiveFromISR(rb->free_space_sem, higher_prio_task_awoken);
}
BaseType_t xRingbufferAddToQueueSetRead(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
configASSERT(rb);
return xQueueAddToSet(rb->items_buffered_sem, xQueueSet);
}
BaseType_t xRingbufferAddToQueueSetWrite(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
configASSERT(rb);
return xQueueAddToSet(rb->free_space_sem, xQueueSet);
}
BaseType_t xRingbufferRemoveFromQueueSetRead(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
configASSERT(rb);
return xQueueRemoveFromSet(rb->items_buffered_sem, xQueueSet);
}
BaseType_t xRingbufferRemoveFromQueueSetWrite(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet)
{
ringbuf_t *rb=(ringbuf_t *)ringbuf;
configASSERT(rb);
return xQueueRemoveFromSet(rb->free_space_sem, xQueueSet);
}

65
components/freertos/tasks.c
View File

@@ -85,6 +85,7 @@ task.h is included from an application file. */
#include "StackMacros.h"
#include "portmacro.h"
#include "semphr.h"
#include "sys/reent.h"
/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
@@ -128,6 +129,9 @@ functions but without including stdio.h here. */
} while(0)
#endif
/* Value that can be assigned to the eNotifyState member of the TCB. */
typedef enum
{
@@ -156,7 +160,7 @@ typedef struct tskTaskControlBlock
StackType_t *pxStack; /*< Points to the start of the stack. */
char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
BaseType_t xCoreID; /*< Core this task is pinned to */
/* If this moves around (other than pcTaskName size changes), please change the define in xtensa_vectors.S as well. */
#if ( portSTACK_GROWTH > 0 )
StackType_t *pxEndOfStack; /*< Points to the end of the stack on architectures where the stack grows up from low memory. */
#endif
@@ -274,9 +278,7 @@ when the scheduler is unsuspended. The pending ready list itself can only be
accessed from a critical section. */
PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended[ portNUM_PROCESSORS ] = { ( UBaseType_t ) pdFALSE };
/* Muxes used in the task code */
PRIVILEGED_DATA static portBASE_TYPE xMutexesInitialised = pdFALSE;
/* For now, we use just one mux for all the critical sections. ToDo: give evrything a bit more granularity;
/* For now, we use just one mux for all the critical sections. ToDo: give everything a bit more granularity;
that could improve performance by not needlessly spinning in spinlocks for unrelated resources. */
PRIVILEGED_DATA static portMUX_TYPE xTaskQueueMutex = portMUX_INITIALIZER_UNLOCKED;
PRIVILEGED_DATA static portMUX_TYPE xTickCountMutex = portMUX_INITIALIZER_UNLOCKED;
@@ -576,15 +578,6 @@ static void prvResetNextTaskUnblockTime( void );
#endif
/*-----------------------------------------------------------*/
static void vTaskInitializeLocalMuxes( void )
{
vPortCPUInitializeMutex(&xTaskQueueMutex);
vPortCPUInitializeMutex(&xTickCountMutex);
xMutexesInitialised = pdTRUE;
}
/*-----------------------------------------------------------*/
@@ -594,10 +587,6 @@ BaseType_t xReturn;
TCB_t * pxNewTCB;
StackType_t *pxTopOfStack;
BaseType_t i;
/* Initialize mutexes, if they're not already initialized. */
if (xMutexesInitialised == pdFALSE) vTaskInitializeLocalMuxes();
configASSERT( pxTaskCode );
configASSERT( ( ( uxPriority & ( ~portPRIVILEGE_BIT ) ) < configMAX_PRIORITIES ) );
configASSERT( (xCoreID>=0 && xCoreID<portNUM_PROCESSORS) || (xCoreID==tskNO_AFFINITY) );
@@ -872,7 +861,7 @@ BaseType_t i;
TickType_t xTimeToWake;
BaseType_t xAlreadyYielded=pdFALSE, xShouldDelay = pdFALSE;
ets_printf("ToDo %s\n", __FUNCTION__);
UNTESTED_FUNCTION();
configASSERT( pxPreviousWakeTime );
configASSERT( ( xTimeIncrement > 0U ) );
configASSERT( uxSchedulerSuspended[ xPortGetCoreID() ] == 0 );
@@ -1042,7 +1031,7 @@ BaseType_t i;
List_t *pxStateList;
const TCB_t * const pxTCB = ( TCB_t * ) xTask;
ets_printf("ToDo %s\n", __FUNCTION__);
UNTESTED_FUNCTION();
configASSERT( pxTCB );
if( pxTCB == pxCurrentTCB[ xPortGetCoreID() ] )
@@ -1112,7 +1101,7 @@ BaseType_t i;
TCB_t *pxTCB;
UBaseType_t uxReturn;
ets_printf("ToDo %s\n", __FUNCTION__);
UNTESTED_FUNCTION();
taskENTER_CRITICAL(&xTaskQueueMutex);
{
/* If null is passed in here then we are changing the
@@ -1320,7 +1309,7 @@ BaseType_t i;
{
TCB_t *pxTCB;
ets_printf("ToDo %s\n", __FUNCTION__);
UNTESTED_FUNCTION();
taskENTER_CRITICAL(&xTaskQueueMutex);
{
/* If null is passed in here then it is the running task that is
@@ -1461,7 +1450,7 @@ BaseType_t i;
{
TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
ets_printf("ToDo %s\n", __FUNCTION__);
UNTESTED_FUNCTION();
/* It does not make sense to resume the calling task. */
configASSERT( xTaskToResume );
@@ -1724,10 +1713,6 @@ BaseType_t xAlreadyYielded = pdFALSE;
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
//This uses a mux, but can be called before tasks are scheduled. Make sure muxes are inited.
/* Initialize mutexes, if they're not already initialized. */
if (xMutexesInitialised == pdFALSE) vTaskInitializeLocalMuxes();
taskENTER_CRITICAL(&xTaskQueueMutex);
{
--uxSchedulerSuspended[ xPortGetCoreID() ];
@@ -1867,7 +1852,7 @@ UBaseType_t uxTaskGetNumberOfTasks( void )
{
UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
ets_printf("ToDo %s\n", __FUNCTION__);
UNTESTED_FUNCTION();
vTaskSuspendAll(); //WARNING: This only suspends one CPU. ToDo: suspend others as well. Mux using taskQueueMutex maybe?
{
/* Is there a space in the array for each task in the system? */
@@ -3153,7 +3138,7 @@ UBaseType_t x;
{
TCB_t *pxTCB;
ets_printf("ToDo %s\n", __FUNCTION__);
UNTESTED_FUNCTION();
/* If null is passed in here then we are deleting ourselves. */
pxTCB = prvGetTCBFromHandle( xTaskToModify );
@@ -3354,6 +3339,17 @@ TCB_t *pxNewTCB;
}
/*-----------------------------------------------------------*/
BaseType_t xTaskGetAffinity( TaskHandle_t xTask )
{
TCB_t *pxTCB;
pxTCB = prvGetTCBFromHandle( xTask );
return pxTCB->xCoreID;
}
/*-----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )
static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
@@ -3361,6 +3357,7 @@ TCB_t *pxNewTCB;
volatile TCB_t *pxNextTCB, *pxFirstTCB;
UBaseType_t uxTask = 0;
UNTESTED_FUNCTION();
if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
{
listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
@@ -3467,6 +3464,7 @@ TCB_t *pxNewTCB;
uint8_t *pucEndOfStack;
UBaseType_t uxReturn;
UNTESTED_FUNCTION();
pxTCB = prvGetTCBFromHandle( xTask );
#if portSTACK_GROWTH < 0
@@ -3489,6 +3487,9 @@ TCB_t *pxNewTCB;
#if ( INCLUDE_vTaskDelete == 1 )
// TODO: move this to newlib component and provide a header file
extern void _extra_cleanup_r(struct _reent* r);
static void prvDeleteTCB( TCB_t *pxTCB )
{
/* This call is required specifically for the TriCore port. It must be
@@ -3500,6 +3501,7 @@ TCB_t *pxNewTCB;
to the task to free any memory allocated at the application level. */
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
pxTCB->xNewLib_reent.__cleanup = &_extra_cleanup_r;
_reclaim_reent( &( pxTCB->xNewLib_reent ) );
}
#endif /* configUSE_NEWLIB_REENTRANT */
@@ -3894,6 +3896,7 @@ scheduler will re-enable the interrupts instead. */
TaskStatus_t *pxTaskStatusArray;
volatile UBaseType_t uxArraySize, x;
char cStatus;
UNTESTED_FUNCTION();
/*
* PLEASE NOTE:
@@ -3987,6 +3990,7 @@ scheduler will re-enable the interrupts instead. */
volatile UBaseType_t uxArraySize, x;
uint32_t ulTotalTime, ulStatsAsPercentage;
UNTESTED_FUNCTION();
#if( configUSE_TRACE_FACILITY != 1 )
{
#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
@@ -4144,6 +4148,7 @@ TickType_t uxReturn;
TickType_t xTimeToWake;
uint32_t ulReturn;
UNTESTED_FUNCTION();
taskENTER_CRITICAL(&xTaskQueueMutex);
{
/* Only block if the notification count is not already non-zero. */
@@ -4254,6 +4259,7 @@ TickType_t uxReturn;
TickType_t xTimeToWake;
BaseType_t xReturn;
UNTESTED_FUNCTION();
taskENTER_CRITICAL(&xTaskQueueMutex);
{
/* Only block if a notification is not already pending. */
@@ -4376,6 +4382,7 @@ TickType_t uxReturn;
eNotifyValue eOriginalNotifyState;
BaseType_t xReturn = pdPASS;
UNTESTED_FUNCTION();
configASSERT( xTaskToNotify );
pxTCB = ( TCB_t * ) xTaskToNotify;
@@ -4460,6 +4467,7 @@ TickType_t uxReturn;
eNotifyValue eOriginalNotifyState;
BaseType_t xReturn = pdPASS;
UNTESTED_FUNCTION();
configASSERT( xTaskToNotify );
pxTCB = ( TCB_t * ) xTaskToNotify;
@@ -4553,6 +4561,7 @@ TickType_t uxReturn;
TCB_t * pxTCB;
eNotifyValue eOriginalNotifyState;
UNTESTED_FUNCTION();
configASSERT( xTaskToNotify );

20
components/freertos/xtensa_vectors.S
View File

@@ -92,6 +92,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "xtensa_rtos.h"
/*
Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used.
Please change this when the tcb structure is changed
*/
#define TASKTCB_XCOREID_OFFSET (0x3C+configMAX_TASK_NAME_LEN+3)&~3
.extern pxCurrentTCB
/* Enable stack backtrace across exception/interrupt - see below */
#define XT_DEBUG_BACKTRACE 0
@@ -892,6 +898,20 @@ _xt_coproc_exc:
addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */
l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */
/* TODO: Remove this as soon as coprocessor state moving works across cores - JD */
/* FPU operations are incompatible with non-pinned tasks. If we have a FPU operation
here, to keep the entire thing from crashing, it's better to pin the task to whatever
core we're running on now. */
movi a2, pxCurrentTCB
getcoreid a3
slli a3, a3, 2
add a2, a2, a3
l32i a2, a2, 0 /* a2 = start of pxCurrentTCB[cpuid] */
addi a2, a2, TASKTCB_XCOREID_OFFSET /* offset to xCoreID in tcb struct */
getcoreid a3
s32i a3, a2, 0 /* store current cpuid */
/* Grab correct xt_coproc_owner_sa for this core */
getcoreid a2
movi a3, XCHAL_CP_MAX << 2
mull a2, a2, a3

61
components/idf_test/README.md Normal file
View File

@@ -0,0 +1,61 @@
# Note: The test cases in this folder are for Espressif internal use.
# Goto internal project wiki Testing page for detail about this folder.
## File Structure
```
test --- CIConfigs --- sanity_test1.yml (Runner config files)
| |-- stress_test1.yml
|-- TestCaseAll.yml (TestCaseFiles)
|-- TestEnvAll.yml (TestCaseFiles)
|-- InitialConditionAll.yml (TestCaseFiles)
|-- TestCaseScript --- ... (Test case scripts)
```
1. CIConfigs folder
* config for CI config files are put in this folder
* CI config files configs the cases and some other options for the CI job with same name
1. Test case files
* TestCaseAll.yml (test cases)
* InitialConditionAll.yml (initial conditions)
* TestEnvAll.yml (test environments)
* [how to modify test cases](https://gitlab.espressif.cn:6688/yinling/auto_test_script/blob/master/public/Design/TestCaseFiles.DesignNote.md)
1. Test case scripts
* some cases are implemented by specified script. those scripts are put in this folder.
## Modify test cases
1. check if the "SDK" of the test case only contain the current SDK
* if Yes, then just modify the test case behavior
* if No:
1. then remove current SDK name from "SDK" of the test case
2. Add a new test case, and set "SDK" only support current SDK name
2. use [auto_test_script](https://gitlab.espressif.cn:6688/yinling/auto_test_script) to load the modified case and verify the modification
3. create a merge request and assign to HYL (or add comment @yinling for merging test).
After review it will be merged to SDK and will be The cases will be synced to database in auto_test_script.
## Run test case locally
1. clone auto_test_script (ssh://git@gitlab.espressif.cn:27227/yinling/auto_test_script.git) from gitlab
2. create test environment:
1. search test case (search test case ID in components/test/TestCaseAll.yml, get the "test environment" value
2. goto [test environment list](https://gitlab.espressif.cn:6688/yinling/auto_test_script/blob/master/public/Documents/TestEnvList.md), find the link and goto the environment detail page
3. create test environment according to figure and description
4. [config test environment](https://gitlab.espressif.cn:6688/yinling/auto_test_script/blob/master/public/Design/TestEnvConfig.DesignNote.md). All parameters in table "Parameters require config before use" MUST be configured.
3. run test cases with [CIRunner.py](https://gitlab.espressif.cn:6688/yinling/auto_test_script/blob/master/public/Design/RunnerConfigs.DesignNote.md)
## exclude known issues for CI
the test cases listed in file "KnownIssues" will be excluded by CI when calculating results
Editing KnownIssues file is very simple, one single line for the ID for each case.
```
TCPIP_TCP_0101
TCPIP_TCP_0201
...
```

5
components/idf_test/integration_test/CIConfigs/IT_Function_SYS_01.yml Normal file
View File

@@ -0,0 +1,5 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [SYS_MISC_0101, SYS_MISC_0201]

10
components/idf_test/integration_test/CIConfigs/IT_Function_TCPIP_01.yml Normal file
View File

@@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^TCPIP_DHCP_0302, TCPIP_DHCP_0302, TCPIP_DHCP_0301, TCPIP_TCP_0403, TCPIP_TCP_0402,
TCPIP_TCP_0401, TCPIP_TCP_0407, TCPIP_TCP_0406, ^TCPIP_TCP_0411, TCPIP_TCP_0404,
TCPIP_TCP_0408, TCPIP_TCP_0110, TCPIP_TCP_0115, TCPIP_IP_0101, TCPIP_IP_0102,
^TCPIP_IGMP_0102, ^TCPIP_IGMP_0101, ^TCPIP_IGMP_0104, TCPIP_IGMP_0104, TCPIP_IGMP_0103,
TCPIP_IGMP_0102, TCPIP_IGMP_0101, TCPIP_UDP_0108, TCPIP_UDP_0106, TCPIP_UDP_0107,
TCPIP_UDP_0105, TCPIP_UDP_0101, TCPIP_IGMP_0204, TCPIP_IGMP_0201, TCPIP_IGMP_0202]

10
components/idf_test/integration_test/CIConfigs/IT_Function_TCPIP_02.yml Normal file
View File

@@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [TCPIP_IGMP_0203, ^TCPIP_TCP_0403, ^TCPIP_TCP_0408, TCPIP_UDP_0201, TCPIP_UDP_0202,
^TCPIP_DHCP_0301, ^TCPIP_TCP_0101, ^TCPIP_TCP_0103, ^TCPIP_TCP_0105, ^TCPIP_TCP_0104,
^TCPIP_TCP_0107, ^TCPIP_TCP_0106, ^TCPIP_DHCP_0210, ^TCPIP_DHCP_0211, ^TCPIP_TCP_0404,
TCPIP_TCP_0212, TCPIP_TCP_0210, ^TCPIP_TCP_0406, ^TCPIP_TCP_0407, ^TCPIP_TCP_0401,
^TCPIP_TCP_0210, ^TCPIP_TCP_0212, TCPIP_DHCP_0211, TCPIP_DHCP_0210, TCPIP_DHCP_0101,
TCPIP_DHCP_0103, TCPIP_DHCP_0102, TCPIP_DHCP_0206, TCPIP_DHCP_0207, ^TCPIP_IP_0102]

10
components/idf_test/integration_test/CIConfigs/IT_Function_TCPIP_03.yml Normal file
View File

@@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^TCPIP_UDP_0105, ^TCPIP_UDP_0107, ^TCPIP_UDP_0106, ^TCPIP_UDP_0101, TCPIP_TCP_0203,
TCPIP_TCP_0202, ^TCPIP_UDP_0108, ^TCPIP_IGMP_0201, ^TCPIP_IGMP_0203, ^TCPIP_IGMP_0202,
^TCPIP_IGMP_0103, TCPIP_UDP_0114, TCPIP_UDP_0113, TCPIP_UDP_0112, TCPIP_DHCP_0205,
TCPIP_DHCP_0202, TCPIP_DHCP_0203, ^TCPIP_TCP_0102, TCPIP_TCP_0106, TCPIP_TCP_0107,
TCPIP_TCP_0104, TCPIP_TCP_0105, TCPIP_TCP_0102, TCPIP_TCP_0103, TCPIP_TCP_0101,
^TCPIP_TCP_0116, ^TCPIP_TCP_0114, ^TCPIP_TCP_0115, ^TCPIP_TCP_0112, ^TCPIP_TCP_0113]

10
components/idf_test/integration_test/CIConfigs/IT_Function_TCPIP_04.yml Normal file
View File

@@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^TCPIP_TCP_0110, ^TCPIP_TCP_0111, TCPIP_DHCP_0209, ^TCPIP_DHCP_0209, ^TCPIP_DHCP_0207,
^TCPIP_DHCP_0206, ^TCPIP_DHCP_0205, ^TCPIP_DHCP_0204, ^TCPIP_DHCP_0203, ^TCPIP_DHCP_0202,
^TCPIP_DHCP_0201, TCPIP_TCP_0204, TCPIP_TCP_0207, TCPIP_TCP_0206, TCPIP_TCP_0201,
^TCPIP_DHCP_0101, ^TCPIP_DHCP_0102, ^TCPIP_DHCP_0103, ^TCPIP_DHCP_0208, TCPIP_TCP_0208,
^TCPIP_TCP_0202, ^TCPIP_TCP_0203, TCPIP_DHCP_0204, ^TCPIP_TCP_0201, ^TCPIP_TCP_0206,
^TCPIP_TCP_0207, ^TCPIP_TCP_0204, TCPIP_DHCP_0201, ^TCPIP_TCP_0208, TCPIP_DHCP_0208]

8
components/idf_test/integration_test/CIConfigs/IT_Function_TCPIP_05.yml Normal file
View File

@@ -0,0 +1,8 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [^TCPIP_IGMP_0204, ^TCPIP_TCP_0412, TCPIP_TCP_0411, TCPIP_TCP_0412, ^TCPIP_UDP_0112,
^TCPIP_UDP_0113, ^TCPIP_UDP_0114, ^TCPIP_UDP_0202, ^TCPIP_UDP_0201, ^TCPIP_IP_0101,
^TCPIP_TCP_0402, TCPIP_TCP_0114, TCPIP_TCP_0116, TCPIP_TCP_0111, TCPIP_TCP_0113,
TCPIP_TCP_0112]

5
components/idf_test/integration_test/CIConfigs/IT_Function_TCPIP_06.yml Normal file
View File

@@ -0,0 +1,5 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [TCPIP_TCP_0405, ^TCPIP_TCP_0405]

10
components/idf_test/integration_test/CIConfigs/IT_Function_TCPIP_07.yml Normal file
View File

@@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC2, SSC1]
Filter:
- Add:
ID: [TCPIP_ICMP_0101, TCPIP_ICMP_0101, TCPIP_ICMP_0101, TCPIP_ICMP_0101, TCPIP_ICMP_0101,
TCPIP_DNS_0102, TCPIP_DNS_0102, TCPIP_DNS_0102, TCPIP_DNS_0102, TCPIP_DNS_0102,
TCPIP_DNS_0101, TCPIP_DNS_0101, TCPIP_DNS_0101, TCPIP_DNS_0101, TCPIP_DNS_0101,
^TCPIP_ICMP_0101, ^TCPIP_ICMP_0101, ^TCPIP_ICMP_0101, ^TCPIP_ICMP_0101, ^TCPIP_ICMP_0101,
TCPIP_UDP_0109, TCPIP_UDP_0109, TCPIP_UDP_0109, TCPIP_UDP_0109, TCPIP_UDP_0109,
TCPIP_UDP_0104, TCPIP_UDP_0104, TCPIP_UDP_0104, TCPIP_UDP_0104, TCPIP_UDP_0104]

10
components/idf_test/integration_test/CIConfigs/IT_Function_TCPIP_08.yml Normal file
View File

@@ -0,0 +1,10 @@
Config: {execute count: 1, execute order: in order}
DUT: [SSC1]
Filter:
- Add:
ID: [TCPIP_UDP_0102, TCPIP_UDP_0102, TCPIP_UDP_0102, TCPIP_UDP_0102, TCPIP_UDP_0102,
TCPIP_UDP_0103, TCPIP_UDP_0103, TCPIP_UDP_0103, TCPIP_UDP_0103, TCPIP_UDP_0103,
^TCPIP_UDP_0307, ^TCPIP_UDP_0307, ^TCPIP_UDP_0307, ^TCPIP_UDP_0307, ^TCPIP_UDP_0307,
^TCPIP_UDP_0306, ^TCPIP_UDP_0306, ^TCPIP_UDP_0306, ^TCPIP_UDP_0306, ^TCPIP_UDP_0306,
^TCPIP_UDP_0305, ^TCPIP_UDP_0305, ^TCPIP_UDP_0305, ^TCPIP_UDP_0305, ^TCPIP_UDP_0305,
^TCPIP_UDP_0304, ^TCPIP_UDP_0304, ^TCPIP_UDP_0304, ^TCPIP_UDP_0304, ^TCPIP_UDP_0304]

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