feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

Merge branch 'fix/fix_s2_s3_rtc_iomux_clock_management_v5.2' into 'release/v5.2'

Browse Source 
fix(esp_hw_support): fix esp32s2/esp32s3 RTC IOMUX clock management (v5.2)

See merge request espressif/esp-idf!37168
This commit is contained in:
Jiang Jiang Jian
2025-02-28 15:24:28 +08:00
parent 41c2b799ad aff8ad355b
commit 2dd257d162
16 changed files with 230 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
components/driver/gpio/gpio.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -23,6 +23,7 @@
#include "hal/gpio_hal.h"
#include "esp_rom_gpio.h"
#include "esp_private/esp_gpio_reserve.h"
#include "esp_private/io_mux.h"
#if (SOC_RTCIO_PIN_COUNT > 0)
#include "hal/rtc_io_hal.h"
@@ -632,6 +633,11 @@ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
if ((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) {
#if SOC_RTCIO_WAKE_SUPPORTED
if (rtc_gpio_is_valid_gpio(gpio_num)) {
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
// LP_IO Wake-up function does not depend on LP_IO Matrix, but uses its clock to
// sample the wake-up signal, we need to enable the LP_IO clock here.
io_mux_enable_lp_io_clock(gpio_num, true);
#endif
ret = rtc_gpio_wakeup_enable(gpio_num, intr_type);
}
#endif
@@ -657,6 +663,9 @@ esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num)
#if SOC_RTCIO_WAKE_SUPPORTED
if (rtc_gpio_is_valid_gpio(gpio_num)) {
ret = rtc_gpio_wakeup_disable(gpio_num);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(gpio_num, false);
#endif
}
#endif
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
@@ -984,6 +993,9 @@ esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t int
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(gpio_num, true);
#endif
gpio_hal_deepsleep_wakeup_enable(gpio_context.gpio_hal, gpio_num, intr_type);
#if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO
gpio_hal_sleep_sel_dis(gpio_context.gpio_hal, gpio_num);
@@ -1002,6 +1014,9 @@ esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num)
gpio_hal_deepsleep_wakeup_disable(gpio_context.gpio_hal, gpio_num);
#if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO
gpio_hal_sleep_sel_en(gpio_context.gpio_hal, gpio_num);
#endif
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(gpio_num, false);
#endif
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
return ESP_OK;

11
components/driver/gpio/rtc_io.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,8 @@
#include "esp_log.h"
#include "esp_err.h"
#include "esp_check.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/io_mux.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/timers.h"
@@ -45,6 +47,9 @@ esp_err_t rtc_gpio_init(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(gpio_num, true);
#endif
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_RTC);
RTCIO_EXIT_CRITICAL();
@@ -57,6 +62,10 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num)
RTCIO_ENTER_CRITICAL();
// Select Gpio as Digital Gpio
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_DIGITAL);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_force_disable_lp_io_clock(gpio_num);
#endif
RTCIO_EXIT_CRITICAL();
return ESP_OK;

26
components/esp_hw_support/include/esp_private/io_mux.h
View File

@@ -1,13 +1,17 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#include "soc/clk_tree_defs.h"
#include "soc/gpio_num.h"
#include "soc/soc_caps.h"
#include "soc/io_mux_reg.h"
#ifdef __cplusplus
extern "C" {
@@ -26,6 +30,26 @@ extern "C" {
*/
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
typedef struct {
uint8_t rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM];
uint32_t rtc_io_using_mask;
} rtc_io_status_t;
/**
* Enable/Disable LP_IO peripheral clock.
* @param gpio_num GPIO number
* @param enable true to enable the clock / false to disable the clock
*/
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable);
/**
* Force disable one LP_IO to clock dependency
* @param gpio_num GPIO number
*/
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num);
#endif
#ifdef __cplusplus
}
#endif

56
components/esp_hw_support/port/esp32s2/io_mux.c
View File

@@ -1,13 +1,67 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "esp_attr.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/io_mux.h"
#include "hal/rtc_io_ll.h"
#define RTCIO_RCC_ATOMIC() \
for (int _rc_cnt = 1; \
_rc_cnt ? (portENTER_CRITICAL(&rtc_spinlock), 1) : 0; \
portEXIT_CRITICAL(&rtc_spinlock), _rc_cnt--)
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
{
// IO MUX clock source is not selectable
return ESP_OK;
}
extern portMUX_TYPE rtc_spinlock;
static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
static rtc_io_status_t s_rtc_io_status = {
.rtc_io_enabled_cnt = { 0 },
.rtc_io_using_mask = 0
};
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
}
}
RTCIO_RCC_ATOMIC() {
if (s_rtc_io_status.rtc_io_using_mask == 0) {
rtcio_ll_enable_io_clock(false);
} else {
rtcio_ll_enable_io_clock(true);
}
}
portEXIT_CRITICAL(&s_io_mux_spinlock);
}
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
}
}
portEXIT_CRITICAL(&s_io_mux_spinlock);
}

56
components/esp_hw_support/port/esp32s3/io_mux.c
View File

@@ -1,13 +1,67 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "esp_attr.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/io_mux.h"
#include "hal/rtc_io_ll.h"
#define RTCIO_RCC_ATOMIC() \
for (int _rc_cnt = 1; \
_rc_cnt ? (portENTER_CRITICAL(&rtc_spinlock), 1) : 0; \
portEXIT_CRITICAL(&rtc_spinlock), _rc_cnt--)
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
{
// IO MUX clock source is not selectable
return ESP_OK;
}
extern portMUX_TYPE rtc_spinlock;
static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
static rtc_io_status_t s_rtc_io_status = {
.rtc_io_enabled_cnt = { 0 },
.rtc_io_using_mask = 0
};
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
}
}
RTCIO_RCC_ATOMIC() {
if (s_rtc_io_status.rtc_io_using_mask == 0) {
rtcio_ll_enable_io_clock(false);
} else {
rtcio_ll_enable_io_clock(true);
}
}
portEXIT_CRITICAL(&s_io_mux_spinlock);
}
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
}
}
portEXIT_CRITICAL(&s_io_mux_spinlock);
}

3
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@@ -19,6 +19,7 @@
#include "esp_hw_log.h"
#include "hal/clk_tree_ll.h"
#include "hal/regi2c_ctrl_ll.h"
#include "hal/rtc_io_ll.h"
#include "esp_private/regi2c_ctrl.h"
#include "soc/regi2c_dig_reg.h"
#include "soc/sens_reg.h"
@@ -65,7 +66,7 @@ void rtc_clk_32k_enable(bool enable)
void rtc_clk_32k_enable_external(void)
{
PIN_INPUT_ENABLE(IO_MUX_GPIO15_REG);
SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_IOMUX_CLK_EN);
rtcio_ll_enable_io_clock(true);
SET_PERI_REG_MASK(RTC_CNTL_PAD_HOLD_REG, RTC_CNTL_X32P_HOLD);
clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL);
}

11
components/esp_hw_support/sleep_modes.c
View File

@@ -14,8 +14,10 @@
#include "esp_sleep.h"
#include "esp_private/esp_sleep_internal.h"
#include "esp_private/esp_timer_private.h"
#include "esp_private/rtc_clk.h"
#include "esp_private/sleep_event.h"
#include "esp_private/system_internal.h"
#include "esp_private/io_mux.h"
#include "esp_log.h"
#include "esp_newlib.h"
#include "esp_timer.h"
@@ -1606,6 +1608,9 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
static void ext0_wakeup_prepare(void)
{
int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
rtcio_ll_enable_io_clock(true);
#endif
rtcio_hal_ext0_set_wakeup_pin(rtc_gpio_num, s_config.ext0_trigger_level);
rtcio_hal_function_select(rtc_gpio_num, RTCIO_LL_FUNC_RTC);
rtcio_hal_input_enable(rtc_gpio_num);
@@ -1735,6 +1740,9 @@ static void ext1_wakeup_prepare(void)
if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
continue;
}
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
rtcio_ll_enable_io_clock(true);
#endif
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
// Route pad to RTC
rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_RTC);
@@ -1806,6 +1814,9 @@ static void gpio_deep_sleep_wakeup_prepare(void)
if (((1ULL << gpio_idx) & s_config.gpio_wakeup_mask) == 0) {
continue;
}
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
rtcio_ll_enable_io_clock(true);
#endif
#if CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS
if (s_config.gpio_trigger_mode & BIT(gpio_idx)) {
ESP_ERROR_CHECK(gpio_pullup_dis(gpio_idx));

21
components/hal/esp32s2/include/hal/rtc_io_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,6 +13,7 @@
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/rtc_io_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_periph.h"
@@ -25,7 +26,7 @@ extern "C" {
#endif
typedef enum {
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
@@ -51,6 +52,16 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, 0x3, func, rtc_io_desc[rtcio_num].func);
}
/**
* @brief Enable/Disable LP IOMUX clock.
*
* @param enable true to enable the clock / false to disable the clock
*/
static inline void rtcio_ll_enable_io_clock(bool enable)
{
SENS.sar_io_mux_conf.iomux_clk_gate_en = enable;
}
/**
* @brief Select the rtcio function.
*
@@ -61,14 +72,12 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_LL_FUNC_RTC) {
SENS.sar_io_mux_conf.iomux_clk_gate_en = 1;
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
}
}
@@ -281,8 +290,7 @@ static inline void rtcio_ll_force_unhold_all(void)
*/
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
SENS.sar_io_mux_conf.iomux_clk_gate_en = 1;
RTCIO.pin[rtcio_num].wakeup_enable = 0x1;
RTCIO.pin[rtcio_num].wakeup_enable = 1;
RTCIO.pin[rtcio_num].int_type = type;
}
@@ -293,7 +301,6 @@ static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t ty
*/
static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
RTCIO.pin[rtcio_num].wakeup_enable = 0;
RTCIO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE;
}

18
components/hal/esp32s3/include/hal/rtc_io_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,6 +13,7 @@
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/rtc_io_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_periph.h"
@@ -42,6 +43,16 @@ typedef enum {
RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
* @brief Enable/Disable LP IOMUX clock.
*
* @param enable true to enable the clock / false to disable the clock
*/
static inline void rtcio_ll_enable_io_clock(bool enable)
{
SENS.sar_peri_clk_gate_conf.iomux_clk_en = enable;
}
/**
* @brief Select a RTC IOMUX function for the RTC IO
*
@@ -67,14 +78,12 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
if (rtcio_num == rtc_io_num_map[USB_INT_PHY0_DM_GPIO_NUM] || rtcio_num == rtc_io_num_map[USB_INT_PHY0_DP_GPIO_NUM]) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
SENS.sar_peri_clk_gate_conf.iomux_clk_en = 1;
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
SENS.sar_peri_clk_gate_conf.iomux_clk_en = 0;
// USB Serial JTAG pad re-enable won't be done here (it requires both DM and DP pins not in rtc function)
// Instead, USB_SERIAL_JTAG_USB_PAD_ENABLE needs to be guaranteed to be set in usb_serial_jtag driver
}
@@ -307,8 +316,7 @@ static inline void rtcio_ll_force_unhold_all(void)
*/
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
SENS.sar_peri_clk_gate_conf.iomux_clk_en = 1;
RTCIO.pin[rtcio_num].wakeup_enable = 0x1;
RTCIO.pin[rtcio_num].wakeup_enable = 1;
RTCIO.pin[rtcio_num].int_type = type;
}

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@@ -619,6 +619,10 @@ config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_SDM_GROUPS
int
default 1

2
components/soc/esp32s2/include/soc/soc_caps.h
View File

@@ -268,6 +268,8 @@
*/
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT 1
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@@ -759,6 +759,10 @@ config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_SDM_GROUPS
bool
default y

2
components/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -304,6 +304,8 @@
*/
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT 1
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1

7
components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -29,11 +29,16 @@ typedef enum {
/**
* @brief Initialize a rtcio pin
* @note If IO is used in LP application, `rtc_gpio_init` must be called at least once
* for the using IO before loading LP core firmware in HP Code.
*
* @param lp_io_num The rtc io pin to initialize
*/
static inline void ulp_lp_core_gpio_init(lp_io_num_t lp_io_num)
{
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
_rtcio_ll_enable_io_clock(true);
#endif
rtcio_ll_function_select(lp_io_num, RTCIO_LL_FUNC_RTC);
}

7
components/ulp/test_apps/lp_core/main/test_lp_core.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,6 +7,9 @@
#include <stdio.h>
#include <inttypes.h>
#include <sys/time.h>
#include "soc/soc_caps.h"
#include "soc/gpio_num.h"
#include "esp_rom_caps.h"
#include "lp_core_test_app.h"
#include "lp_core_test_app_counter.h"
#include "lp_core_test_app_set_timer_wakeup.h"
@@ -17,6 +20,7 @@
#include "unity.h"
#include "esp_sleep.h"
#include "esp_timer.h"
#include "driver/rtc_io.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
@@ -301,6 +305,7 @@ TEST_CASE("LP core gpio tests", "[ulp]")
.lp_timer_sleep_duration_us = LP_TIMER_TEST_SLEEP_DURATION_US,
};
rtc_gpio_init(GPIO_NUM_0);
load_and_start_lp_core_firmware(&cfg, lp_core_main_gpio_bin_start, lp_core_main_gpio_bin_end);
while(!ulp_gpio_test_finished) {

10
components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,10 +11,12 @@ extern "C" {
#endif
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "soc/rtc_io_reg.h"
#include "soc/sens_reg.h"
#include "hal/gpio_types.h"
#include "ulp_riscv_register_ops.h"
#include "hal/rtc_io_ll.h"
typedef enum {
ULP_RISCV_GPIO_INTR_DISABLE = 0, /*!< Disable RTC GPIO interrupt */
@@ -33,10 +35,8 @@ typedef enum {
static inline void ulp_riscv_gpio_init(gpio_num_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32S2
SET_PERI_REG_MASK(SENS_SAR_IO_MUX_CONF_REG, SENS_IOMUX_CLK_GATE_EN_M);
#elif CONFIG_IDF_TARGET_ESP32S3
SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_IOMUX_CLK_EN_M);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
rtcio_ll_enable_io_clock(true);
#endif
SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_MUX_SEL);
REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_FUN_SEL, 0);