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Merge branch 'bugfix/lp_uart_baudrate_limitation' into 'master'

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fix(uart): LP UART does not have the pre-divider for its clock source

Closes IDFGH-14685 and IDF-12524

See merge request espressif/esp-idf!37250
This commit is contained in:
Song Ruo Jing
2025-03-07 16:05:54 +08:00
parent 96fdcec77b 1b09bb3037
commit 2fabe6ff9c
27 changed files with 284 additions and 241 deletions
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4
components/esp_driver_uart/include/driver/uart.h
View File

@@ -233,7 +233,7 @@ esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t* out_freq_hz);
* @param baudrate UART baud rate.
*
* @return
* - ESP_FAIL Parameter error
* - ESP_FAIL Parameter error, such as baud rate unachievable
* - ESP_OK Success
*/
esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baudrate);
@@ -463,7 +463,7 @@ esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num);
*
* @return
* - ESP_OK Success
* - ESP_FAIL Parameter error
* - ESP_FAIL Parameter error, such as baud rate unachievable
*/
esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_config);

14
components/esp_driver_uart/src/uart.c
View File

@@ -349,20 +349,20 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk);
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
bool success = false;
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_num < SOC_UART_HP_NUM) {
HP_UART_SRC_CLK_ATOMIC() {
uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
}
}
#if (SOC_UART_LP_NUM >= 1)
else {
lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, baud_rate, sclk_freq);
success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, baud_rate, sclk_freq);
}
#endif
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable");
return ESP_OK;
}
@@ -911,13 +911,14 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
uint32_t sclk_freq;
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
bool success = false;
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_init(&(uart_context[uart_num].hal), uart_num);
if (uart_num < SOC_UART_HP_NUM) {
esp_clk_tree_enable_src((soc_module_clk_t)uart_sclk_sel, true);
HP_UART_SRC_CLK_ATOMIC() {
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
}
}
#if (SOC_UART_LP_NUM >= 1)
@@ -925,7 +926,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
LP_UART_SRC_CLK_ATOMIC() {
lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)uart_sclk_sel);
}
lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq);
success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq);
}
#endif
uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity);
@@ -936,6 +937,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
uart_hal_txfifo_rst(&(uart_context[uart_num].hal));
ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable");
return ESP_OK;
}

2
components/esp_driver_uart/test_apps/uart/main/test_app_main.c
View File

@@ -10,7 +10,7 @@
#include "esp_heap_caps.h"
#include "esp_newlib.h"
#define TEST_MEMORY_LEAK_THRESHOLD (212)
#define TEST_MEMORY_LEAK_THRESHOLD (250)
void setUp(void)
{

2
components/esp_hw_support/port/esp32c5/io_mux.c
View File

@@ -47,6 +47,7 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
@@ -71,6 +72,7 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);

2
components/esp_hw_support/port/esp32c6/io_mux.c
View File

@@ -48,6 +48,7 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
@@ -72,6 +73,7 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);

2
components/esp_hw_support/port/esp32c61/io_mux.c
View File

@@ -46,6 +46,7 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
@@ -70,6 +71,7 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);

31
components/esp_hw_support/port/esp32h2/io_mux.c
View File

@@ -14,8 +14,11 @@
static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter)
static uint8_t s_rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM] = { 0 };
static uint32_t s_rtc_io_using_mask = 0;
static rtc_io_status_t s_rtc_io_status = {
.rtc_io_enabled_cnt = { 0 },
.rtc_io_using_mask = 0
};
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
{
@@ -40,20 +43,21 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
}
s_rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
}
}
RTCIO_RCC_ATOMIC() {
if (s_rtc_io_using_mask == 0) {
if (s_rtc_io_status.rtc_io_using_mask == 0) {
rtcio_ll_enable_io_clock(false);
} else {
rtcio_ll_enable_io_clock(true);
@@ -64,10 +68,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_using_mask &= ~(1ULL << gpio_num);
if (s_rtc_io_using_mask == 0) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
}

31
components/esp_hw_support/port/esp32h21/io_mux.c
View File

@@ -15,8 +15,11 @@
static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter)
static uint8_t s_rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM] = { 0 };
static uint32_t s_rtc_io_using_mask = 0;
static rtc_io_status_t s_rtc_io_status = {
.rtc_io_enabled_cnt = { 0 },
.rtc_io_using_mask = 0
};
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
{
@@ -41,20 +44,21 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
}
s_rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
}
}
RTCIO_RCC_ATOMIC() {
if (s_rtc_io_using_mask == 0) {
if (s_rtc_io_status.rtc_io_using_mask == 0) {
rtcio_ll_enable_io_clock(false);
} else {
rtcio_ll_enable_io_clock(true);
@@ -65,10 +69,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_using_mask &= ~(1ULL << gpio_num);
if (s_rtc_io_using_mask == 0) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
}

10
components/esp_hw_support/port/esp32p4/io_mux.c
View File

@@ -53,10 +53,7 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
if (gpio_num > MAX_RTC_GPIO_NUM) {
assert(false && "RTCIO number error");
return;
}
assert((gpio_num != GPIO_NUM_NC) && (gpio_num <= MAX_RTC_GPIO_NUM) && "RTCIO number error");
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
@@ -81,10 +78,7 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
if (gpio_num > MAX_RTC_GPIO_NUM) {
assert(false && "RTCIO number error");
return;
}
assert((gpio_num != GPIO_NUM_NC) && (gpio_num <= MAX_RTC_GPIO_NUM) && "RTCIO number error");
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);

2
components/esp_hw_support/port/esp32s2/io_mux.c
View File

@@ -31,6 +31,7 @@ static rtc_io_status_t s_rtc_io_status = {
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
@@ -55,6 +56,7 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);

2
components/esp_hw_support/port/esp32s3/io_mux.c
View File

@@ -31,6 +31,7 @@ static rtc_io_status_t s_rtc_io_status = {
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
@@ -55,6 +56,7 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
portENTER_CRITICAL(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);

24
components/hal/esp32/include/hal/uart_ll.h
View File

@@ -205,17 +205,23 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud-rate to be set. When the source clock is APB, the max baud-rate is `UART_LL_BITRATE_MAX`
* @param sclk_freq Frequency of the clock source of UART, in Hz.
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
uint32_t clk_div;
clk_div = ((sclk_freq) << 4) / baud;
// The baud-rate configuration register is divided into
// an integer part and a fractional part.
hw->clk_div.div_int = clk_div >> 4;
hw->clk_div.div_frag = clk_div & 0xf;
if (baud == 0) {
return false;
}
uint32_t clk_div = ((sclk_freq) << 4) / baud;
// The baud-rate configuration register is divided into an integer part and a fractional part.
uint32_t clkdiv_int = clk_div >> 4;
if (clkdiv_int > UART_CLKDIV_V) {
return false; // unachievable baud-rate
}
uint32_t clkdiv_frag = clk_div & 0xf;
hw->clk_div.div_int = clkdiv_int;
hw->clk_div.div_frag = clkdiv_frag;
return true;
}
/**

19
components/hal/esp32c2/include/hal/uart_ll.h
View File

@@ -209,23 +209,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0) abort();
if (sclk_div == 0 || sclk_div > (UART_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clk_div.div_int = clk_div >> 4;
hw->clk_div.div_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
return true;
}
/**

19
components/hal/esp32c3/include/hal/uart_ll.h
View File

@@ -213,23 +213,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0) abort();
if (sclk_div == 0 || sclk_div > (UART_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clk_div.div_int = clk_div >> 4;
hw->clk_div.div_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
return true;
}
/**

65
components/hal/esp32c5/include/hal/uart_ll.h
View File

@@ -153,23 +153,25 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if (sclk_div == 0) abort();
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
if (baud == 0) {
return false;
}
// No pre-divider for LP UART clock source on the target
uint32_t clk_div = (sclk_freq << 4) / baud;
// The baud rate configuration register is divided into an integer part and a fractional part.
uint32_t clkdiv_int = clk_div >> 4;
if (clkdiv_int > UART_CLKDIV_V) {
return false; // unachievable baud-rate
}
uint32_t clkdiv_frag = clk_div & 0xf;
hw->clkdiv_sync.clkdiv_int = clkdiv_int;
hw->clkdiv_sync.clkdiv_frag = clkdiv_frag;
uart_ll_update(hw);
return true;
}
/**
@@ -419,28 +421,33 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if ((hw) == &LP_UART) {
abort(); // need to call lp_uart_ll_set_baudrate()
}
if (sclk_div == 0) abort();
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
if ((hw) == &LP_UART) {
abort();
} else {
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
}
#undef DIV_UP
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
uart_ll_update(hw);
return true;
}
/**
@@ -457,7 +464,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
div_reg.val = hw->clkdiv_sync.val;
int sclk_div;
if ((hw) == &LP_UART) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
sclk_div = 1; // no pre-divider for LP UART clock source on the target
} else {
sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1;
}

65
components/hal/esp32c6/include/hal/uart_ll.h
View File

@@ -153,23 +153,25 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if (sclk_div == 0) abort();
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
if (baud == 0) {
return false;
}
// No pre-divider for LP UART clock source on the target
uint32_t clk_div = (sclk_freq << 4) / baud;
// The baud rate configuration register is divided into an integer part and a fractional part.
uint32_t clkdiv_int = clk_div >> 4;
if (clkdiv_int > UART_CLKDIV_V) {
return false; // unachievable baud-rate
}
uint32_t clkdiv_frag = clk_div & 0xf;
hw->clkdiv_sync.clkdiv_int = clkdiv_int;
hw->clkdiv_sync.clkdiv_frag = clkdiv_frag;
uart_ll_update(hw);
return true;
}
/**
@@ -400,28 +402,33 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if ((hw) == &LP_UART) {
abort(); // need to call lp_uart_ll_set_baudrate()
}
if (sclk_div == 0) abort();
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
if ((hw) == &LP_UART) {
abort();
} else {
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
}
#undef DIV_UP
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
uart_ll_update(hw);
return true;
}
/**
@@ -438,7 +445,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
div_reg.val = hw->clkdiv_sync.val;
int sclk_div;
if ((hw) == &LP_UART) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
sclk_div = 1; // no pre-divider for LP UART clock source on the target
} else {
sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1;
}

19
components/hal/esp32c61/include/hal/uart_ll.h
View File

@@ -259,24 +259,29 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0) abort();
if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
uart_ll_update(hw);
return true;
}
/**

19
components/hal/esp32h2/include/hal/uart_ll.h
View File

@@ -240,26 +240,29 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0) {
abort();
if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
uart_ll_update(hw);
return true;
}
/**

19
components/hal/esp32h21/include/hal/uart_ll.h
View File

@@ -240,26 +240,29 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0) {
abort();
if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clkdiv_sync.clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
uart_ll_update(hw);
return true;
}
/**

60
components/hal/esp32p4/include/hal/uart_ll.h
View File

@@ -17,6 +17,7 @@
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/lp_uart_reg.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lpperi_struct.h"
@@ -143,24 +144,25 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if (sclk_div == 0) abort();
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
//needs force u32 write
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
if (baud == 0) {
return false;
}
// No pre-divider for LP UART clock source on the target
uint32_t clk_div = (sclk_freq << 4) / baud;
// The baud rate configuration register is divided into an integer part and a fractional part.
uint32_t clkdiv_int = clk_div >> 4;
if (clkdiv_int > UART_CLKDIV_V) {
return false; // unachievable baud-rate
}
uint32_t clkdiv_frag = clk_div & 0xf;
hw->clkdiv_sync.clkdiv = clkdiv_int;
hw->clkdiv_sync.clkdiv_frag = clkdiv_frag;
uart_ll_update(hw);
return true;
}
/**
@@ -497,18 +499,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
if ((hw) == &LP_UART) {
abort(); // need to call lp_uart_ll_set_baudrate()
}
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if (sclk_div == 0) abort();
#undef DIV_UP
if (sclk_div == 0 || sclk_div > (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clkdiv_sync.clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
//needs force u32 write
@@ -525,12 +537,12 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
} else {
abort();
}
#undef DIV_UP
uart_ll_update(hw);
return true;
}
#if !BOOTLOADER_BUILD
//HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
#define uart_ll_set_baudrate(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_baudrate(__VA_ARGS__)
#define uart_ll_set_baudrate(...) uart_ll_set_baudrate(__VA_ARGS__); (void)__DECLARE_RCC_ATOMIC_ENV
#endif
/**
@@ -557,7 +569,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
} else if ((hw) == &UART4) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num) + 1;
} else if ((hw) == &LP_UART) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
sclk_div = 1; // no pre-divider for LP UART clock source on the target
}
return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * sclk_div);
}

24
components/hal/esp32s2/include/hal/uart_ll.h
View File

@@ -193,17 +193,23 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set. When the source clock is APB, the max baud rate is `UART_LL_BITRATE_MAX`
* @param sclk_freq Frequency of the clock source of UART, in Hz.
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
uint32_t clk_div;
clk_div = ((sclk_freq) << 4) / baud;
// The baud rate configuration register is divided into
// an integer part and a fractional part.
hw->clk_div.div_int = clk_div >> 4;
hw->clk_div.div_frag = clk_div & 0xf;
if (baud == 0) {
return false;
}
uint32_t clk_div = ((sclk_freq) << 4) / baud;
// The baud-rate configuration register is divided into an integer part and a fractional part.
uint32_t clkdiv_int = clk_div >> 4;
if (clkdiv_int > UART_CLKDIV_V) {
return false; // unachievable baud-rate
}
uint32_t clkdiv_frag = clk_div & 0xf;
hw->clk_div.div_int = clkdiv_int;
hw->clk_div.div_frag = clkdiv_frag;
return true;
}
/**

19
components/hal/esp32s3/include/hal/uart_ll.h
View File

@@ -216,23 +216,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0) abort();
if (sclk_div == 0 || sclk_div > (UART_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clkdiv.clkdiv = clk_div >> 4;
hw->clkdiv.clkdiv_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
return true;
}
/**

2
components/hal/include/hal/uart_hal.h
View File

@@ -36,7 +36,7 @@ typedef struct {
* @param baud_rate The baud-rate to be set
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
#define uart_hal_set_baudrate(hal, baud_rate, sclk_freq) uart_ll_set_baudrate((hal)->dev, baud_rate, sclk_freq)

29
components/soc/esp32c5/register/soc/uart_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -946,22 +946,7 @@ typedef union {
*/
typedef union {
struct {
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.'
* Only available to LP UART instance
*/
uint32_t sclk_div_b:6; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_a:6; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_num:8; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
uint32_t reserved_20:4;
uint32_t reserved_0:24;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Configures whether or not to enable UART TX clock.\\
* 0: Disable\\
@@ -1338,11 +1323,11 @@ typedef struct uart_dev_s {
volatile uart_mem_tx_status_reg_t mem_tx_status;
volatile uart_mem_rx_status_reg_t mem_rx_status;
volatile uart_fsm_status_reg_t fsm_status;
volatile uart_pospulse_reg_t pospulse;
volatile uart_negpulse_reg_t negpulse;
volatile uart_lowpulse_reg_t lowpulse;
volatile uart_highpulse_reg_t highpulse;
volatile uart_rxd_cnt_reg_t rxd_cnt;
volatile uart_pospulse_reg_t pospulse; /* LP_UART instance has this register reserved */
volatile uart_negpulse_reg_t negpulse; /* LP_UART instance has this register reserved */
volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */
volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */
volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */
volatile uart_clk_conf_reg_t clk_conf;
volatile uart_date_reg_t date;
volatile uart_afifo_status_reg_t afifo_status;

16
components/soc/esp32c6/register/soc/uart_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -880,19 +880,7 @@ typedef union {
*/
typedef union {
struct {
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
uint32_t sclk_div_b:6; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
uint32_t sclk_div_a:6; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
*/
uint32_t sclk_div_num:8; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
uint32_t reserved_20:4;
uint32_t reserved_0:24;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/

17
components/soc/esp32p4/register/soc/uart_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -880,20 +880,7 @@ typedef union {
*/
typedef union {
struct {
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
uint32_t sclk_div_b:6; //HP UART's sclk_div_b is in hp_sys_clkrst_struct.h
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
uint32_t sclk_div_a:6; //HP UART's sclk_div_a is in hp_sys_clkrst_struct.h
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
* It is only used by LP UART
*/
uint32_t sclk_div_num:8; //HP UART's sclk_div_num is in hp_sys_clkrst_struct.h
uint32_t reserved_20:4;
uint32_t reserved_0:24;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/

7
components/ulp/lp_core/lp_core_uart.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -62,7 +62,10 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
uart_hal_init(&hal, LP_UART_PORT_NUM);
/* Override protocol parameters from the configuration */
lp_uart_ll_set_baudrate(hal.dev, cfg->uart_proto_cfg.baud_rate, sclk_freq);
if (!lp_uart_ll_set_baudrate(hal.dev, cfg->uart_proto_cfg.baud_rate, sclk_freq)) {
/* Unachievable baud rate */
return ESP_FAIL;
}
uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity);
uart_hal_set_data_bit_num(&hal, cfg->uart_proto_cfg.data_bits);
uart_hal_set_stop_bits(&hal, cfg->uart_proto_cfg.stop_bits);