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Merge branch 'refactor/rng_ll_c5' into 'master'

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refactor(rng): refactor to use hal/ll apis for c5

Closes IDF-12534

See merge request espressif/esp-idf!37601
This commit is contained in:
Gao Xu
2025-03-27 15:31:01 +08:00
parent de44fbb92b 32b7347965
commit 3157356157
8 changed files with 159 additions and 96 deletions
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118
components/bootloader_support/src/bootloader_random_esp32c5.c
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@@ -1,108 +1,60 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/lpperi_reg.h"
#include "soc/regi2c_saradc.h"
#include "esp_log.h"
static const uint32_t SAR2_CHANNEL = 9;
static const uint32_t SAR1_CHANNEL = 7;
static const uint32_t PATTERN_BIT_WIDTH = 6;
static const uint32_t SAR1_ATTEN = 3;
static const uint32_t SAR2_ATTEN = 3;
#include "hal/regi2c_ctrl_ll.h"
#include "hal/adc_ll.h"
#include "hal/adc_types.h"
void bootloader_random_enable(void)
{
// pull SAR ADC out of reset
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
// enable SAR ADC APB clock
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
// pull APB register out of reset
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
// enable ADC_CTRL_CLK (SAR ADC function clock)
REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0); // 0: XTAL; 1: 80M(from bbpll); 2. FOSC
// set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
// some magic register poke from the digital team
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
adc_ll_reset_register();
adc_ll_enable_bus_clock(true);
adc_ll_enable_func_clock(true);
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
adc_ll_digi_controller_clk_div(0, 0, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
// Config ADC circuit (Analog part) with I2C (HOST ID 0X69) and choose internal voltage as sampling source
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 1);
adc_ll_regi2c_init();
adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66);
adc_digi_pattern_config_t pattern_config = {};
pattern_config.unit = ADC_UNIT_1;
pattern_config.atten = ADC_ATTEN_DB_12;
pattern_config.channel = ADC_CHANNEL_7; //Use reserved channel to get internal voltage
adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
pattern_config.unit = ADC_UNIT_2;
pattern_config.atten = ADC_ATTEN_DB_12;
pattern_config.channel = ADC_CHANNEL_1; //Use reserved ADC2 and reserved channel to get internal voltage
adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
// create patterns and set them in pattern table
uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN; // we want channel 7 with max attenuation
uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 2);
// set pattern length (APB_SARADC_SARADC_SAR_PATT_LEN counts from 0)
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1);
adc_ll_digi_set_clk_div(15);
adc_ll_digi_set_trigger_interval(200);
adc_ll_digi_trigger_enable();
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
// set timer expiry (timer is ADC_CTRL_CLK)
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
// enable timer
REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
CLEAR_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
}
void bootloader_random_disable(void)
{
// disable timer
REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
// Write reset value of this register
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
// Revert ADC I2C configuration and initial voltage source setting
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0);
adc_ll_digi_trigger_disable();
adc_ll_digi_reset_pattern_table();
adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
adc_ll_regi2c_adc_deinit();
// disable analog i2c master clock
ANALOG_CLOCK_DISABLE();
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
// Set PCR_SARADC_CONF_REG to initial state
REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
adc_ll_digi_controller_clk_div(4, 0, 0);
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
}

4
components/bootloader_support/src/bootloader_random_esp32c6.c
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@@ -30,11 +30,11 @@ void bootloader_random_enable(void)
adc_digi_pattern_config_t pattern_config = {};
pattern_config.unit = ADC_UNIT_2;
pattern_config.atten = ADC_ATTEN_DB_2_5;
pattern_config.channel = ADC_CHANNEL_1;
pattern_config.channel = ADC_CHANNEL_1; //Use reserved channel to get internal voltage
adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
pattern_config.unit = ADC_UNIT_2;
pattern_config.atten = ADC_ATTEN_DB_2_5;
pattern_config.channel = ADC_CHANNEL_1;
pattern_config.channel = ADC_CHANNEL_1; //Use reserved ADC2 and reserved channel to get internal voltage
adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, 2);

4
components/bootloader_support/src/bootloader_random_esp32c61.c
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@@ -30,11 +30,11 @@ void bootloader_random_enable(void)
adc_digi_pattern_config_t pattern_config = {};
pattern_config.unit = ADC_UNIT_1;
pattern_config.atten = ADC_ATTEN_DB_12;
pattern_config.channel = ADC_CHANNEL_7;
pattern_config.channel = ADC_CHANNEL_7; //Use reserved channel to get internal voltage
adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
pattern_config.unit = ADC_UNIT_2;
pattern_config.atten = ADC_ATTEN_DB_12;
pattern_config.channel = ADC_CHANNEL_1;
pattern_config.channel = ADC_CHANNEL_1; //Use reserved ADC2 and reserved channel to get internal voltage
adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 2);

2
components/bootloader_support/src/bootloader_random_esp32h2.c
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@@ -31,7 +31,7 @@ void bootloader_random_enable(void)
adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
pattern_config.unit = ADC_UNIT_2;
pattern_config.atten = ADC_ATTEN_DB_2_5;
pattern_config.channel = ADC_CHANNEL_1;
pattern_config.channel = ADC_CHANNEL_1; //Use reserved ADC2 and reserved channel to get internal voltage
adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);

4
components/esp_hw_support/port/esp32c5/pmu_init.c
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@@ -209,8 +209,8 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
void pmu_init(void)
{
/* Peripheral reg i2c power up */
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
pmu_hp_system_init_default(PMU_instance());
pmu_lp_system_init_default(PMU_instance());

85
components/hal/esp32c5/include/hal/adc_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -224,6 +224,15 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
}
}
/**
* Rest pattern table to default value
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = 0xffffff;
APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = 0xffffff;
}
/**
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
*
@@ -846,8 +855,78 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
uint8_t msb = param >> 8;
uint8_t lsb = param & 0xFF;
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
} else {
//C5 doesn't support ADC2, here is for backward compatibility for RNG
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
}
}
/**
* Set the SAR DTEST param
*
* @param param DTEST value
*/
__attribute__((always_inline))
static inline void adc_ll_set_dtest_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, param);
}
/**
* Set the SAR ENT param
*
* @param param ENT value
*/
__attribute__((always_inline))
static inline void adc_ll_set_ent_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, param);
}
/**
* Enable/disable the calibration voltage reference for ADC unit.
*
* @param adc_n ADC index number.
* @param en true to enable, false to disable
*/
__attribute__((always_inline))
static inline void adc_ll_enable_calibration_ref(adc_unit_t adc_n, bool en)
{
//C5 doesn't support ADC2, here is for backward compatibility for RNG
if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, en);
} else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, en);
}
}
/**
* Init regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_init(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(1);
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
adc_ll_enable_calibration_ref(ADC_UNIT_1, true);
adc_ll_enable_calibration_ref(ADC_UNIT_2, true);
}
/**
* Deinit regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_adc_deinit(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(0);
adc_ll_enable_calibration_ref(ADC_UNIT_1, false);
adc_ll_enable_calibration_ref(ADC_UNIT_2, false);
}
#ifdef __cplusplus

34
components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,6 +13,7 @@
#include "modem/modem_lpcon_struct.h"
#include "modem/modem_syscon_struct.h"
#include "soc/i2c_ana_mst_reg.h"
#include "soc/pmu_reg.h"
#ifdef __cplusplus
extern "C" {
@@ -111,6 +112,37 @@ static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
// TODO: IDF-8727
}
/**
* @brief Enable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
{
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Disable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
{
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Enter / Exit reset state
*
* @param enter True to reset mode, false to normal working mode
*/
static inline void regi2c_ctrl_ll_reset(bool enter)
{
if (enter) {
// Reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} else {
// Normal working mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
}
#ifdef __cplusplus
}
#endif

4
components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h
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@@ -133,9 +133,9 @@ static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
*
* @param enter True to reset mode, false to normal working mode
*/
static inline void regi2c_ctrl_ll_reset(bool reset_on)
static inline void regi2c_ctrl_ll_reset(bool enter)
{
if (reset_on) {
if (enter) {
// Reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} else {