forked from espressif/esp-idf
Merge branch 'doc/flash_enc_update_v4.2' into 'release/v4.2'
docs: update flash encryption docs for S2 See merge request espressif/esp-idf!12324
This commit is contained in:
Angus Gratton
145
docs/en/security/esp32_log.inc
Normal file
145
docs/en/security/esp32_log.inc
Normal file
@@ -0,0 +1,145 @@
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.. first_boot_enc
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||||
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.. code-block:: none
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||||
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--- idf_monitor on /dev/cu.SLAB_USBtoUART 115200 ---
|
||||
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
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||||
ets Jun 8 2016 00:22:57
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|
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rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
|
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configsip: 0, SPIWP:0xee
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clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
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||||
mode:DIO, clock div:2
|
||||
load:0x3fff0018,len:4
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||||
load:0x3fff001c,len:8452
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load:0x40078000,len:13608
|
||||
load:0x40080400,len:6664
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||||
entry 0x40080764
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||||
I (28) boot: ESP-IDF v4.0-dev-850-gc4447462d-dirty 2nd stage bootloader
|
||||
I (29) boot: compile time 15:37:14
|
||||
I (30) boot: Enabling RNG early entropy source...
|
||||
I (35) boot: SPI Speed : 40MHz
|
||||
I (39) boot: SPI Mode : DIO
|
||||
I (43) boot: SPI Flash Size : 4MB
|
||||
I (47) boot: Partition Table:
|
||||
I (51) boot: ## Label Usage Type ST Offset Length
|
||||
I (58) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (66) boot: 1 phy_init RF data 01 01 00010000 00001000
|
||||
I (73) boot: 2 factory factory app 00 00 00020000 00100000
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||||
I (81) boot: End of partition table
|
||||
I (85) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (105) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844) load
|
||||
I (109) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024) load
|
||||
0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
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||||
|
||||
I (114) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720) load
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||||
I (132) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
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0x400d0018: _flash_cache_start at ??:?
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||||
|
||||
I (159) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012) load
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0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
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I (168) boot: Loaded app from partition at offset 0x20000
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I (168) boot: Checking flash encryption...
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I (168) flash_encrypt: Generating new flash encryption key...
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I (187) flash_encrypt: Read & write protecting new key...
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I (187) flash_encrypt: Setting CRYPT_CONFIG efuse to 0xF
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W (188) flash_encrypt: Not disabling UART bootloader encryption
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I (195) flash_encrypt: Disable UART bootloader decryption...
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||||
I (201) flash_encrypt: Disable UART bootloader MMU cache...
|
||||
I (208) flash_encrypt: Disable JTAG...
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||||
I (212) flash_encrypt: Disable ROM BASIC interpreter fallback...
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||||
I (219) esp_image: segment 0: paddr=0x00001020 vaddr=0x3fff0018 size=0x00004 ( 4)
|
||||
I (227) esp_image: segment 1: paddr=0x0000102c vaddr=0x3fff001c size=0x02104 ( 8452)
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||||
I (239) esp_image: segment 2: paddr=0x00003138 vaddr=0x40078000 size=0x03528 ( 13608)
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||||
I (249) esp_image: segment 3: paddr=0x00006668 vaddr=0x40080400 size=0x01a08 ( 6664)
|
||||
I (657) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (669) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844)
|
||||
I (672) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024)
|
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0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
|
||||
|
||||
I (676) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720)
|
||||
I (692) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
|
||||
0x400d0018: _flash_cache_start at ??:?
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||||
|
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I (719) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012)
|
||||
0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
|
||||
|
||||
I (722) flash_encrypt: Encrypting partition 2 at offset 0x20000...
|
||||
I (13229) flash_encrypt: Flash encryption completed
|
||||
I (13229) boot: Resetting with flash encryption enabled...
|
||||
|
||||
------
|
||||
|
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.. already_en_enc
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
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configsip: 0, SPIWP:0xee
|
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clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
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mode:DIO, clock div:2
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load:0x3fff0018,len:4
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load:0x3fff001c,len:8452
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load:0x40078000,len:13652
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ho 0 tail 12 room 4
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load:0x40080400,len:6664
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entry 0x40080764
|
||||
I (30) boot: ESP-IDF v4.0-dev-850-gc4447462d-dirty 2nd stage bootloader
|
||||
I (30) boot: compile time 16:32:53
|
||||
I (31) boot: Enabling RNG early entropy source...
|
||||
I (37) boot: SPI Speed : 40MHz
|
||||
I (41) boot: SPI Mode : DIO
|
||||
I (45) boot: SPI Flash Size : 4MB
|
||||
I (49) boot: Partition Table:
|
||||
I (52) boot: ## Label Usage Type ST Offset Length
|
||||
I (60) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (67) boot: 1 phy_init RF data 01 01 00010000 00001000
|
||||
I (75) boot: 2 factory factory app 00 00 00020000 00100000
|
||||
I (82) boot: End of partition table
|
||||
I (86) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (107) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844) load
|
||||
I (111) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024) load
|
||||
0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
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||||
|
||||
I (116) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720) load
|
||||
I (134) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
|
||||
0x400d0018: _flash_cache_start at ??:?
|
||||
|
||||
I (162) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012) load
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||||
0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
|
||||
|
||||
I (171) boot: Loaded app from partition at offset 0x20000
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||||
I (171) boot: Checking flash encryption...
|
||||
I (171) flash_encrypt: flash encryption is enabled (3 plaintext flashes left)
|
||||
I (178) boot: Disabling RNG early entropy source...
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||||
I (184) cpu_start: Pro cpu up.
|
||||
I (188) cpu_start: Application information:
|
||||
I (193) cpu_start: Project name: flash-encryption
|
||||
I (198) cpu_start: App version: v4.0-dev-850-gc4447462d-dirty
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||||
I (205) cpu_start: Compile time: Jun 17 2019 16:32:52
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||||
I (211) cpu_start: ELF file SHA256: 8770c886bdf561a7...
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I (217) cpu_start: ESP-IDF: v4.0-dev-850-gc4447462d-dirty
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||||
I (224) cpu_start: Starting app cpu, entry point is 0x40080e4c
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0x40080e4c: call_start_cpu1 at esp-idf/esp-idf/components/{IDF_TARGET_PATH_NAME}/cpu_start.c:265
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I (0) cpu_start: App cpu up.
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I (235) heap_init: Initializing. RAM available for dynamic allocation:
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I (241) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
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||||
I (247) heap_init: At 3FFB2EC8 len 0002D138 (180 KiB): DRAM
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||||
I (254) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
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||||
I (260) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
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I (266) heap_init: At 40087FF4 len 0001800C (96 KiB): IRAM
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I (273) cpu_start: Pro cpu start user code
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I (291) cpu_start: Starting scheduler on PRO CPU.
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I (0) cpu_start: Starting scheduler on APP CPU.
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Sample program to check Flash Encryption
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This is ESP32 chip with 2 CPU cores, WiFi/BT/BLE, silicon revision 1, 4MB external flash
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Flash encryption feature is enabled
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Flash encryption mode is DEVELOPMENT
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Flash in encrypted mode with flash_crypt_cnt = 1
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Halting...
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------
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155
docs/en/security/esp32s2_log.inc
Normal file
155
docs/en/security/esp32s2_log.inc
Normal file
@@ -0,0 +1,155 @@
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.. first_boot_enc
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.. code-block:: none
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ESP-ROM:esp32s2-rc4-20191025
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Build:Oct 25 2019
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rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
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SPIWP:0xee
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mode:DIO, clock div:1
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load:0x3ffe6260,len:0x78
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load:0x3ffe62d8,len:0x231c
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load:0x4004c000,len:0x9d8
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load:0x40050000,len:0x3cf8
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entry 0x4004c1ec
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||||
I (48) boot: ESP-IDF qa-test-v4.3-20201113-777-gd8e1 2nd stage bootloader
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||||
I (48) boot: compile time 11:24:04
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||||
I (48) boot: chip revision: 0
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||||
I (52) boot.esp32s2: SPI Speed : 80MHz
|
||||
I (57) boot.esp32s2: SPI Mode : DIO
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||||
I (62) boot.esp32s2: SPI Flash Size : 2MB
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||||
I (66) boot: Enabling RNG early entropy source...
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||||
I (72) boot: Partition Table:
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||||
I (75) boot: ## Label Usage Type ST Offset Length
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||||
I (83) boot: 0 nvs WiFi data 01 02 0000a000 00006000
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||||
I (90) boot: 1 storage Unknown data 01 ff 00010000 00001000
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||||
I (98) boot: 2 factory factory app 00 00 00020000 00100000
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||||
I (105) boot: End of partition table
|
||||
I (109) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f000020 size=0x0618c ( 24972) map
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||||
I (124) esp_image: segment 1: paddr=0x000261b4 vaddr=0x3ffbcae0 size=0x02624 ( 9764) load
|
||||
I (129) esp_image: segment 2: paddr=0x000287e0 vaddr=0x40022000 size=0x00404 ( 1028) load
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||||
0x40022000: _WindowOverflow4 at /home/marius/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730
|
||||
|
||||
I (136) esp_image: segment 3: paddr=0x00028bec vaddr=0x40022404 size=0x0742c ( 29740) load
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||||
0x40022404: _coredump_iram_end at ??:?
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||||
|
||||
I (153) esp_image: segment 4: paddr=0x00030020 vaddr=0x40080020 size=0x1457c ( 83324) map
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0x40080020: _stext at ??:?
|
||||
|
||||
I (171) esp_image: segment 5: paddr=0x000445a4 vaddr=0x40029830 size=0x032ac ( 12972) load
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0x40029830: gpspi_flash_ll_set_miso_bitlen at /home/marius/esp-idf/examples/security/flash_encryption/build/../../../../components/hal/esp32s2/include/hal/gpspi_flash_ll.h:261
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||||
(inlined by) spi_flash_hal_gpspi_common_command at /home/marius/esp-idf/components/hal/spi_flash_hal_common.inc:161
|
||||
|
||||
I (181) boot: Loaded app from partition at offset 0x20000
|
||||
I (181) boot: Checking flash encryption...
|
||||
I (181) efuse: Batch mode of writing fields is enabled
|
||||
I (188) flash_encrypt: Generating new flash encryption key...
|
||||
W (199) flash_encrypt: Not disabling UART bootloader encryption
|
||||
I (201) flash_encrypt: Disable UART bootloader cache...
|
||||
I (207) flash_encrypt: Disable JTAG...
|
||||
I (212) efuse: Batch mode of writing fields is disabled
|
||||
I (217) esp_image: segment 0: paddr=0x00001020 vaddr=0x3ffe6260 size=0x00078 ( 120)
|
||||
I (226) esp_image: segment 1: paddr=0x000010a0 vaddr=0x3ffe62d8 size=0x0231c ( 8988)
|
||||
I (236) esp_image: segment 2: paddr=0x000033c4 vaddr=0x4004c000 size=0x009d8 ( 2520)
|
||||
I (243) esp_image: segment 3: paddr=0x00003da4 vaddr=0x40050000 size=0x03cf8 ( 15608)
|
||||
I (651) flash_encrypt: bootloader encrypted successfully
|
||||
I (704) flash_encrypt: partition table encrypted and loaded successfully
|
||||
I (704) flash_encrypt: Encrypting partition 1 at offset 0x10000 (length 0x1000)...
|
||||
I (765) flash_encrypt: Done encrypting
|
||||
I (766) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f000020 size=0x0618c ( 24972) map
|
||||
I (773) esp_image: segment 1: paddr=0x000261b4 vaddr=0x3ffbcae0 size=0x02624 ( 9764)
|
||||
I (778) esp_image: segment 2: paddr=0x000287e0 vaddr=0x40022000 size=0x00404 ( 1028)
|
||||
0x40022000: _WindowOverflow4 at /home/marius/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730
|
||||
|
||||
I (785) esp_image: segment 3: paddr=0x00028bec vaddr=0x40022404 size=0x0742c ( 29740)
|
||||
0x40022404: _coredump_iram_end at ??:?
|
||||
|
||||
I (799) esp_image: segment 4: paddr=0x00030020 vaddr=0x40080020 size=0x1457c ( 83324) map
|
||||
0x40080020: _stext at ??:?
|
||||
|
||||
I (820) esp_image: segment 5: paddr=0x000445a4 vaddr=0x40029830 size=0x032ac ( 12972)
|
||||
0x40029830: gpspi_flash_ll_set_miso_bitlen at /home/marius/esp-idf/examples/security/flash_encryption/build/../../../../components/hal/esp32s2/include/hal/gpspi_flash_ll.h:261
|
||||
(inlined by) spi_flash_hal_gpspi_common_command at /home/marius/esp-idf/components/hal/spi_flash_hal_common.inc:161
|
||||
|
||||
I (823) flash_encrypt: Encrypting partition 2 at offset 0x20000 (length 0x100000)...
|
||||
I (13869) flash_encrypt: Done encrypting
|
||||
I (13870) flash_encrypt: Flash encryption completed
|
||||
I (13870) boot: Resetting with flash encryption enabled...
|
||||
|
||||
|
||||
------
|
||||
|
||||
.. already_en_enc
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
ESP-ROM:esp32s2-rc4-20191025
|
||||
Build:Oct 25 2019
|
||||
rst:0x3 (RTC_SW_SYS_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
|
||||
Saved PC:0x40051242
|
||||
SPIWP:0xee
|
||||
mode:DIO, clock div:1
|
||||
load:0x3ffe6260,len:0x78
|
||||
load:0x3ffe62d8,len:0x231c
|
||||
load:0x4004c000,len:0x9d8
|
||||
load:0x40050000,len:0x3cf8
|
||||
entry 0x4004c1ec
|
||||
I (56) boot: ESP-IDF qa-test-v4.3-20201113-777-gd8e1 2nd stage bootloader
|
||||
I (56) boot: compile time 11:24:04
|
||||
I (56) boot: chip revision: 0
|
||||
I (60) boot.esp32s2: SPI Speed : 80MHz
|
||||
I (65) boot.esp32s2: SPI Mode : DIO
|
||||
I (69) boot.esp32s2: SPI Flash Size : 2MB
|
||||
I (74) boot: Enabling RNG early entropy source...
|
||||
I (80) boot: Partition Table:
|
||||
I (83) boot: ## Label Usage Type ST Offset Length
|
||||
I (90) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (98) boot: 1 storage Unknown data 01 ff 00010000 00001000
|
||||
I (105) boot: 2 factory factory app 00 00 00020000 00100000
|
||||
I (113) boot: End of partition table
|
||||
I (117) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f000020 size=0x0618c ( 24972) map
|
||||
I (132) esp_image: segment 1: paddr=0x000261b4 vaddr=0x3ffbcae0 size=0x02624 ( 9764) load
|
||||
I (137) esp_image: segment 2: paddr=0x000287e0 vaddr=0x40022000 size=0x00404 ( 1028) load
|
||||
0x40022000: _WindowOverflow4 at /home/marius/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730
|
||||
|
||||
I (144) esp_image: segment 3: paddr=0x00028bec vaddr=0x40022404 size=0x0742c ( 29740) load
|
||||
0x40022404: _coredump_iram_end at ??:?
|
||||
|
||||
I (161) esp_image: segment 4: paddr=0x00030020 vaddr=0x40080020 size=0x1457c ( 83324) map
|
||||
0x40080020: _stext at ??:?
|
||||
|
||||
I (180) esp_image: segment 5: paddr=0x000445a4 vaddr=0x40029830 size=0x032ac ( 12972) load
|
||||
0x40029830: gpspi_flash_ll_set_miso_bitlen at /home/marius/esp-idf/examples/security/flash_encryption/build/../../../../components/hal/esp32s2/include/hal/gpspi_flash_ll.h:261
|
||||
(inlined by) spi_flash_hal_gpspi_common_command at /home/marius/esp-idf/components/hal/spi_flash_hal_common.inc:161
|
||||
|
||||
I (190) boot: Loaded app from partition at offset 0x20000
|
||||
I (191) boot: Checking flash encryption...
|
||||
I (191) flash_encrypt: flash encryption is enabled (1 plaintext flashes left)
|
||||
I (199) boot: Disabling RNG early entropy source...
|
||||
I (216) cache: Instruction cache : size 8KB, 4Ways, cache line size 32Byte
|
||||
I (216) cpu_start: Pro cpu up.
|
||||
I (268) cpu_start: Pro cpu start user code
|
||||
I (268) cpu_start: cpu freq: 160000000
|
||||
I (268) cpu_start: Application information:
|
||||
I (271) cpu_start: Project name: flash_encryption
|
||||
I (277) cpu_start: App version: qa-test-v4.3-20201113-777-gd8e1
|
||||
I (284) cpu_start: Compile time: Dec 21 2020 11:24:00
|
||||
I (290) cpu_start: ELF file SHA256: 30fd1b899312fef7...
|
||||
I (296) cpu_start: ESP-IDF: qa-test-v4.3-20201113-777-gd8e1
|
||||
I (303) heap_init: Initializing. RAM available for dynamic allocation:
|
||||
I (310) heap_init: At 3FF9E000 len 00002000 (8 KiB): RTCRAM
|
||||
I (316) heap_init: At 3FFBF898 len 0003C768 (241 KiB): DRAM
|
||||
I (323) heap_init: At 3FFFC000 len 00003A10 (14 KiB): DRAM
|
||||
W (329) flash_encrypt: Flash encryption mode is DEVELOPMENT (not secure)
|
||||
I (336) spi_flash: detected chip: generic
|
||||
I (341) spi_flash: flash io: dio
|
||||
W (345) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
|
||||
I (358) cpu_start: Starting scheduler on PRO CPU.
|
||||
|
||||
Example to check Flash Encryption status
|
||||
This is esp32s2 chip with 1 CPU core(s), WiFi, silicon revision 0, 2MB external flash
|
||||
FLASH_CRYPT_CNT eFuse value is 1
|
||||
Flash encryption feature is enabled in DEVELOPMENT mode
|
||||
|
||||
------
|
||||
@@ -34,13 +34,14 @@ Other types of data can be encrypted conditionally:
|
||||
|
||||
Enabling flash encryption limits the options for further updates of {IDF_TARGET_NAME}. Before using this feature, read the document and make sure to understand the implications.
|
||||
|
||||
{IDF_TARGET_CRYPT_CNT:default="SPI_BOOT_CRYPT_CNT",esp32="FLASH_CRYPT_CNT"}
|
||||
|
||||
.. _flash-encryption-efuse:
|
||||
|
||||
Relevant eFuses
|
||||
---------------
|
||||
|
||||
The flash encryption operation is controlled by various eFuses available on {IDF_TARGET_NAME}. The list of eFuses and their descriptions is given in the table below.
|
||||
The flash encryption operation is controlled by various eFuses available on {IDF_TARGET_NAME}. The list of eFuses and their descriptions is given in the table below. The names in eFuse column are also used by espefuse.py tool. For usage in the eFuse API, modify the name by adding ``ESP_EFUSE_``, for example: esp_efuse_read_field_bit(ESP_EFUSE_**DISABLE_DL_ENCRYPT**).
|
||||
|
||||
.. Comment: As text in cells of list-table header rows does not wrap, it is necessary to make 0 header rows and apply bold typeface to the first row. Otherwise, the table goes beyond the html page limits on the right.
|
||||
|
||||
@@ -53,14 +54,14 @@ The flash encryption operation is controlled by various eFuses available on {IDF
|
||||
* - **eFuse**
|
||||
- **Description**
|
||||
- **Bit Depth**
|
||||
- **Locking for Reading/Writing Available**
|
||||
- **R/W Access Control Available**
|
||||
- **Default Value**
|
||||
* - ``CODING_SCHEME``
|
||||
- Controls actual number of BLOCK1 bits used to derive final 256-bit AES key. Possible values: ``0`` for 256 bits, ``1`` for 192 bits, ``2`` for 128 bits. Final AES key is derived based on the ``FLASH_CRYPT_CONFIG`` value.
|
||||
- Controls actual number of block1 bits used to derive final 256-bit AES key. Possible values: ``0`` for 256 bits, ``1`` for 192 bits, ``2`` for 128 bits. Final AES key is derived based on the ``FLASH_CRYPT_CONFIG`` value.
|
||||
- 2
|
||||
- Yes
|
||||
- 0
|
||||
* - ``BLOCK1``
|
||||
* - ``flash_encryption`` (block1)
|
||||
- AES key storage.
|
||||
- 256
|
||||
- Yes
|
||||
@@ -70,24 +71,22 @@ The flash encryption operation is controlled by various eFuses available on {IDF
|
||||
- 4
|
||||
- Yes
|
||||
- 0xF
|
||||
* - ``download_dis_encrypt``
|
||||
* - ``DISABLE_DL_ENCRYPT``
|
||||
- If set, disables flash encryption operation while running in Firmware Download mode.
|
||||
- 1
|
||||
- Yes
|
||||
- 0
|
||||
* - ``download_dis_decrypt``
|
||||
* - ``DISABLE_DL_DECRYPT``
|
||||
- If set, disables flash decryption while running in UART Firmware Download mode.
|
||||
- 1
|
||||
- Yes
|
||||
- 0
|
||||
* - ``FLASH_CRYPT_CNT``
|
||||
* - ``{IDF_TARGET_CRYPT_CNT}``
|
||||
- Enables/disables encryption at boot time. If even number of bits set (0, 2, 4, 6) - encrypt flash at boot time. If odd number of bits set (1, 3, 5, 7) - do not encrypt flash at boot time.
|
||||
- 7
|
||||
- Yes
|
||||
- 0
|
||||
|
||||
Read and write access to eFuse bits is controlled by appropriate fields in the registers ``efuse_wr_disable`` and ``efuse_rd_disable``. For more information on {IDF_TARGET_NAME} eFuses, see :doc:`eFuse manager <../api-reference/system/efuse>`.
|
||||
|
||||
|
||||
.. only:: esp32s2
|
||||
|
||||
@@ -98,54 +97,53 @@ The flash encryption operation is controlled by various eFuses available on {IDF
|
||||
* - **eFuse**
|
||||
- **Description**
|
||||
- **Bit Depth**
|
||||
- **Locking for Reading/Writing Available**
|
||||
- **R/W Access Control Available**
|
||||
- **Default Value**
|
||||
* - ``KEYN``
|
||||
* - ``BLOCK_KEYN``
|
||||
- AES key storage. N is between 0 and 5.
|
||||
- 256
|
||||
- Yes
|
||||
- x
|
||||
* - ``EFUSE_KEY_PURPOSE_N``
|
||||
- Controls the purpose of eFuse block ``KEYN``, where N is between 0 and 5. Possible values: ``2`` for ``XTS_AES_256_KEY_1`` , ``3`` for ``XTS_AES_256_KEY_2``, and ``4`` for ``XTS_AES_128_KEY``. Final AES key is derived based on the value of one or two of these purpose eFuses. For a detailed description of the possible combinations see `{IDF_TARGET_NAME} Technical Reference Manual <{IDF_TARGET_TRM_EN_URL}>`_, chapter Flash Encryption.
|
||||
* - ``KEY_PURPOSE_N``
|
||||
- Controls the purpose of eFuse block ``BLOCK_KEYN``, where N is between 0 and 5. Possible values: ``2`` for ``XTS_AES_256_KEY_1`` , ``3`` for ``XTS_AES_256_KEY_2``, and ``4`` for ``XTS_AES_128_KEY``. Final AES key is derived based on the value of one or two of these purpose eFuses. For a detailed description of the possible combinations, see *{IDF_TARGET_NAME} Technical Reference Manual* > *External Memory Encryption and Decryption (XTS_AES)* [`PDF <{IDF_TARGET_TRM_EN_URL}#extmemencr>`__].
|
||||
- 4
|
||||
- Yes
|
||||
- 0
|
||||
* - ``EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT``
|
||||
* - ``DIS_DOWNLOAD_MANUAL_ENCRYPT``
|
||||
- If set, disables flash encryption when in download bootmodes.
|
||||
- 1
|
||||
- Yes
|
||||
- 0
|
||||
* - ``EFUSE_SPI_BOOT_CRYPT_CNT``
|
||||
* - ``{IDF_TARGET_CRYPT_CNT}``
|
||||
- Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled if 1 or 3 bits are set in the eFuse, disabled otherwise.
|
||||
- 3
|
||||
- Yes
|
||||
- 0
|
||||
|
||||
Read and write access to eFuse bits is controlled by appropriate fields in the registers ``EFUSE_WR_DIS`` and ``EFUSE_RD_DIS``. For more information on {IDF_TARGET_NAME} eFuses, see :doc:`eFuse manager <../api-reference/system/efuse>`.
|
||||
|
||||
Read and write access to eFuse bits is controlled by appropriate fields in the registers ``WR_DIS`` and ``RD_DIS``. For more information on {IDF_TARGET_NAME} eFuses, see :doc:`eFuse manager <../api-reference/system/efuse>`. To change protection bits of eFuse field using espefuse.py, use these two commands: read_protect_efuse and write_protect_efuse. Example ``espefuse.py write_protect_efuse DISABLE_DL_ENCRYPT``.
|
||||
|
||||
|
||||
Flash Encryption Process
|
||||
------------------------
|
||||
|
||||
{IDF_TARGET_CRYPT_CNT:default="EFUSE_SPI_BOOT_CRYPT_CNT",esp32="FLASH_CRYPT_CNT",esp32s2="EFUSE_SPI_BOOT_CRYPT_CNT"}
|
||||
|
||||
Assuming that the eFuse values are in their default states and the firmware bootloader is compiled to support flash encryption, the flash encryption process executes as shown below:
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The ROM bootloader loads the firmware bootloader.
|
||||
|
||||
2. Firmware bootloader reads the ``FLASH_CRYPT_CNT`` eFuse value (``0b00000000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. It also sets the ``FLASH_CRYPT_CONFIG`` eFuse to 0xF. For more information on the flash encryption block, see `{IDF_TARGET_NAME} Technical Reference Manual <{IDF_TARGET_TRM_EN_URL}>`_.
|
||||
2. Firmware bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b0000000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. It also sets the ``FLASH_CRYPT_CONFIG`` eFuse to 0xF. For more information on the flash encryption block, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* > *Flash Encryption Block* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
|
||||
|
||||
3. Flash encryption block generates an AES-256 bit key and writes it into the BLOCK1 eFuse. This operation is done entirely by hardware, and the key cannot be accessed via software.
|
||||
3. Firmware bootloader uses RNG (random) module to generate an AES-256 bit key and then writes it into the ``flash_encryption`` eFuse. The key cannot be accessed via software as the write and read protection bits for the ``flash_encryption`` eFuse are set. The flash encryption operations happen entirely by hardware, and the key cannot be accessed via software.
|
||||
|
||||
4. Flash encryption block encrypts the flash contents - partitions encrypted by default and the ones marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
|
||||
4. Flash encryption block encrypts the flash contents - the firmware bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
|
||||
|
||||
5. Firmware bootloader sets the first available bit in ``FLASH_CRYPT_CNT`` (0b00000001) to mark the flash contents as encrypted. Odd number of bits is set.
|
||||
5. Firmware bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b0000001) to mark the flash contents as encrypted. Odd number of bits is set.
|
||||
|
||||
6. For :ref:`flash-enc-development-mode`, the firmware bootloader sets only the eFuse bits ``download_dis_decrypt`` and ``download_dis_cache`` to allow the UART bootloader to re-flash encrypted binaries. Also, the ``FLASH_CRYPT_CNT`` eFuse bits are NOT write-protected.
|
||||
6. For :ref:`flash-enc-development-mode`, the firmware bootloader sets only the eFuse bits ``DISABLE_DL_DECRYPT`` and ``DISABLE_DL_CACHE`` to allow the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected.
|
||||
|
||||
7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets the eFuse bits ``download_dis_encrypt``, ``download_dis_decrypt``, and ``download_dis_cache`` to 1 to prevent the UART bootloader from decrypting the flash contents. It also write-protects the ``FLASH_CRYPT_CNT`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
|
||||
7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets the eFuse bits ``DISABLE_DL_ENCRYPT``, ``DISABLE_DL_DECRYPT``, and ``DISABLE_DL_CACHE`` to 1 to prevent the UART bootloader from decrypting the flash contents. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
|
||||
|
||||
8. The device is then rebooted to start executing the encrypted image. The firmware bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
|
||||
|
||||
@@ -153,17 +151,17 @@ Assuming that the eFuse values are in their default states and the firmware boot
|
||||
|
||||
1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The ROM bootloader loads the firmware bootloader.
|
||||
|
||||
2. Firmware bootloader reads the ``EFUSE_SPI_BOOT_CRYPT_CNT`` eFuse value (``0b00000000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. For more information on the flash encryption block, see `{IDF_TARGET_NAME} Technical Reference Manual <{IDF_TARGET_TRM_EN_URL}>`_.
|
||||
2. Firmware bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. For more information on the flash encryption block, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* > *Auto Encryption Block* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
|
||||
|
||||
3. Flash encryption block generates an 256 bit or 512 bit key, depending on the value of :ref:`Size of generated AES-XTS key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`, and writes it into respectively one or two `KEYN` eFuses. The software also updates the ``EFUSE_KEY_PURPOSE_N`` for the blocks where the keys where stored. This operation is done entirely by hardware, and the key cannot be accessed via software.
|
||||
3. Firmware bootloader uses RNG (random) module to generate an 256 bit or 512 bit key, depending on the value of :ref:`Size of generated AES-XTS key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`, and then writes it into respectively one or two `BLOCK_KEYN` eFuses. The software also updates the ``KEY_PURPOSE_N`` for the blocks where the keys were stored. The key cannot be accessed via software as the write and read protection bits for one or two `BLOCK_KEYN` eFuses are set. ``KEY_PURPOSE_N`` field is write-protected as well. The flash encryption operations happen entirely by hardware, and the key cannot be accessed via software.
|
||||
|
||||
4. Flash encryption block encrypts the flash contents - partitions encrypted by default and the ones marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
|
||||
4. Flash encryption block encrypts the flash contents - the firmware bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
|
||||
|
||||
5. Firmware bootloader sets the first available bit in ``EFUSE_SPI_BOOT_CRYPT_CNT`` (0b00000001) to mark the flash contents as encrypted. Odd number of bits is set.
|
||||
5. Firmware bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b001) to mark the flash contents as encrypted. Odd number of bits is set.
|
||||
|
||||
6. For :ref:`flash-enc-development-mode`, the firmware bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``EFUSE_SPI_BOOT_CRYPT_CNT`` eFuse bits are NOT write-protected.
|
||||
6. For :ref:`flash-enc-development-mode`, the firmware bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the firmware bootloader by default sets the eFuse bits ``DIS_BOOT_REMAP``, ``DIS_DOWNLOAD_ICACHE``, ``DIS_DOWNLOAD_DCACHE``, ``HARD_DIS_JTAG`` and ``DIS_LEGACY_SPI_BOOT``.
|
||||
|
||||
7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets the eFuse bits ``EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT``, ``EFUSE_DIS_BOOT_REMAP``, ``EFUSE_DIS_DOWNLOAD_ICACHE`` and ``EFUSE_DIS_DOWNLOAD_DCACHE``. It also write-protects the ``EFUSE_SPI_BOOT_CRYPT_CNT`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
|
||||
7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets all the eFuse bits set under development mode as well as ``DIS_DOWNLOAD_MANUAL_ENCRYPT``. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
|
||||
|
||||
8. The device is then rebooted to start executing the encrypted image. The firmware bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
|
||||
|
||||
@@ -172,8 +170,6 @@ During the development stage, there is a frequent need to program different plai
|
||||
|
||||
Hence, two different flash encryption configurations were created: for development and for production. For details on these configurations, see Section `Flash Encryption Configuration`_.
|
||||
|
||||
.. _{IDF_TARGET_NAME} Technical Reference Manual: {IDF_TARGET_TRM_EN_URL}
|
||||
|
||||
|
||||
Flash Encryption Configuration
|
||||
------------------------------
|
||||
@@ -216,158 +212,32 @@ To test flash encryption process, take the following steps:
|
||||
- :ref:`Select the appropriate bootloader log verbosity <CONFIG_BOOTLOADER_LOG_LEVEL>`
|
||||
- Save the configuration and exit.
|
||||
|
||||
.. only:: esp32
|
||||
Enabling flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`.
|
||||
|
||||
Enabling flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`
|
||||
|
||||
3. Run the command given below to build and flash the complete image.
|
||||
3. Run the command given below to build and flash the complete images.
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
idf.py flash monitor
|
||||
|
||||
The image will include the firmware bootloader, partition table, application, and other partitions marked by the user as ``encrypted``. These binaries will be written to flash memory unencrypted. Once the flashing is complete, your device will reset. On the next boot, the firmware bootloader encrypts the flash application partition and then resets. After that, the sample application is decrypted at runtime and executed.
|
||||
.. note::
|
||||
|
||||
This command does not include any user files which should be written to the partitions on the flash memory. Please write them manually before running this command otherwise the files should be encrypted separately before writing.
|
||||
|
||||
This command will write to flash memory unencrypted images: the firmware bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the firmware bootloader encrypts: the firmware bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
|
||||
|
||||
A sample output of the first {IDF_TARGET_NAME} boot after enabling flash encryption is given below:
|
||||
|
||||
.. code-block:: bash
|
||||
.. include:: {IDF_TARGET_PATH_NAME}_log.inc
|
||||
:start-after: first_boot_enc
|
||||
:end-before: ------
|
||||
|
||||
--- idf_monitor on /dev/cu.SLAB_USBtoUART 115200 ---
|
||||
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
|
||||
ets Jun 8 2016 00:22:57
|
||||
|
||||
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
|
||||
configsip: 0, SPIWP:0xee
|
||||
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
|
||||
mode:DIO, clock div:2
|
||||
load:0x3fff0018,len:4
|
||||
load:0x3fff001c,len:8452
|
||||
load:0x40078000,len:13608
|
||||
load:0x40080400,len:6664
|
||||
entry 0x40080764
|
||||
I (28) boot: ESP-IDF v4.0-dev-850-gc4447462d-dirty 2nd stage bootloader
|
||||
I (29) boot: compile time 15:37:14
|
||||
I (30) boot: Enabling RNG early entropy source...
|
||||
I (35) boot: SPI Speed : 40MHz
|
||||
I (39) boot: SPI Mode : DIO
|
||||
I (43) boot: SPI Flash Size : 4MB
|
||||
I (47) boot: Partition Table:
|
||||
I (51) boot: ## Label Usage Type ST Offset Length
|
||||
I (58) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (66) boot: 1 phy_init RF data 01 01 00010000 00001000
|
||||
I (73) boot: 2 factory factory app 00 00 00020000 00100000
|
||||
I (81) boot: End of partition table
|
||||
I (85) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (105) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844) load
|
||||
I (109) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024) load
|
||||
0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
|
||||
|
||||
I (114) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720) load
|
||||
I (132) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
|
||||
0x400d0018: _flash_cache_start at ??:?
|
||||
|
||||
I (159) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012) load
|
||||
0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
|
||||
|
||||
I (168) boot: Loaded app from partition at offset 0x20000
|
||||
I (168) boot: Checking flash encryption...
|
||||
I (168) flash_encrypt: Generating new flash encryption key...
|
||||
I (187) flash_encrypt: Read & write protecting new key...
|
||||
I (187) flash_encrypt: Setting CRYPT_CONFIG efuse to 0xF
|
||||
W (188) flash_encrypt: Not disabling UART bootloader encryption
|
||||
I (195) flash_encrypt: Disable UART bootloader decryption...
|
||||
I (201) flash_encrypt: Disable UART bootloader MMU cache...
|
||||
I (208) flash_encrypt: Disable JTAG...
|
||||
I (212) flash_encrypt: Disable ROM BASIC interpreter fallback...
|
||||
I (219) esp_image: segment 0: paddr=0x00001020 vaddr=0x3fff0018 size=0x00004 ( 4)
|
||||
I (227) esp_image: segment 1: paddr=0x0000102c vaddr=0x3fff001c size=0x02104 ( 8452)
|
||||
I (239) esp_image: segment 2: paddr=0x00003138 vaddr=0x40078000 size=0x03528 ( 13608)
|
||||
I (249) esp_image: segment 3: paddr=0x00006668 vaddr=0x40080400 size=0x01a08 ( 6664)
|
||||
I (657) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (669) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844)
|
||||
I (672) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024)
|
||||
0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
|
||||
|
||||
I (676) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720)
|
||||
I (692) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
|
||||
0x400d0018: _flash_cache_start at ??:?
|
||||
|
||||
I (719) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012)
|
||||
0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
|
||||
|
||||
I (722) flash_encrypt: Encrypting partition 2 at offset 0x20000...
|
||||
I (13229) flash_encrypt: Flash encryption completed
|
||||
I (13229) boot: Resetting with flash encryption enabled...
|
||||
|
||||
A sample output of subsequent {IDF_TARGET_NAME} boots just mentions that flash encryption is already enabled:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
|
||||
configsip: 0, SPIWP:0xee
|
||||
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
|
||||
mode:DIO, clock div:2
|
||||
load:0x3fff0018,len:4
|
||||
load:0x3fff001c,len:8452
|
||||
load:0x40078000,len:13652
|
||||
ho 0 tail 12 room 4
|
||||
load:0x40080400,len:6664
|
||||
entry 0x40080764
|
||||
I (30) boot: ESP-IDF v4.0-dev-850-gc4447462d-dirty 2nd stage bootloader
|
||||
I (30) boot: compile time 16:32:53
|
||||
I (31) boot: Enabling RNG early entropy source...
|
||||
I (37) boot: SPI Speed : 40MHz
|
||||
I (41) boot: SPI Mode : DIO
|
||||
I (45) boot: SPI Flash Size : 4MB
|
||||
I (49) boot: Partition Table:
|
||||
I (52) boot: ## Label Usage Type ST Offset Length
|
||||
I (60) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (67) boot: 1 phy_init RF data 01 01 00010000 00001000
|
||||
I (75) boot: 2 factory factory app 00 00 00020000 00100000
|
||||
I (82) boot: End of partition table
|
||||
I (86) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (107) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844) load
|
||||
I (111) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024) load
|
||||
0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
|
||||
|
||||
I (116) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720) load
|
||||
I (134) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
|
||||
0x400d0018: _flash_cache_start at ??:?
|
||||
|
||||
I (162) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012) load
|
||||
0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
|
||||
|
||||
I (171) boot: Loaded app from partition at offset 0x20000
|
||||
I (171) boot: Checking flash encryption...
|
||||
I (171) flash_encrypt: flash encryption is enabled (3 plaintext flashes left)
|
||||
I (178) boot: Disabling RNG early entropy source...
|
||||
I (184) cpu_start: Pro cpu up.
|
||||
I (188) cpu_start: Application information:
|
||||
I (193) cpu_start: Project name: flash-encryption
|
||||
I (198) cpu_start: App version: v4.0-dev-850-gc4447462d-dirty
|
||||
I (205) cpu_start: Compile time: Jun 17 2019 16:32:52
|
||||
I (211) cpu_start: ELF file SHA256: 8770c886bdf561a7...
|
||||
I (217) cpu_start: ESP-IDF: v4.0-dev-850-gc4447462d-dirty
|
||||
I (224) cpu_start: Starting app cpu, entry point is 0x40080e4c
|
||||
0x40080e4c: call_start_cpu1 at esp-idf/esp-idf/components/{IDF_TARGET_PATH_NAME}/cpu_start.c:265
|
||||
|
||||
I (0) cpu_start: App cpu up.
|
||||
I (235) heap_init: Initializing. RAM available for dynamic allocation:
|
||||
I (241) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
|
||||
I (247) heap_init: At 3FFB2EC8 len 0002D138 (180 KiB): DRAM
|
||||
I (254) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
|
||||
I (260) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
|
||||
I (266) heap_init: At 40087FF4 len 0001800C (96 KiB): IRAM
|
||||
I (273) cpu_start: Pro cpu start user code
|
||||
I (291) cpu_start: Starting scheduler on PRO CPU.
|
||||
I (0) cpu_start: Starting scheduler on APP CPU.
|
||||
|
||||
Sample program to check Flash Encryption
|
||||
This is ESP32 chip with 2 CPU cores, WiFi/BT/BLE, silicon revision 1, 4MB external flash
|
||||
Flash encryption feature is enabled
|
||||
Flash encryption mode is DEVELOPMENT
|
||||
Flash in encrypted mode with flash_crypt_cnt = 1
|
||||
Halting...
|
||||
.. include:: {IDF_TARGET_PATH_NAME}_log.inc
|
||||
:start-after: already_en_enc
|
||||
:end-before: ------
|
||||
|
||||
At this stage, if you need to update and re-flash binaries, see :ref:`encrypt-partitions`.
|
||||
|
||||
@@ -391,15 +261,64 @@ To use a host generated key, take the following steps:
|
||||
|
||||
2. Generate a random key by running:
|
||||
|
||||
.. code-block:: bash
|
||||
.. only:: esp32s2
|
||||
|
||||
espsecure.py generate_flash_encryption_key my_flash_encryption_key.bin
|
||||
If :ref:`Size of generated AES-XTS key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>` is AES-256 (512-bit key) need to use the `XTS_AES_256_KEY_1` and `XTS_AES_256_KEY_2` purposes. The espsecure does not support 512-bit key, but it is possible to workaround:
|
||||
|
||||
3. **Before the first encrypted boot**, burn the key into your device's BLOCK1 eFuse using the command below. This action can be done **only once**.
|
||||
.. code-block:: bash
|
||||
|
||||
espsecure.py generate_flash_encryption_key my_flash_encryption_key1.bin
|
||||
|
||||
espsecure.py generate_flash_encryption_key my_flash_encryption_key2.bin
|
||||
|
||||
# To use encrypt_flash_data with XTS_AES_256 requires combining the two binary files to one 64 byte file
|
||||
cat my_flash_encryption_key1.bin my_flash_encryption_key2.bin > my_flash_encryption_key.bin
|
||||
|
||||
If :ref:`Size of generated AES-XTS key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>` is AES-128 (256-bit key) need to use the `XTS_AES_128_KEY` purpose.
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
espsecure.py generate_flash_encryption_key my_flash_encryption_key.bin
|
||||
|
||||
|
||||
.. only:: not esp32s2
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
espsecure.py generate_flash_encryption_key my_flash_encryption_key.bin
|
||||
|
||||
|
||||
3. **Before the first encrypted boot**, burn the key into your device's eFuse using the command below. This action can be done **only once**.
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
espefuse.py --port PORT burn_key flash_encryption my_flash_encryption_key.bin
|
||||
|
||||
.. only:: esp32s2
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
espefuse.py --port PORT burn_key BLOCK my_flash_encryption_key.bin KEYPURPOSE
|
||||
|
||||
where `BLOCK` is a free keyblock between `BLOCK_KEY0` and `BLOCK_KEY5`. And `KEYPURPOSE` is either `AES_256_KEY_1`, `XTS_AES_256_KEY_2`, `XTS_AES_128_KEY`. See `{IDF_TARGET_NAME} Technical Reference Manual <{IDF_TARGET_TRM_EN_URL}>`_ for a description of the key purposes.
|
||||
|
||||
AES-128 (256-bit key) - `XTS_AES_128_KEY`:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
espefuse.py --port PORT burn_key flash_encryption my_flash_encryption_key.bin
|
||||
espefuse.py --port PORT burn_key BLOCK my_flash_encryption_key.bin XTS_AES_128_KEY
|
||||
|
||||
AES-256 (512-bit key) - `XTS_AES_256_KEY_1` and `XTS_AES_256_KEY_2`. It is not fully supported yet in espefuse.py and espsecure.py. Need to do the following steps:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
espefuse.py --port PORT burn_key BLOCK my_flash_encryption_key1.bin XTS_AES_256_KEY_1
|
||||
|
||||
espefuse.py --port PORT burn_key BLOCK+1 my_flash_encryption_key2.bin XTS_AES_256_KEY_2
|
||||
|
||||
where `BLOCK+1` is a block adjacent to `BLOCK` (best practice is to keep them adjacent).
|
||||
|
||||
If the key is not burned and the device is started after enabling flash encryption, the {IDF_TARGET_NAME} will generate a random key that software cannot access or modify.
|
||||
|
||||
@@ -410,17 +329,19 @@ To use a host generated key, take the following steps:
|
||||
- :ref:`Select the appropriate bootloader log verbosity <CONFIG_BOOTLOADER_LOG_LEVEL>`
|
||||
- Save the configuration and exit.
|
||||
|
||||
.. only:: esp32
|
||||
Enabling flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`.
|
||||
|
||||
Enabling flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`
|
||||
|
||||
5. Run the command given below to build and flash the complete.
|
||||
5. Run the command given below to build and flash the complete images.
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
idf.py flash monitor
|
||||
|
||||
The image will include the firmware bootloader, partition table, application, and other partitions marked by the user as ``encrypted``. These binaries will be written to flash memory unencrypted. Once the flashing is complete, your device will reset. On the next boot, the firmware bootloader encrypts the flash application partition and then resets. After that, the sample application is decrypted at runtime and executed.
|
||||
.. note::
|
||||
|
||||
This command does not include any user files which should be written to the partitions on the flash memory. Please write them manually before running this command otherwise the files should be encrypted separately before writing.
|
||||
|
||||
This command will write to flash memory unencrypted images: the firmware bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the firmware bootloader encrypts: the firmware bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
|
||||
|
||||
At this stage, if you need to update and re-flash binaries, see :ref:`encrypt-partitions`.
|
||||
|
||||
@@ -461,23 +382,26 @@ To use this mode, take the following steps:
|
||||
.. list::
|
||||
|
||||
- :ref:`Enable flash encryption on boot <CONFIG_SECURE_FLASH_ENC_ENABLED>`
|
||||
:esp32: - :ref:`Select Release mode <CONFIG_SECURE_FLASH_ENCRYPTION_MODE>` (Note that once Release mode is selected, the ``download_dis_encrypt`` and ``download_dis_decrypt`` eFuse bits will be burned to disable UART bootloader access to flash contents)
|
||||
:esp32s2: - :ref:`Select Release mode <CONFIG_SECURE_FLASH_ENCRYPTION_MODE>` (Note that once Release mode is selected, the ``EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT`` eFuse bit will be burned to disable UART bootloader access to flash contents)
|
||||
:esp32: - :ref:`Select Release mode <CONFIG_SECURE_FLASH_ENCRYPTION_MODE>` (Note that once Release mode is selected, the ``DISABLE_DL_ENCRYPT`` and ``DISABLE_DL_DECRYPT`` eFuse bits will be burned to disable UART bootloader access to flash contents)
|
||||
:not esp32: - :ref:`Select Release mode <CONFIG_SECURE_FLASH_ENCRYPTION_MODE>` (Note that once Release mode is selected, the ``EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT`` eFuse bit will be burned to disable UART bootloader access to flash contents)
|
||||
:esp32s2: - Set :ref:`Size of generated AES-XTS key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`
|
||||
- :ref:`Select the appropriate bootloader log verbosity <CONFIG_BOOTLOADER_LOG_LEVEL>`
|
||||
- Save the configuration and exit.
|
||||
|
||||
.. only:: esp32
|
||||
Enabling flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`.
|
||||
|
||||
Enabling flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`
|
||||
|
||||
3. Run the command given below to build and flash the complete image.
|
||||
3. Run the command given below to build and flash the complete images.
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
idf.py flash monitor
|
||||
|
||||
The image will include the firmware bootloader, partition table, application, and other partitions marked by the user as ``encrypted``. These binaries will be written to flash memory unencrypted. Once the flashing is complete, your device will reset. On the next boot, the firmware bootloader encrypts the flash application partition and then resets. After that, the sample application is decrypted at runtime and executed.
|
||||
|
||||
.. note::
|
||||
|
||||
This command does not include any user files which should be written to the partitions on the flash memory. Please write them manually before running this command otherwise the files should be encrypted separately before writing.
|
||||
|
||||
This command will write to flash memory unencrypted images: the firmware bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the firmware bootloader encrypts: the firmware bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
|
||||
|
||||
Once the flash encryption is enabled in Release mode, the bootloader will write-protect the ``{IDF_TARGET_CRYPT_CNT}`` eFuse.
|
||||
|
||||
@@ -495,9 +419,8 @@ When using Flash Encryption in production:
|
||||
|
||||
- Do not reuse the same flash encryption key between multiple devices. This means that an attacker who copies encrypted data from one device cannot transfer it to a second device.
|
||||
:esp32: - When using ESP32 V3, if the UART ROM Download Mode is not needed for a production device then it should be disabled to provide an extra level of protection. Do this by calling :cpp:func:`esp_efuse_disable_rom_download_mode` during application startup. Alternatively, configure the project :ref:`CONFIG_ESP32_REV_MIN` level to 3 (targeting ESP32 V3 only) and enable :ref:`CONFIG_SECURE_DISABLE_ROM_DL_MODE`. The ability to disable ROM Download Mode is not available on earlier ESP32 versions.
|
||||
:esp32s2: - The UART ROM Download Mode should be disabled entirely if it is not needed, or permanently set to "Secure Download Mode" otherwise. Secure Download Mode permanently limits the available commands to basic flash read and write only. The default behaviour is to set Secure Download Mode on first boot in Release mode. To disable Download Mode entirely, enable configuration option :ref:`CONFIG_SECURE_DISABLE_ROM_DL_MODE` or call :cpp:func:`esp_efuse_disable_rom_download_mode` at runtime.
|
||||
:esp32: - Enable :doc:`Secure Boot <secure-boot-v2>` as an extra layer of protection, and to prevent an attacker from selectively corrupting any part of the flash before boot.
|
||||
:esp32s2: - Enable Secure Boot as an extra layer of protection, and to prevent an attacker from selectively corrupting any part of the flash before boot.
|
||||
:not esp32: - The UART ROM Download Mode should be disabled entirely if it is not needed, or permanently set to "Secure Download Mode" otherwise. Secure Download Mode permanently limits the available commands to basic flash read and write only. The default behaviour is to set Secure Download Mode on first boot in Release mode. To disable Download Mode entirely, enable configuration option :ref:`CONFIG_SECURE_DISABLE_ROM_DL_MODE` or call :cpp:func:`esp_efuse_disable_rom_download_mode` at runtime.
|
||||
- Enable :doc:`Secure Boot <secure-boot-v2>` as an extra layer of protection, and to prevent an attacker from selectively corrupting any part of the flash before boot.
|
||||
|
||||
Possible Failures
|
||||
-----------------
|
||||
@@ -506,6 +429,8 @@ Once flash encryption is enabled, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value wil
|
||||
|
||||
1. If the bootloader partition is re-flashed with a **plaintext firmware bootloader image**, the ROM bootloader will fail to load the firmware bootloader resulting in the following failure:
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
|
||||
@@ -533,6 +458,23 @@ Once flash encryption is enabled, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value wil
|
||||
ets_main.c 371
|
||||
ets Jun 8 2016 00:22:57
|
||||
|
||||
.. only:: not esp32
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
|
||||
invalid header: 0xb414f76b
|
||||
invalid header: 0xb414f76b
|
||||
invalid header: 0xb414f76b
|
||||
invalid header: 0xb414f76b
|
||||
invalid header: 0xb414f76b
|
||||
invalid header: 0xb414f76b
|
||||
invalid header: 0xb414f76b
|
||||
|
||||
.. note::
|
||||
|
||||
The value of invalid header will be different for every application.
|
||||
|
||||
.. note::
|
||||
|
||||
This error also appears if the flash contents are erased or corrupted.
|
||||
@@ -690,7 +632,7 @@ For general information about ESP-IDF OTA updates, please refer to :doc:`OTA <..
|
||||
Disabling Flash Encryption
|
||||
--------------------------
|
||||
|
||||
If flash encryption was enabled accidentally, flashing of plaintext data will soft-brick the {IDF_TARGET_NAME}. The device will reboot continuously, printing the error ``flash read err, 1000``.
|
||||
If flash encryption was enabled accidentally, flashing of plaintext data will soft-brick the {IDF_TARGET_NAME}. The device will reboot continuously, printing the error ``flash read err, 1000`` or ``invalid header: 0xXXXXXX``.
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
@@ -717,11 +659,11 @@ Key Points About Flash Encryption
|
||||
|
||||
.. list::
|
||||
|
||||
:esp32: - Flash memory contents are encrypted using AES-256. The flash encryption key is stored in the ``BLOCK1`` eFuse internal to the chip and, by default, is protected from software access.
|
||||
:esp32: - Flash memory contents is encrypted using AES-256. The flash encryption key is stored in the ``flash_encryption`` eFuse internal to the chip and, by default, is protected from software access.
|
||||
|
||||
:esp32: - The flash encryption algorithm is AES-256, where the key is "tweaked" with the offset address of each 32 byte block of flash. This means that every 32-byte block (two consecutive 16 byte AES blocks) is encrypted with a unique key derived from the flash encryption key.
|
||||
|
||||
:esp32s2: - Flash memory contents are encrypted using XTS-AES-128 or XTS-AES-256. The flash encryption key is 256 bits and 512 bits respectively and stored one or two ``KEYN`` eFuses internal to the chip and, by default, is protected from software access.
|
||||
:esp32s2: - Flash memory contents is encrypted using XTS-AES-128 or XTS-AES-256. The flash encryption key is 256 bits and 512 bits respectively and stored one or two ``BLOCK_KEYN`` eFuses internal to the chip and, by default, is protected from software access.
|
||||
|
||||
- Flash access is transparent via the flash cache mapping feature of {IDF_TARGET_NAME} - any flash regions which are mapped to the address space will be transparently decrypted when read.
|
||||
|
||||
@@ -731,9 +673,7 @@ Key Points About Flash Encryption
|
||||
|
||||
- If secure boot is enabled, re-flashing the bootloader of an encrypted device requires a "Re-flashable" secure boot digest (see :ref:`flash-encryption-and-secure-boot`).
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
The firmware bootloader app binary ``bootloader.bin`` might become too large if both secure boot and flash encryption are enabled. See :ref:`secure-boot-bootloader-size`.
|
||||
Enabling flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`.
|
||||
|
||||
.. important::
|
||||
|
||||
@@ -752,8 +692,7 @@ Flash encryption protects firmware against unauthorised readout and modification
|
||||
- Not all data is stored encrypted. If storing data on flash, check if the method you are using (library, API, etc.) supports flash encryption.
|
||||
- Flash encryption does not prevent an attacker from understanding the high-level layout of the flash. This is because the same AES key is used for every pair of adjacent 16 byte AES blocks. When these adjacent 16 byte blocks contain identical content (such as empty or padding areas), these blocks will encrypt to produce matching pairs of encrypted blocks. This may allow an attacker to make high-level comparisons between encrypted devices (i.e. to tell if two devices are probably running the same firmware version).
|
||||
:esp32: - For the same reason, an attacker can always tell when a pair of adjacent 16 byte blocks (32 byte aligned) contain two identical 16 byte sequences. Keep this in mind if storing sensitive data on the flash, design your flash storage so this doesn't happen (using a counter byte or some other non-identical value every 16 bytes is sufficient). :ref:`NVS Encryption <nvs_encryption>` deals with this and is suitable for many uses.
|
||||
:esp32: - Flash encryption alone may not prevent an attacker from modifying the firmware of the device. To prevent unauthorised firmware from running on the device, use flash encryption in combination with :doc:`Secure Boot <secure-boot-v2>`.
|
||||
:esp32s2: - Flash encryption alone may not prevent an attacker from modifying the firmware of the device. To prevent unauthorised firmware from running on the device, use flash encryption in combination with Secure Boot.
|
||||
- Flash encryption alone may not prevent an attacker from modifying the firmware of the device. To prevent unauthorised firmware from running on the device, use flash encryption in combination with :doc:`Secure Boot <secure-boot-v2>`.
|
||||
|
||||
.. _flash-encryption-and-secure-boot:
|
||||
|
||||
@@ -813,12 +752,17 @@ On the first boot, the flash encryption process burns by default the following e
|
||||
.. only:: esp32
|
||||
|
||||
- ``DISABLE_DL_ENCRYPT`` which disables flash encryption operation when running in UART bootloader boot mode.
|
||||
- ``DISABLE_DL_DECRYPT`` which disables transparent flash decryption when running in UART bootloader mode, even if the eFuse ``FLASH_CRYPT_CNT`` is set to enable it in normal operation.
|
||||
- ``DISABLE_DL_DECRYPT`` which disables transparent flash decryption when running in UART bootloader mode, even if the eFuse ``{IDF_TARGET_CRYPT_CNT}`` is set to enable it in normal operation.
|
||||
- ``DISABLE_DL_CACHE`` which disables the entire MMU flash cache when running in UART bootloader mode.
|
||||
|
||||
.. only:: esp32s2
|
||||
|
||||
- ``EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT`` flash encryption operation when running in UART bootloader boot mode.
|
||||
.. list::
|
||||
|
||||
- ``DIS_DOWNLOAD_MANUAL_ENCRYPT`` which disables flash encryption operation when running in UART bootloader boot mode.
|
||||
:esp32s2: - ``DIS_DOWNLOAD_ICACHE`` and ``DIS_DOWNLOAD_DCACHE`` which disables the entire MMU flash cache when running in UART bootloader mode.
|
||||
:esp32s2: - ``HARD_DIS_JTAG`` which disables JTAG.
|
||||
- ``DIS_LEGACY_SPI_BOOT`` which disables Legacy SPI boot mode
|
||||
|
||||
However, before the first boot you can choose to keep any of these features enabled by burning only selected eFuses and write-protect the rest of eFuses with unset value 0. For example:
|
||||
|
||||
@@ -829,6 +773,13 @@ However, before the first boot you can choose to keep any of these features enab
|
||||
espefuse.py --port PORT burn_efuse DISABLE_DL_DECRYPT
|
||||
espefuse.py --port PORT write_protect_efuse DISABLE_DL_ENCRYPT
|
||||
|
||||
.. only:: esp32s2
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
espefuse.py --port PORT burn_efuse DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
espefuse.py --port PORT write_protect_efuse DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
|
||||
.. note::
|
||||
|
||||
Set all appropriate bits before write-protecting!
|
||||
@@ -882,16 +833,16 @@ The following sections provide some reference information about the operation of
|
||||
|
||||
- AES-256 operates on 16-byte blocks of data. The flash encryption engine encrypts and decrypts data in 32-byte blocks - two AES blocks in series.
|
||||
|
||||
- The main flash encryption key is stored in the ``BLOCK1`` eFuse and, by default, is protected from further writes or software readout.
|
||||
- The main flash encryption key is stored in the ``flash_encryption`` eFuse and, by default, is protected from further writes or software readout.
|
||||
|
||||
- AES-256 key size is 256 bits (32 bytes) read from the ``BLOCK1`` eFuse. The hardware AES engine uses the key in reversed byte order as compared to the storage order in ``BLOCK1``.
|
||||
- AES-256 key size is 256 bits (32 bytes) read from the ``flash_encryption`` eFuse. The hardware AES engine uses the key in reversed byte order as compared to the storage order in ``flash_encryption``.
|
||||
|
||||
- If the ``CODING_SCHEME`` eFuse is set to ``0`` (default, "None" Coding Scheme) then the eFuse key block is 256 bits and the key is stored as-is (in reversed byte order).
|
||||
- If the ``CODING_SCHEME`` eFuse is set to ``1`` (3/4 Encoding) then the eFuse key block is 192 bits (in reversed byte order), so overall entropy is reduced. The hardware flash encryption still operates on a 256-bit key, after being read (and un-reversed), the key is extended as ``key = key[0:255] + key[64:127]``.
|
||||
|
||||
- AES algorithm is used inverted in flash encryption, so the flash encryption "encrypt" operation is AES decrypt and the "decrypt" operation is AES encrypt. This is for performance reasons and does not alter the effeciency of the algorithm.
|
||||
|
||||
- Each 32-byte block (two adjacent 16-byte AES blocks) is encrypted with a unique key. The key is derived from the main flash encryption key in ``BLOCK1``, XORed with the offset of this block in the flash (a "key tweak").
|
||||
- Each 32-byte block (two adjacent 16-byte AES blocks) is encrypted with a unique key. The key is derived from the main flash encryption key in ``flash_encryption``, XORed with the offset of this block in the flash (a "key tweak").
|
||||
|
||||
- The specific tweak depends on the ``FLASH_CRYPT_CONFIG`` eFuse setting. This is a 4-bit eFuse where each bit enables XORing of a particular range of the key bits:
|
||||
|
||||
@@ -918,6 +869,6 @@ The following sections provide some reference information about the operation of
|
||||
|
||||
- XTS-AES is a block chiper mode specifically designed for disc encryption and addresses the weaknesses other potential modes (e.g. AES-CTR) have for this use case. A detailed description of the XTS-AES algorithm can be found in `IEEE Std 1619-2007 <https://ieeexplore.ieee.org/document/4493450>`_.
|
||||
|
||||
- The flash encryption key is stored in one or two ``KEYN`` eFuses and, by default, is protected from further writes or software readout.
|
||||
- The flash encryption key is stored in one or two ``BLOCK_KEYN`` eFuses and, by default, is protected from further writes or software readout.
|
||||
|
||||
- To see the full flash encryption algorithm implemented in Python, refer to the `_flash_encryption_operation()` function in the ``espsecure.py`` source code.
|
||||
|
||||
25
docs/en/security/secure-boot-bootloader-size.rst
Normal file
25
docs/en/security/secure-boot-bootloader-size.rst
Normal file
@@ -0,0 +1,25 @@
|
||||
:orphan:
|
||||
|
||||
.. _secure-boot-bootloader-size:
|
||||
|
||||
Bootloader Size (with enabled secure features)
|
||||
==============================================
|
||||
|
||||
|
||||
{IDF_TARGET_MAX_BOOTLOADER_SIZE:default = "64KB (0x10000 bytes)", esp32 = "48KB (0xC000 bytes)"}
|
||||
{IDF_TARGET_MAX_PARTITION_TABLE_OFFSET:default = "0x12000", esp32 = "0xE000"}
|
||||
.. Above is calculated as 0x1000 at start of flash + IDF_TARGET_MAX_BOOTLOADER_SIZE + 0x1000 signature sector
|
||||
|
||||
When secure boot is enabled the bootloader app binary ``bootloader.bin`` may exceed the default bootloader size limit. This is especially likely if flash encryption is enabled as well. The default size limit is 0x7000 (28672) bytes (partition table offset 0x8000 - bootloader offset 0x1000).
|
||||
|
||||
If the bootloader becomes too large, the {IDF_TARGET_NAME} will fail to boot - errors will be logged about either invalid partition table or invalid bootloader checksum.
|
||||
|
||||
When Secure Boot V2 is enabled, there is also an absolute binary size limit of {IDF_TARGET_MAX_BOOTLOADER_SIZE} (excluding the 4KB signature), because the bootloader is first loaded into a fixed size buffer for verification.
|
||||
|
||||
Options to work around this are:
|
||||
|
||||
- Set :ref:`bootloader compiler optimization <CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION>` back to "Size" if it has been changed from this default value.
|
||||
- Reduce :ref:`bootloader log level <CONFIG_BOOTLOADER_LOG_LEVEL>`. Setting log level to Warning, Error or None all significantly reduce the final binary size (but may make it harder to debug).
|
||||
- Set :ref:`partition table offset <CONFIG_PARTITION_TABLE_OFFSET>` to a higher value than 0x8000, to place the partition table later in the flash. This increases the space available for the bootloader. If the :doc:`partition table </api-guides/partition-tables>` CSV file contains explicit partition offsets, they will need changing so no partition has an offset lower than ``CONFIG_PARTITION_TABLE_OFFSET + 0x1000``. (This includes the default partition CSV files supplied with ESP-IDF.)
|
||||
|
||||
Note that because of the absolute binary size limit, there is no benefit to moving the partition table any higher than offset {IDF_TARGET_MAX_PARTITION_TABLE_OFFSET}.
|
||||
@@ -19,7 +19,7 @@ Background
|
||||
|
||||
- Most data is stored in flash. Flash access does not need to be protected from physical access in order for secure boot to function, because critical data is stored (non-software-accessible) in Efuses internal to the chip.
|
||||
|
||||
- Efuses are used to store the secure bootloader key (in efuse BLOCK2), and also a single Efuse bit (ABS_DONE_0) is burned (written to 1) to permanently enable secure boot on the chip. For more details about efuse, see Chapter 11 "eFuse Controller" in the Technical Reference Manual.
|
||||
- Efuses are used to store the secure bootloader key (in efuse BLOCK2), and also a single Efuse bit (ABS_DONE_0) is burned (written to 1) to permanently enable secure boot on the chip. For more details on eFuses, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
|
||||
|
||||
- To understand the secure boot process, first familiarise yourself with the standard :doc:`ESP-IDF boot process <../api-guides/general-notes>`.
|
||||
|
||||
@@ -56,13 +56,7 @@ The following keys are used by the secure boot process:
|
||||
|
||||
- By default, the Efuse Block 2 Coding Scheme is "None" and a 256 bit key is stored in this block. On some {IDF_TARGET_NAME}s, the Coding Scheme is set to 3/4 Encoding (CODING_SCHEME efuse has value 1) and a 192 bit key must be stored in this block.
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
See ESP32 Technical Reference Manual section 20.3.1.3 *System Parameter coding_scheme* for more details.
|
||||
|
||||
.. only:: esp32s2
|
||||
|
||||
See ESP32-S2 Technical Reference Manual for more details.
|
||||
For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* > *System Parameter coding_scheme* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
|
||||
|
||||
The algorithm operates on a 256 bit key in all cases, 192 bit keys are extended by repeating some bits (:ref:`details<secure-bootloader-digest-algorithm>`).
|
||||
|
||||
@@ -72,19 +66,10 @@ The following keys are used by the secure boot process:
|
||||
|
||||
- The private key from this key pair *must be securely kept private*, as anyone who has this key can authenticate to any bootloader that is configured with secure boot and the matching public key.
|
||||
|
||||
.. _secure-boot-bootloader-size:
|
||||
|
||||
Bootloader Size
|
||||
---------------
|
||||
|
||||
When secure boot is enabled the bootloader app binary ``bootloader.bin`` may exceed the default bootloader size limit. This is especially likely if flash encryption is enabled as well. The default size limit is 0x7000 (28672) bytes (partition table offset 0x8000 - bootloader offset 0x1000).
|
||||
|
||||
If the bootloader becomes too large, the {IDF_TARGET_NAME} will fail to boot - errors will be logged about either invalid partition table or invalid bootloader checksum.
|
||||
|
||||
Options to work around this are:
|
||||
|
||||
- Reduce :ref:`bootloader log level <CONFIG_BOOTLOADER_LOG_LEVEL>`. Setting log level to Warning, Error or None all significantly reduce the final binary size (but may make it harder to debug).
|
||||
- Set :ref:`partition table offset <CONFIG_PARTITION_TABLE_OFFSET>` to a higher value than 0x8000, to place the partition table later in the flash. This increases the space available for the bootloader. If the :doc:`partition table </api-guides/partition-tables>` CSV file contains explicit partition offsets, they will need changing so no partition has an offset lower than ``CONFIG_PARTITION_TABLE_OFFSET + 0x1000``. (This includes the default partition CSV files supplied with ESP-IDF.)
|
||||
Enabling Secure boot and/or flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`.
|
||||
|
||||
.. _secure-boot-howto:
|
||||
|
||||
|
||||
@@ -25,11 +25,15 @@ Advantages
|
||||
|
||||
- The RSA public key is stored on the device. The corresponding RSA private key is kept secret on a server and is never accessed by the device.
|
||||
|
||||
- Up to three public keys can be generated and stored in ESP32-S2 during manufacturing. (ESP32 ECO3: only one key)
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
- ESP32-S2 provides the facility to permanently revoke individual public keys. This can be configured conservatively or aggressively.
|
||||
- Only one public key can be generated and stored in ESP32 ECO3 during manufacturing.
|
||||
|
||||
.. only:: esp32s2
|
||||
|
||||
- Up to three public keys can be generated and stored in the chip during manufacturing.
|
||||
|
||||
- {IDF_TARGET_NAME} provides the facility to permanently revoke individual public keys. This can be configured conservatively or aggressively.
|
||||
|
||||
- Conservatively - The old key is revoked after the bootloader and application have successfully migrated to a new key. Aggressively - The key is revoked as soon as verification with this key fails.
|
||||
|
||||
@@ -96,7 +100,15 @@ The remainder of the signature sector is erased flash (0xFF) which allows writin
|
||||
Verifying the signature Block
|
||||
-----------------------------
|
||||
|
||||
A signature block is “valid” if the first byte is 0xe7 and a valid CRC32 is stored at offset 1196. Upto 3 signature blocks can be appended to the bootloader or application image in ESP32-S2. (ESP32 ECO3: only one key)
|
||||
A signature block is “valid” if the first byte is 0xe7 and a valid CRC32 is stored at offset 1196.
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
Only one signature block can be appended to the bootloader or application image in ESP32 ECO3.
|
||||
|
||||
.. only:: esp32s2
|
||||
|
||||
Upto 3 signature blocks can be appended to the bootloader or application image in {IDF_TARGET_NAME}.
|
||||
|
||||
An image is “verified” if the public key stored in any signature block is valid for this device, and if the stored signature is valid for the image data read from flash.
|
||||
|
||||
@@ -113,28 +125,10 @@ An image is “verified” if the public key stored in any signature block is va
|
||||
.. important::
|
||||
It is recommended to use Secure Boot V2 on the chip versions supporting them.
|
||||
|
||||
.. _secure-boot-v2-bootloader-size:
|
||||
|
||||
Bootloader Size
|
||||
---------------
|
||||
|
||||
{IDF_TARGET_MAX_BOOTLOADER_SIZE:default = "64KB (0x10000 bytes)", esp32 = "48KB (0xC000 bytes)"}
|
||||
{IDF_TARGET_MAX_PARTITION_TABLE_OFFSET:default = "0x12000", esp32 = "0xE000"}
|
||||
.. Above is calculated as 0x1000 at start of flash + IDF_TARGET_MAX_BOOTLOADER_SIZE + 0x1000 signature sector
|
||||
|
||||
When secure boot is enabled the bootloader app binary ``bootloader.bin`` may exceed the default bootloader size limit. This is especially likely if flash encryption is enabled as well. The default size limit is 0x7000 (28672) bytes (partition table offset 0x8000 - bootloader offset 0x1000).
|
||||
|
||||
If the bootloader becomes too large, the {IDF_TARGET_NAME} will fail to boot - errors will be logged about either invalid partition table or invalid bootloader checksum.
|
||||
|
||||
When Secure Boot V2 is enabled, there is also an absolute binary size limit of {IDF_TARGET_MAX_BOOTLOADER_SIZE} (excluding the 4KB signature), because the bootloader is first loaded into a fixed size buffer for verification.
|
||||
|
||||
Options to work around this are:
|
||||
|
||||
- Set :ref:`bootloader compiler optimization <CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION>` back to "Size" if it has been changed from this default value.
|
||||
- Reduce :ref:`bootloader log level <CONFIG_BOOTLOADER_LOG_LEVEL>`. Setting log level to Warning, Error or None all significantly reduce the final binary size (but may make it harder to debug).
|
||||
- Set :ref:`partition table offset <CONFIG_PARTITION_TABLE_OFFSET>` to a higher value than 0x8000, to place the partition table later in the flash. This increases the space available for the bootloader. If the :doc:`partition table </api-guides/partition-tables>` CSV file contains explicit partition offsets, they will need changing so no partition has an offset lower than ``CONFIG_PARTITION_TABLE_OFFSET + 0x1000``. (This includes the default partition CSV files supplied with ESP-IDF.)
|
||||
|
||||
Note that because of the absolute binary size limit, there is no benefit to moving the partition table any higher than offset {IDF_TARGET_MAX_PARTITION_TABLE_OFFSET}.
|
||||
Enabling Secure boot and/or flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`secure-boot-bootloader-size`.
|
||||
|
||||
.. _efuse-usage:
|
||||
|
||||
@@ -153,7 +147,7 @@ eFuse usage
|
||||
|
||||
- SECURE_BOOT_EN - Enables secure boot protection on boot.
|
||||
|
||||
- KEY_PURPOSE_X - Set the purpose of the key block on ESP32-S2 by programming SECURE_BOOT_DIGESTX (X = 0, 1, 2) into KEY_PURPOSE_X (X = 0, 1, 2, 3, 4). Example: If KEY_PURPOSE_2 is set to SECURE_BOOT_DIGEST1, then BLOCK_KEY2 will have the Secure Boot V2 public key digest.
|
||||
- KEY_PURPOSE_X - Set the purpose of the key block on {IDF_TARGET_NAME} by programming SECURE_BOOT_DIGESTX (X = 0, 1, 2) into KEY_PURPOSE_X (X = 0, 1, 2, 3, 4, 5). Example: If KEY_PURPOSE_2 is set to SECURE_BOOT_DIGEST1, then BLOCK_KEY2 will have the Secure Boot V2 public key digest.
|
||||
|
||||
- BLOCK_KEYX - The block contains the data corresponding to its purpose programmed in KEY_PURPOSE_X. Stores the SHA-256 digest of the public key. SHA-256 hash of public key modulus, exponent, precalculated R & M’ values (represented as 776 bytes – offsets 36 to 812 - as per the :ref:`signature-block-format`) is written to an eFuse key block.
|
||||
|
||||
@@ -288,6 +282,7 @@ Secure Boot Best Practices
|
||||
* The bootloader can be signed with multiple keys from the factory.
|
||||
|
||||
Assuming a trusted private key (N-1) has been compromised, to update to new keypair (N).
|
||||
|
||||
1. Server sends an OTA update with an application signed with the new private key (#N).
|
||||
2. The new OTA update is written to an unused OTA app partition.
|
||||
3. The new application's signature block is validated. The public keys are checked against the digests programmed in the eFuse & the application is verified using the verified public key.
|
||||
|
||||
145
docs/zh_CN/security/esp32_log.inc
Normal file
145
docs/zh_CN/security/esp32_log.inc
Normal file
@@ -0,0 +1,145 @@
|
||||
|
||||
.. first_boot_enc
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
--- idf_monitor on /dev/cu.SLAB_USBtoUART 115200 ---
|
||||
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
|
||||
ets Jun 8 2016 00:22:57
|
||||
|
||||
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
|
||||
configsip: 0, SPIWP:0xee
|
||||
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
|
||||
mode:DIO, clock div:2
|
||||
load:0x3fff0018,len:4
|
||||
load:0x3fff001c,len:8452
|
||||
load:0x40078000,len:13608
|
||||
load:0x40080400,len:6664
|
||||
entry 0x40080764
|
||||
I (28) boot: ESP-IDF v4.0-dev-850-gc4447462d-dirty 2nd stage bootloader
|
||||
I (29) boot: compile time 15:37:14
|
||||
I (30) boot: Enabling RNG early entropy source...
|
||||
I (35) boot: SPI Speed : 40MHz
|
||||
I (39) boot: SPI Mode : DIO
|
||||
I (43) boot: SPI Flash Size : 4MB
|
||||
I (47) boot: Partition Table:
|
||||
I (51) boot: ## Label Usage Type ST Offset Length
|
||||
I (58) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (66) boot: 1 phy_init RF data 01 01 00010000 00001000
|
||||
I (73) boot: 2 factory factory app 00 00 00020000 00100000
|
||||
I (81) boot: End of partition table
|
||||
I (85) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (105) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844) load
|
||||
I (109) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024) load
|
||||
0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
|
||||
|
||||
I (114) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720) load
|
||||
I (132) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
|
||||
0x400d0018: _flash_cache_start at ??:?
|
||||
|
||||
I (159) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012) load
|
||||
0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
|
||||
|
||||
I (168) boot: Loaded app from partition at offset 0x20000
|
||||
I (168) boot: Checking flash encryption...
|
||||
I (168) flash_encrypt: Generating new flash encryption key...
|
||||
I (187) flash_encrypt: Read & write protecting new key...
|
||||
I (187) flash_encrypt: Setting CRYPT_CONFIG efuse to 0xF
|
||||
W (188) flash_encrypt: Not disabling UART bootloader encryption
|
||||
I (195) flash_encrypt: Disable UART bootloader decryption...
|
||||
I (201) flash_encrypt: Disable UART bootloader MMU cache...
|
||||
I (208) flash_encrypt: Disable JTAG...
|
||||
I (212) flash_encrypt: Disable ROM BASIC interpreter fallback...
|
||||
I (219) esp_image: segment 0: paddr=0x00001020 vaddr=0x3fff0018 size=0x00004 ( 4)
|
||||
I (227) esp_image: segment 1: paddr=0x0000102c vaddr=0x3fff001c size=0x02104 ( 8452)
|
||||
I (239) esp_image: segment 2: paddr=0x00003138 vaddr=0x40078000 size=0x03528 ( 13608)
|
||||
I (249) esp_image: segment 3: paddr=0x00006668 vaddr=0x40080400 size=0x01a08 ( 6664)
|
||||
I (657) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (669) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844)
|
||||
I (672) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024)
|
||||
0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
|
||||
|
||||
I (676) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720)
|
||||
I (692) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
|
||||
0x400d0018: _flash_cache_start at ??:?
|
||||
|
||||
I (719) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012)
|
||||
0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
|
||||
|
||||
I (722) flash_encrypt: Encrypting partition 2 at offset 0x20000...
|
||||
I (13229) flash_encrypt: Flash encryption completed
|
||||
I (13229) boot: Resetting with flash encryption enabled...
|
||||
|
||||
------
|
||||
|
||||
.. already_en_enc
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
|
||||
configsip: 0, SPIWP:0xee
|
||||
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
|
||||
mode:DIO, clock div:2
|
||||
load:0x3fff0018,len:4
|
||||
load:0x3fff001c,len:8452
|
||||
load:0x40078000,len:13652
|
||||
ho 0 tail 12 room 4
|
||||
load:0x40080400,len:6664
|
||||
entry 0x40080764
|
||||
I (30) boot: ESP-IDF v4.0-dev-850-gc4447462d-dirty 2nd stage bootloader
|
||||
I (30) boot: compile time 16:32:53
|
||||
I (31) boot: Enabling RNG early entropy source...
|
||||
I (37) boot: SPI Speed : 40MHz
|
||||
I (41) boot: SPI Mode : DIO
|
||||
I (45) boot: SPI Flash Size : 4MB
|
||||
I (49) boot: Partition Table:
|
||||
I (52) boot: ## Label Usage Type ST Offset Length
|
||||
I (60) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (67) boot: 1 phy_init RF data 01 01 00010000 00001000
|
||||
I (75) boot: 2 factory factory app 00 00 00020000 00100000
|
||||
I (82) boot: End of partition table
|
||||
I (86) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x0808c ( 32908) map
|
||||
I (107) esp_image: segment 1: paddr=0x000280b4 vaddr=0x3ffb0000 size=0x01ea4 ( 7844) load
|
||||
I (111) esp_image: segment 2: paddr=0x00029f60 vaddr=0x40080000 size=0x00400 ( 1024) load
|
||||
0x40080000: _WindowOverflow4 at esp-idf/esp-idf/components/freertos/xtensa_vectors.S:1778
|
||||
|
||||
I (116) esp_image: segment 3: paddr=0x0002a368 vaddr=0x40080400 size=0x05ca8 ( 23720) load
|
||||
I (134) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x126a8 ( 75432) map
|
||||
0x400d0018: _flash_cache_start at ??:?
|
||||
|
||||
I (162) esp_image: segment 5: paddr=0x000426c8 vaddr=0x400860a8 size=0x01f4c ( 8012) load
|
||||
0x400860a8: prvAddNewTaskToReadyList at esp-idf/esp-idf/components/freertos/tasks.c:4561
|
||||
|
||||
I (171) boot: Loaded app from partition at offset 0x20000
|
||||
I (171) boot: Checking flash encryption...
|
||||
I (171) flash_encrypt: flash encryption is enabled (3 plaintext flashes left)
|
||||
I (178) boot: Disabling RNG early entropy source...
|
||||
I (184) cpu_start: Pro cpu up.
|
||||
I (188) cpu_start: Application information:
|
||||
I (193) cpu_start: Project name: flash-encryption
|
||||
I (198) cpu_start: App version: v4.0-dev-850-gc4447462d-dirty
|
||||
I (205) cpu_start: Compile time: Jun 17 2019 16:32:52
|
||||
I (211) cpu_start: ELF file SHA256: 8770c886bdf561a7...
|
||||
I (217) cpu_start: ESP-IDF: v4.0-dev-850-gc4447462d-dirty
|
||||
I (224) cpu_start: Starting app cpu, entry point is 0x40080e4c
|
||||
0x40080e4c: call_start_cpu1 at esp-idf/esp-idf/components/{IDF_TARGET_PATH_NAME}/cpu_start.c:265
|
||||
|
||||
I (0) cpu_start: App cpu up.
|
||||
I (235) heap_init: Initializing. RAM available for dynamic allocation:
|
||||
I (241) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
|
||||
I (247) heap_init: At 3FFB2EC8 len 0002D138 (180 KiB): DRAM
|
||||
I (254) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
|
||||
I (260) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
|
||||
I (266) heap_init: At 40087FF4 len 0001800C (96 KiB): IRAM
|
||||
I (273) cpu_start: Pro cpu start user code
|
||||
I (291) cpu_start: Starting scheduler on PRO CPU.
|
||||
I (0) cpu_start: Starting scheduler on APP CPU.
|
||||
|
||||
Sample program to check Flash Encryption
|
||||
This is ESP32 chip with 2 CPU cores, WiFi/BT/BLE, silicon revision 1, 4MB external flash
|
||||
Flash encryption feature is enabled
|
||||
Flash encryption mode is DEVELOPMENT
|
||||
Flash in encrypted mode with flash_crypt_cnt = 1
|
||||
Halting...
|
||||
|
||||
------
|
||||
155
docs/zh_CN/security/esp32s2_log.inc
Normal file
155
docs/zh_CN/security/esp32s2_log.inc
Normal file
@@ -0,0 +1,155 @@
|
||||
|
||||
.. first_boot_enc
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
ESP-ROM:esp32s2-rc4-20191025
|
||||
Build:Oct 25 2019
|
||||
rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
|
||||
SPIWP:0xee
|
||||
mode:DIO, clock div:1
|
||||
load:0x3ffe6260,len:0x78
|
||||
load:0x3ffe62d8,len:0x231c
|
||||
load:0x4004c000,len:0x9d8
|
||||
load:0x40050000,len:0x3cf8
|
||||
entry 0x4004c1ec
|
||||
I (48) boot: ESP-IDF qa-test-v4.3-20201113-777-gd8e1 2nd stage bootloader
|
||||
I (48) boot: compile time 11:24:04
|
||||
I (48) boot: chip revision: 0
|
||||
I (52) boot.esp32s2: SPI Speed : 80MHz
|
||||
I (57) boot.esp32s2: SPI Mode : DIO
|
||||
I (62) boot.esp32s2: SPI Flash Size : 2MB
|
||||
I (66) boot: Enabling RNG early entropy source...
|
||||
I (72) boot: Partition Table:
|
||||
I (75) boot: ## Label Usage Type ST Offset Length
|
||||
I (83) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (90) boot: 1 storage Unknown data 01 ff 00010000 00001000
|
||||
I (98) boot: 2 factory factory app 00 00 00020000 00100000
|
||||
I (105) boot: End of partition table
|
||||
I (109) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f000020 size=0x0618c ( 24972) map
|
||||
I (124) esp_image: segment 1: paddr=0x000261b4 vaddr=0x3ffbcae0 size=0x02624 ( 9764) load
|
||||
I (129) esp_image: segment 2: paddr=0x000287e0 vaddr=0x40022000 size=0x00404 ( 1028) load
|
||||
0x40022000: _WindowOverflow4 at /home/marius/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730
|
||||
|
||||
I (136) esp_image: segment 3: paddr=0x00028bec vaddr=0x40022404 size=0x0742c ( 29740) load
|
||||
0x40022404: _coredump_iram_end at ??:?
|
||||
|
||||
I (153) esp_image: segment 4: paddr=0x00030020 vaddr=0x40080020 size=0x1457c ( 83324) map
|
||||
0x40080020: _stext at ??:?
|
||||
|
||||
I (171) esp_image: segment 5: paddr=0x000445a4 vaddr=0x40029830 size=0x032ac ( 12972) load
|
||||
0x40029830: gpspi_flash_ll_set_miso_bitlen at /home/marius/esp-idf/examples/security/flash_encryption/build/../../../../components/hal/esp32s2/include/hal/gpspi_flash_ll.h:261
|
||||
(inlined by) spi_flash_hal_gpspi_common_command at /home/marius/esp-idf/components/hal/spi_flash_hal_common.inc:161
|
||||
|
||||
I (181) boot: Loaded app from partition at offset 0x20000
|
||||
I (181) boot: Checking flash encryption...
|
||||
I (181) efuse: Batch mode of writing fields is enabled
|
||||
I (188) flash_encrypt: Generating new flash encryption key...
|
||||
W (199) flash_encrypt: Not disabling UART bootloader encryption
|
||||
I (201) flash_encrypt: Disable UART bootloader cache...
|
||||
I (207) flash_encrypt: Disable JTAG...
|
||||
I (212) efuse: Batch mode of writing fields is disabled
|
||||
I (217) esp_image: segment 0: paddr=0x00001020 vaddr=0x3ffe6260 size=0x00078 ( 120)
|
||||
I (226) esp_image: segment 1: paddr=0x000010a0 vaddr=0x3ffe62d8 size=0x0231c ( 8988)
|
||||
I (236) esp_image: segment 2: paddr=0x000033c4 vaddr=0x4004c000 size=0x009d8 ( 2520)
|
||||
I (243) esp_image: segment 3: paddr=0x00003da4 vaddr=0x40050000 size=0x03cf8 ( 15608)
|
||||
I (651) flash_encrypt: bootloader encrypted successfully
|
||||
I (704) flash_encrypt: partition table encrypted and loaded successfully
|
||||
I (704) flash_encrypt: Encrypting partition 1 at offset 0x10000 (length 0x1000)...
|
||||
I (765) flash_encrypt: Done encrypting
|
||||
I (766) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f000020 size=0x0618c ( 24972) map
|
||||
I (773) esp_image: segment 1: paddr=0x000261b4 vaddr=0x3ffbcae0 size=0x02624 ( 9764)
|
||||
I (778) esp_image: segment 2: paddr=0x000287e0 vaddr=0x40022000 size=0x00404 ( 1028)
|
||||
0x40022000: _WindowOverflow4 at /home/marius/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730
|
||||
|
||||
I (785) esp_image: segment 3: paddr=0x00028bec vaddr=0x40022404 size=0x0742c ( 29740)
|
||||
0x40022404: _coredump_iram_end at ??:?
|
||||
|
||||
I (799) esp_image: segment 4: paddr=0x00030020 vaddr=0x40080020 size=0x1457c ( 83324) map
|
||||
0x40080020: _stext at ??:?
|
||||
|
||||
I (820) esp_image: segment 5: paddr=0x000445a4 vaddr=0x40029830 size=0x032ac ( 12972)
|
||||
0x40029830: gpspi_flash_ll_set_miso_bitlen at /home/marius/esp-idf/examples/security/flash_encryption/build/../../../../components/hal/esp32s2/include/hal/gpspi_flash_ll.h:261
|
||||
(inlined by) spi_flash_hal_gpspi_common_command at /home/marius/esp-idf/components/hal/spi_flash_hal_common.inc:161
|
||||
|
||||
I (823) flash_encrypt: Encrypting partition 2 at offset 0x20000 (length 0x100000)...
|
||||
I (13869) flash_encrypt: Done encrypting
|
||||
I (13870) flash_encrypt: Flash encryption completed
|
||||
I (13870) boot: Resetting with flash encryption enabled...
|
||||
|
||||
|
||||
------
|
||||
|
||||
.. already_en_enc
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
ESP-ROM:esp32s2-rc4-20191025
|
||||
Build:Oct 25 2019
|
||||
rst:0x3 (RTC_SW_SYS_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
|
||||
Saved PC:0x40051242
|
||||
SPIWP:0xee
|
||||
mode:DIO, clock div:1
|
||||
load:0x3ffe6260,len:0x78
|
||||
load:0x3ffe62d8,len:0x231c
|
||||
load:0x4004c000,len:0x9d8
|
||||
load:0x40050000,len:0x3cf8
|
||||
entry 0x4004c1ec
|
||||
I (56) boot: ESP-IDF qa-test-v4.3-20201113-777-gd8e1 2nd stage bootloader
|
||||
I (56) boot: compile time 11:24:04
|
||||
I (56) boot: chip revision: 0
|
||||
I (60) boot.esp32s2: SPI Speed : 80MHz
|
||||
I (65) boot.esp32s2: SPI Mode : DIO
|
||||
I (69) boot.esp32s2: SPI Flash Size : 2MB
|
||||
I (74) boot: Enabling RNG early entropy source...
|
||||
I (80) boot: Partition Table:
|
||||
I (83) boot: ## Label Usage Type ST Offset Length
|
||||
I (90) boot: 0 nvs WiFi data 01 02 0000a000 00006000
|
||||
I (98) boot: 1 storage Unknown data 01 ff 00010000 00001000
|
||||
I (105) boot: 2 factory factory app 00 00 00020000 00100000
|
||||
I (113) boot: End of partition table
|
||||
I (117) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f000020 size=0x0618c ( 24972) map
|
||||
I (132) esp_image: segment 1: paddr=0x000261b4 vaddr=0x3ffbcae0 size=0x02624 ( 9764) load
|
||||
I (137) esp_image: segment 2: paddr=0x000287e0 vaddr=0x40022000 size=0x00404 ( 1028) load
|
||||
0x40022000: _WindowOverflow4 at /home/marius/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730
|
||||
|
||||
I (144) esp_image: segment 3: paddr=0x00028bec vaddr=0x40022404 size=0x0742c ( 29740) load
|
||||
0x40022404: _coredump_iram_end at ??:?
|
||||
|
||||
I (161) esp_image: segment 4: paddr=0x00030020 vaddr=0x40080020 size=0x1457c ( 83324) map
|
||||
0x40080020: _stext at ??:?
|
||||
|
||||
I (180) esp_image: segment 5: paddr=0x000445a4 vaddr=0x40029830 size=0x032ac ( 12972) load
|
||||
0x40029830: gpspi_flash_ll_set_miso_bitlen at /home/marius/esp-idf/examples/security/flash_encryption/build/../../../../components/hal/esp32s2/include/hal/gpspi_flash_ll.h:261
|
||||
(inlined by) spi_flash_hal_gpspi_common_command at /home/marius/esp-idf/components/hal/spi_flash_hal_common.inc:161
|
||||
|
||||
I (190) boot: Loaded app from partition at offset 0x20000
|
||||
I (191) boot: Checking flash encryption...
|
||||
I (191) flash_encrypt: flash encryption is enabled (1 plaintext flashes left)
|
||||
I (199) boot: Disabling RNG early entropy source...
|
||||
I (216) cache: Instruction cache : size 8KB, 4Ways, cache line size 32Byte
|
||||
I (216) cpu_start: Pro cpu up.
|
||||
I (268) cpu_start: Pro cpu start user code
|
||||
I (268) cpu_start: cpu freq: 160000000
|
||||
I (268) cpu_start: Application information:
|
||||
I (271) cpu_start: Project name: flash_encryption
|
||||
I (277) cpu_start: App version: qa-test-v4.3-20201113-777-gd8e1
|
||||
I (284) cpu_start: Compile time: Dec 21 2020 11:24:00
|
||||
I (290) cpu_start: ELF file SHA256: 30fd1b899312fef7...
|
||||
I (296) cpu_start: ESP-IDF: qa-test-v4.3-20201113-777-gd8e1
|
||||
I (303) heap_init: Initializing. RAM available for dynamic allocation:
|
||||
I (310) heap_init: At 3FF9E000 len 00002000 (8 KiB): RTCRAM
|
||||
I (316) heap_init: At 3FFBF898 len 0003C768 (241 KiB): DRAM
|
||||
I (323) heap_init: At 3FFFC000 len 00003A10 (14 KiB): DRAM
|
||||
W (329) flash_encrypt: Flash encryption mode is DEVELOPMENT (not secure)
|
||||
I (336) spi_flash: detected chip: generic
|
||||
I (341) spi_flash: flash io: dio
|
||||
W (345) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
|
||||
I (358) cpu_start: Starting scheduler on PRO CPU.
|
||||
|
||||
Example to check Flash Encryption status
|
||||
This is esp32s2 chip with 1 CPU core(s), WiFi, silicon revision 0, 2MB external flash
|
||||
FLASH_CRYPT_CNT eFuse value is 1
|
||||
Flash encryption feature is enabled in DEVELOPMENT mode
|
||||
|
||||
------
|
||||
1
docs/zh_CN/security/secure-boot-bootloader-size.rst
Normal file
1
docs/zh_CN/security/secure-boot-bootloader-size.rst
Normal file
@@ -0,0 +1 @@
|
||||
.. include:: ../../en/security/secure-boot-bootloader-size.rst
|
||||
Reference in New Issue
Block a user