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Merge branch 'refactor/sync_lp_ana_peri_csv_update_on_c5' into 'master'

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change(soc): update lp_ana_peri soc header on C5

See merge request espressif/esp-idf!35168
This commit is contained in:
Kevin (Lao Kaiyao)
2024-11-27 10:02:54 +08:00
parent 64960f0751 13f7b55ae5
commit 32b5359693
9 changed files with 138 additions and 200 deletions
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4
components/bootloader_support/src/esp32c5/bootloader_soc.c
View File

@@ -28,8 +28,8 @@ void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
} else {
REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
}
}

119
components/soc/esp32c5/register/soc/lp_analog_peri_reg.h
View File

@@ -12,72 +12,75 @@ extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
* Configure brownout mode0
* Brownout detector mode 0 configuration register
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
* enable suspend spi when brownout interrupt or not
* 1:enable
* 0:disable
* Configures whether to enable the brown-out detector to trigger flash suspend.
* 0: Disable
* 1: Enable
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6))
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6
/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
* enable power down RF when brownout interrupt or not
* 1:enable
* 0:disable
* Configures whether to enable the brown-out detector to power down the RF module.
* 0: Disable
* 1: Enable
*/
#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7))
#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7
/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
* set the undervoltage hold time for triggering brownout interrupt
* Configures the time to generate an interrupt after the brown-out signal is valid.
* The unit is LP_FAST_CLK cycles.
*/
#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8
/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
* set the undervoltage hold time for triggering brownout reset
* Configures the time to generate a reset after the brown-out signal is valid. The
* unit is LP_FAST_CLK cycles.
*/
#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18
/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
* clear brownout count or not
* 1: clear
* 0: no operation
* Configures whether to clear the count value of the brown-out detector.
* 0: Do not clear
* 1: Clear
*/
#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28))
#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_CNT_CLR_S 28
/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
* enable brownout interrupt or not
* 1: enable
* 0: disable
* Enables the interrupts for the brown-out detector mode 0. LP_ANA_BOD_MODE0_INT_RAW
* and LP_ANA_BOD_MODE0_LP_INT_RAW are valid only when this field is set to 1.
* 0: Disable
* 1: Enable
*/
#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29))
#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INTR_ENA_S 29
/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
* select brownout reset level
* 1: system reset
* 0: chip reset
* Configures the reset type when the brown-out detector is triggered.
* 0: Chip reset
* 1: System reset
*/
#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30))
#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_SEL_S 30
/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
* enable brownout reset or not
* 1: enable
* 0: disable
* Configures whether to enable reset for the brown-out detector.
* 0: Disable
* 1: Enable
*/
#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
@@ -85,44 +88,43 @@ extern "C" {
#define LP_ANA_BOD_MODE0_RESET_ENA_S 31
/** LP_ANA_BOD_MODE1_CNTL_REG register
* Configure brownout mode1
* Brownout detector mode 1 configuration register
*/
#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
* enable brownout mode1 reset or not
* 1: enable
* 0: disable
* Configures whether to enable brown-out detector mode 1.
* 0: Disable
* 1: Enable
*/
#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE1_RESET_ENA_S 31
/** LP_ANA_CK_GLITCH_CNTL_REG register
* Configure power glitch
/** LP_ANA_POWER_GLITCH_CNTL_REG register
* Voltage glitch configuration register
*/
#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
#define LP_ANA_POWER_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
/** LP_ANA_PWR_GLITCH_RESET_ENA : R/W; bitpos: [30:27]; default: 0;
* enable powerglitch or not
* Configures whether to enable the voltage glitch detectors. Bit0, bit1, bit2, bit3
* correspond to VDDPST2/3, VDDPST1, VDDA3, and VDDA8, respectively.
* 0: Disable
* 1: Enable
*/
#define LP_ANA_PWR_GLITCH_RESET_ENA 0x0000000FU
#define LP_ANA_PWR_GLITCH_RESET_ENA_M (LP_ANA_PWR_GLITCH_RESET_ENA_V << LP_ANA_PWR_GLITCH_RESET_ENA_S)
#define LP_ANA_PWR_GLITCH_RESET_ENA_V 0x0000000FU
#define LP_ANA_PWR_GLITCH_RESET_ENA_S 27
/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* reserved
*/
#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANA_FIB_ENABLE_REG register
* configure FIB REG
* Voltage glitch detectors' enable control register
*/
#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
* configure analog fib by software
* Controls the enable of the voltage glitch detectors. Bit2, bit3, bit4, bit5
* correspond to VDDPST2/3, VDDPST1, VDDA3, and VDDA8, respectively.
* 0: Controlled by LP_ANA_PWR_GLITCH_RESET_ENA
* 1: Forcibly enabled by hardware
*/
#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
@@ -135,11 +137,11 @@ extern "C" {
#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S 2
/** LP_ANA_INT_RAW_REG register
* interrpt raw register
* LP_ANA_BOD_MODE0_INT raw interrupt
*/
#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 interrupt raw register
* The raw interrupt status of LP_ANA_BOD_MODE0_INT.
*/
#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
@@ -147,11 +149,11 @@ extern "C" {
#define LP_ANA_BOD_MODE0_INT_RAW_S 31
/** LP_ANA_INT_ST_REG register
* interrpt status register
* LP_ANA_BOD_MODE0_INT state interrupt
*/
#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
* brownout mode0 interrupt status register
* The masked interrupt status of LP_ANA_BOD_MODE0_INT.
*/
#define LP_ANA_BOD_MODE0_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
@@ -159,11 +161,11 @@ extern "C" {
#define LP_ANA_BOD_MODE0_INT_ST_S 31
/** LP_ANA_INT_ENA_REG register
* interrpt enable register
* LP_ANA_BOD_MODE0_INT enable register
*/
#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
* brownout mode0 interrupt enable register
* Write 1 to enable LP_ANA_BOD_MODE0_INT.
*/
#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
@@ -171,11 +173,11 @@ extern "C" {
#define LP_ANA_BOD_MODE0_INT_ENA_S 31
/** LP_ANA_INT_CLR_REG register
* interrpt clear register
* LP_ANA_BOD_MODE0_INT clear register
*/
#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
* brownout mode0 interrupt clear register
* Write 1 to clear LP_ANA_BOD_MODE0_INT.
*/
#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
@@ -183,11 +185,11 @@ extern "C" {
#define LP_ANA_BOD_MODE0_INT_CLR_S 31
/** LP_ANA_LP_INT_RAW_REG register
* lp interrupt raw register
* LP_ANA_BOD_MODE0_LP_INT raw interrupt
*/
#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt raw register
* The raw interrupt status of LP_ANA_BOD_MODE0_LP_INT.
*/
#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
@@ -195,11 +197,11 @@ extern "C" {
#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31
/** LP_ANA_LP_INT_ST_REG register
* lp interrupt status register
* LP_ANA_BOD_MODE0_LP_INT state interrupt
*/
#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt status register
* The masked interrupt status of LP_ANA_BOD_MODE0_LP_INT.
*/
#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
@@ -207,11 +209,11 @@ extern "C" {
#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31
/** LP_ANA_LP_INT_ENA_REG register
* lp interrupt enable register
* LP_ANA_BOD_MODE0_LP_INT enable register
*/
#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt enable register
* Write 1 to enable LP_ANA_BOD_MODE0_LP_INT.
*/
#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
@@ -219,11 +221,11 @@ extern "C" {
#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31
/** LP_ANA_LP_INT_CLR_REG register
* lp interrupt clear register
* LP_ANA_BOD_MODE0_LP_INT clear register
*/
#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt clear register
* Write 1 to clear LP_ANA_BOD_MODE0_LP_INT.
*/
#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
@@ -231,18 +233,21 @@ extern "C" {
#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31
/** LP_ANA_DATE_REG register
* version register
* Version control register
*/
#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 36774528;
* version register
* Version control register.
*/
#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_S 0
/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
* reserved
* Configures whether to force enable register clock.
* 0: Automatic clock gating
* 1: Force enable register clock
* The configuration of this field does not effect the access of registers.
*/
#define LP_ANA_CLK_EN (BIT(31))
#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)

123
components/soc/esp32c5/register/soc/lp_analog_peri_struct.h
View File

@@ -10,55 +10,58 @@
extern "C" {
#endif
/** Group: configure_register */
/** Group: Configuration Registers */
/** Type of bod_mode0_cntl register
* Configure brownout mode0
* Brownout detector mode 0 configuration register
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
* enable suspend spi when brownout interrupt or not
* 1:enable
* 0:disable
* Configures whether to enable the brown-out detector to trigger flash suspend.
* 0: Disable
* 1: Enable
*/
uint32_t bod_mode0_close_flash_ena:1;
/** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
* enable power down RF when brownout interrupt or not
* 1:enable
* 0:disable
* Configures whether to enable the brown-out detector to power down the RF module.
* 0: Disable
* 1: Enable
*/
uint32_t bod_mode0_pd_rf_ena:1;
/** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
* set the undervoltage hold time for triggering brownout interrupt
* Configures the time to generate an interrupt after the brown-out signal is valid.
* The unit is LP_FAST_CLK cycles.
*/
uint32_t bod_mode0_intr_wait:10;
/** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
* set the undervoltage hold time for triggering brownout reset
* Configures the time to generate a reset after the brown-out signal is valid. The
* unit is LP_FAST_CLK cycles.
*/
uint32_t bod_mode0_reset_wait:10;
/** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
* clear brownout count or not
* 1: clear
* 0: no operation
* Configures whether to clear the count value of the brown-out detector.
* 0: Do not clear
* 1: Clear
*/
uint32_t bod_mode0_cnt_clr:1;
/** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
* enable brownout interrupt or not
* 1: enable
* 0: disable
* Enables the interrupts for the brown-out detector mode 0. LP_ANA_BOD_MODE0_INT_RAW
* and LP_ANA_BOD_MODE0_LP_INT_RAW are valid only when this field is set to 1.
* 0: Disable
* 1: Enable
*/
uint32_t bod_mode0_intr_ena:1;
/** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
* select brownout reset level
* 1: system reset
* 0: chip reset
* Configures the reset type when the brown-out detector is triggered.
* 0: Chip reset
* 1: System reset
*/
uint32_t bod_mode0_reset_sel:1;
/** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
* enable brownout reset or not
* 1: enable
* 0: disable
* Configures whether to enable reset for the brown-out detector.
* 0: Disable
* 1: Enable
*/
uint32_t bod_mode0_reset_ena:1;
};
@@ -66,46 +69,49 @@ typedef union {
} lp_ana_bod_mode0_cntl_reg_t;
/** Type of bod_mode1_cntl register
* Configure brownout mode1
* Brownout detector mode 1 configuration register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
* enable brownout mode1 reset or not
* 1: enable
* 0: disable
* Configures whether to enable brown-out detector mode 1.
* 0: Disable
* 1: Enable
*/
uint32_t bod_mode1_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode1_cntl_reg_t;
/** Type of ck_glitch_cntl register
* Configure power glitch
/** Type of power_glitch_cntl register
* Voltage glitch configuration register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** pwr_glitch_reset_ena : R/W; bitpos: [30:27]; default: 0;
* enable powerglitch or not
* Configures whether to enable the voltage glitch detectors. Bit0, bit1, bit2, bit3
* correspond to VDDPST2/3, VDDPST1, VDDA3, and VDDA8, respectively.
* 0: Disable
* 1: Enable
*/
uint32_t pwr_glitch_reset_ena:4;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* reserved
*/
uint32_t ck_glitch_reset_ena:1;
uint32_t reserved_31:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
} lp_ana_power_glitch_cntl_reg_t;
/** Type of fib_enable register
* configure FIB REG
* Voltage glitch detectors' enable control register
*/
typedef union {
struct {
/** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
* configure analog fib by software
* Controls the enable of the voltage glitch detectors. Bit2, bit3, bit4, bit5
* correspond to VDDPST2/3, VDDPST1, VDDA3, and VDDA8, respectively.
* 0: Controlled by LP_ANA_PWR_GLITCH_RESET_ENA
* 1: Forcibly enabled by hardware
*/
uint32_t ana_fib_ena:32;
};
@@ -113,13 +119,13 @@ typedef union {
} lp_ana_fib_enable_reg_t;
/** Type of int_raw register
* interrpt raw register
* LP_ANA_BOD_MODE0_INT raw interrupt
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 interrupt raw register
* The raw interrupt status of LP_ANA_BOD_MODE0_INT.
*/
uint32_t bod_mode0_int_raw:1;
};
@@ -127,13 +133,13 @@ typedef union {
} lp_ana_int_raw_reg_t;
/** Type of int_st register
* interrpt status register
* LP_ANA_BOD_MODE0_INT state interrupt
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
* brownout mode0 interrupt status register
* The masked interrupt status of LP_ANA_BOD_MODE0_INT.
*/
uint32_t bod_mode0_int_st:1;
};
@@ -141,13 +147,13 @@ typedef union {
} lp_ana_int_st_reg_t;
/** Type of int_ena register
* interrpt enable register
* LP_ANA_BOD_MODE0_INT enable register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
* brownout mode0 interrupt enable register
* Write 1 to enable LP_ANA_BOD_MODE0_INT.
*/
uint32_t bod_mode0_int_ena:1;
};
@@ -155,13 +161,13 @@ typedef union {
} lp_ana_int_ena_reg_t;
/** Type of int_clr register
* interrpt clear register
* LP_ANA_BOD_MODE0_INT clear register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
* brownout mode0 interrupt clear register
* Write 1 to clear LP_ANA_BOD_MODE0_INT.
*/
uint32_t bod_mode0_int_clr:1;
};
@@ -169,13 +175,13 @@ typedef union {
} lp_ana_int_clr_reg_t;
/** Type of lp_int_raw register
* lp interrupt raw register
* LP_ANA_BOD_MODE0_LP_INT raw interrupt
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt raw register
* The raw interrupt status of LP_ANA_BOD_MODE0_LP_INT.
*/
uint32_t bod_mode0_lp_int_raw:1;
};
@@ -183,13 +189,13 @@ typedef union {
} lp_ana_lp_int_raw_reg_t;
/** Type of lp_int_st register
* lp interrupt status register
* LP_ANA_BOD_MODE0_LP_INT state interrupt
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt status register
* The masked interrupt status of LP_ANA_BOD_MODE0_LP_INT.
*/
uint32_t bod_mode0_lp_int_st:1;
};
@@ -197,13 +203,13 @@ typedef union {
} lp_ana_lp_int_st_reg_t;
/** Type of lp_int_ena register
* lp interrupt enable register
* LP_ANA_BOD_MODE0_LP_INT enable register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt enable register
* Write 1 to enable LP_ANA_BOD_MODE0_LP_INT.
*/
uint32_t bod_mode0_lp_int_ena:1;
};
@@ -211,30 +217,35 @@ typedef union {
} lp_ana_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* lp interrupt clear register
* LP_ANA_BOD_MODE0_LP_INT clear register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt clear register
* Write 1 to clear LP_ANA_BOD_MODE0_LP_INT.
*/
uint32_t bod_mode0_lp_int_clr:1;
};
uint32_t val;
} lp_ana_lp_int_clr_reg_t;
/** Group: Version Control Registers */
/** Type of date register
* version register
* Version control register
*/
typedef union {
struct {
/** lp_ana_date : R/W; bitpos: [30:0]; default: 36774528;
* version register
* Version control register.
*/
uint32_t lp_ana_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* reserved
* Configures whether to force enable register clock.
* 0: Automatic clock gating
* 1: Force enable register clock
* The configuration of this field does not effect the access of registers.
*/
uint32_t clk_en:1;
};
@@ -245,7 +256,7 @@ typedef union {
typedef struct {
volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
volatile lp_ana_power_glitch_cntl_reg_t power_glitch_cntl;
volatile lp_ana_fib_enable_reg_t fib_enable;
volatile lp_ana_int_raw_reg_t int_raw;
volatile lp_ana_int_st_reg_t int_st;

14
components/soc/esp32c6/register/soc/lp_analog_peri_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -84,18 +84,6 @@ extern "C" {
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_S 31
/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x8)
/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG register
* need_des
*/

18
components/soc/esp32c6/register/soc/lp_analog_peri_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -67,20 +67,6 @@ typedef union {
uint32_t val;
} lp_ana_bod_mode1_cntl_reg_t;
/** Type of ck_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
/** Type of fib_enable register
* need_des
*/
@@ -227,7 +213,7 @@ typedef union {
typedef struct lp_ana_dev_t {
volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
uint32_t reserved_008;
volatile lp_ana_fib_enable_reg_t fib_enable;
volatile lp_ana_int_raw_reg_t int_raw;
volatile lp_ana_int_st_reg_t int_st;

14
components/soc/esp32h2/register/soc/lp_analog_peri_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -197,18 +197,6 @@ extern "C" {
#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU
#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22
/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14)
/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANALOG_PERI_LP_ANA_PG_GLITCH_CNTL_REG register
* need_des
*/

18
components/soc/esp32h2/register/soc/lp_analog_peri_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -152,20 +152,6 @@ typedef union {
uint32_t val;
} lp_ana_vddbat_charge_cntl_reg_t;
/** Type of ck_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
/** Type of pg_glitch_cntl register
* need_des
*/
@@ -393,7 +379,7 @@ typedef struct {
volatile lp_ana_vdd_source_cntl_reg_t vdd_source_cntl;
volatile lp_ana_vddbat_bod_cntl_reg_t vddbat_bod_cntl;
volatile lp_ana_vddbat_charge_cntl_reg_t vddbat_charge_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
uint32_t reserved_014;
volatile lp_ana_pg_glitch_cntl_reg_t pg_glitch_cntl;
volatile lp_ana_fib_enable_reg_t fib_enable;
volatile lp_ana_int_raw_reg_t int_raw;

12
components/soc/esp32p4/register/soc/lp_analog_peri_reg.h
View File

@@ -197,18 +197,6 @@ extern "C" {
#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU
#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22
/** LP_ANALOG_PERI_CK_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANALOG_PERI_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14)
/** LP_ANALOG_PERI_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_S)
#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_S 31
/** LP_ANALOG_PERI_PG_GLITCH_CNTL_REG register
* need_des
*/

16
components/soc/esp32p4/register/soc/lp_analog_peri_struct.h
View File

@@ -152,20 +152,6 @@ typedef union {
uint32_t val;
} lp_analog_peri_vddbat_charge_cntl_reg_t;
/** Type of ck_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_analog_peri_ck_glitch_cntl_reg_t;
/** Type of pg_glitch_cntl register
* need_des
*/
@@ -853,7 +839,7 @@ typedef struct {
volatile lp_analog_peri_vdd_source_cntl_reg_t vdd_source_cntl;
volatile lp_analog_peri_vddbat_bod_cntl_reg_t vddbat_bod_cntl;
volatile lp_analog_peri_vddbat_charge_cntl_reg_t vddbat_charge_cntl;
volatile lp_analog_peri_ck_glitch_cntl_reg_t ck_glitch_cntl;
uint32_t reserved_014;
volatile lp_analog_peri_pg_glitch_cntl_reg_t pg_glitch_cntl;
volatile lp_analog_peri_fib_enable_reg_t fib_enable;
volatile lp_analog_peri_int_raw_reg_t int_raw;