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essl: update essl component in driver test

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This commit is contained in:
Armando
2023-01-06 16:16:02 +08:00
committed by Armando (Dou Yiwen)
parent 57d9cb5ef6
commit 38551239fd
6 changed files with 73 additions and 13 deletions
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2
components/driver/test_apps/components/esp_serial_slave_link/CMakeLists.txt
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@@ -5,7 +5,7 @@ if(CONFIG_SOC_GPSPI_SUPPORTED)
endif()
if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED)
list(APPEND srcs "essl_sdio.c")
list(APPEND srcs "essl_sdio.c" "essl_sdio_defs.c")
endif()
idf_component_register(

24
components/driver/test_apps/components/esp_serial_slave_link/essl_sdio.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,12 +12,24 @@
#include "essl_internal.h"
#include "essl_sdio.h"
#if SOC_SDIO_SLAVE_SUPPORTED
#include "soc/host_reg.h"
static const char TAG[] = "essl_sdio";
#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
#ifndef DR_REG_SLCHOST_BASE
#define DR_REG_SLCHOST_BASE 0 //The SDIO slave only check the least significant 10 bits, this doesn't matter
#endif
//This should be consistent with the macro in soc/host_reg.h
#define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
#define HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
#define HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
#define HOST_SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
#define HOST_SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6C)
#define HOST_SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8C)
#define HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD4)
#define HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xDC)
#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
#define ESSL_CMD53_END_ADDR 0x1f800
@@ -495,5 +507,3 @@ void essl_sdio_reset_cnt(void *arg)
ctx->rx_got_bytes = 0;
ctx->tx_sent_buffers = 0;
}
#endif // #if SOC_SDIO_SLAVE_SUPPORTED

18
components/driver/test_apps/components/esp_serial_slave_link/essl_sdio_defs.c Normal file
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@@ -0,0 +1,18 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Definitions of Espressif SDIO Slave hardware
#include "essl_sdio.h"
essl_sdio_def_t ESSL_SDIO_DEF_ESP32 = {
.new_packet_intr_mask = BIT(23),
};
essl_sdio_def_t ESSL_SDIO_DEF_ESP32C6 = {
.new_packet_intr_mask = BIT(23),
};

7
components/driver/test_apps/components/esp_serial_slave_link/essl_spi.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -267,9 +267,8 @@ static esp_err_t essl_spi_update_tx_buffer_num(void *arg, uint32_t wait_ms);
esp_err_t essl_spi_init_dev(essl_handle_t *out_handle, const essl_spi_config_t *init_config)
{
ESP_RETURN_ON_FALSE(init_config->spi, ESP_ERR_INVALID_STATE, TAG, "Check SPI initialization first");
// for esp32-s2 SOC_SPI_MAXIMUM_BUFFER_SIZE is 72, so compiler warns that comparisons of 'tx/rx_sync_reg' are always true
ESP_RETURN_ON_FALSE((uint32_t)init_config->tx_sync_reg <= (SOC_SPI_MAXIMUM_BUFFER_SIZE - 1) * 4, ESP_ERR_INVALID_ARG, TAG, "GPSPI supports %d-byte-width internal registers", SOC_SPI_MAXIMUM_BUFFER_SIZE);
ESP_RETURN_ON_FALSE((uint32_t)init_config->rx_sync_reg <= (SOC_SPI_MAXIMUM_BUFFER_SIZE - 1) * 4, ESP_ERR_INVALID_ARG, TAG, "GPSPI supports %d-byte-width internal registers", SOC_SPI_MAXIMUM_BUFFER_SIZE);
ESP_RETURN_ON_FALSE(init_config->tx_sync_reg <= (SOC_SPI_MAXIMUM_BUFFER_SIZE - 1) * 4, ESP_ERR_INVALID_ARG, TAG, "GPSPI supports %d-byte-width internal registers", SOC_SPI_MAXIMUM_BUFFER_SIZE);
ESP_RETURN_ON_FALSE(init_config->rx_sync_reg <= (SOC_SPI_MAXIMUM_BUFFER_SIZE - 1) * 4, ESP_ERR_INVALID_ARG, TAG, "GPSPI supports %d-byte-width internal registers", SOC_SPI_MAXIMUM_BUFFER_SIZE);
ESP_RETURN_ON_FALSE(init_config->tx_sync_reg != init_config->rx_sync_reg, ESP_ERR_INVALID_ARG, TAG, "Should use different word of registers for synchronization");
essl_spi_context_t *context = calloc(1, sizeof(essl_spi_context_t));

4
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,9 +9,11 @@
#pragma once
#include "esp_err.h"
#include "driver/sdmmc_types.h"
#include "driver/sdmmc_host.h"
#include "esp_serial_slave_link/essl.h"
#include "essl_sdio_defs.h"
#ifdef __cplusplus
extern "C" {

31
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio_defs.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* This file contains SDIO Slave hardware specific requirements
*/
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
//interrupts
uint32_t new_packet_intr_mask;
} essl_sdio_def_t;
/// Definitions of ESP32 SDIO Slave hardware
extern essl_sdio_def_t ESSL_SDIO_DEF_ESP32;
/// Definitions of ESP32C6 SDIO Slave hardware
extern essl_sdio_def_t ESSL_SDIO_DEF_ESP32C6;
#ifdef __cplusplus
}
#endif