forked from espressif/esp-idf
feat(efuse): Support efuses for ESP32-C5 ECO2
This commit is contained in:
Konstantin Kondrashov
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -9,7 +9,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table b26e7466c400977081a142076ef1a5bb
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// md5_digest_table 0c453d200f282e320677c1ac46786658
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -143,8 +143,8 @@ static const esp_efuse_desc_t WR_DIS_XTS_DPA_CLK_ENABLE[] = {
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{EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_CLK_ENABLE,
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};
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static const esp_efuse_desc_t WR_DIS_ECDSA_DISABLE_P192[] = {
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{EFUSE_BLK0, 14, 1}, // [] wr_dis of ECDSA_DISABLE_P192,
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static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_SHA384_EN[] = {
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{EFUSE_BLK0, 14, 1}, // [] wr_dis of SECURE_BOOT_SHA384_EN,
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};
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static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = {
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@ -315,6 +315,14 @@ static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of LP_HP_DBIAS_VOL_GAP,
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};
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static const esp_efuse_desc_t WR_DIS_REF_CURR_CODE[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of REF_CURR_CODE,
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};
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static const esp_efuse_desc_t WR_DIS_RES_TUNE_CODE[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of RES_TUNE_CODE,
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};
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static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
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};
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@ -463,156 +471,176 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
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{EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
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};
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static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI[] = {
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{EFUSE_BLK0, 39, 1}, // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader (the high part of the field),
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};
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static const esp_efuse_desc_t DIS_ICACHE[] = {
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{EFUSE_BLK0, 40, 1}, // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 40, 1}, // [] Represents whether cache is disabled. 1: Disabled 0: Enabled,
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};
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static const esp_efuse_desc_t DIS_USB_JTAG[] = {
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{EFUSE_BLK0, 41, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 41, 1}, // [] Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is configured to 0. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.1: Disabled0: Enabled,
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};
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static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_EN[] = {
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{EFUSE_BLK0, 42, 1}, // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled,
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};
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static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
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{EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into Download mode is disabled. 1: Disabled0: Enabled,
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};
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static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = {
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{EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot\_mode\_download is disabled.0: Enabled1: Disabled,
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};
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static const esp_efuse_desc_t DIS_TWAI[] = {
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{EFUSE_BLK0, 46, 1}, // [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 46, 1}, // [] Represents whether TWAI$^®$ function is disabled.1: Disabled0: Enabled,
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};
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static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
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{EFUSE_BLK0, 47, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled,
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{EFUSE_BLK0, 47, 1}, // [] Represents whether the selection of a JTAG signal source through the strapping pin value is enabled when all of \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}; \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are configured to 0. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.1: Enabled0: Disabled,
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};
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static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
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{EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled,
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{EFUSE_BLK0, 48, 3}, // [] Represents whether PAD JTAG is disabled in the soft way. It can be restarted via HMAC. Odd count of bits with a value of 1: DisabledEven count of bits with a value of 1: Enabled,
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};
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static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
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{EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 51, 1}, // [] Represents whether PAD JTAG is disabled in the hard way (permanently).1: Disabled0: Enabled,
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};
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static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
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{EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 52, 1}, // [] Represents whether flash encryption is disabled (except in SPI boot mode).1: Disabled0: Enabled,
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};
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static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
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{EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged,
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{EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged.1: Exchanged0: Not exchanged,
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};
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static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = {
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{EFUSE_BLK0, 58, 1}, // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned,
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};
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static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = {
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{EFUSE_BLK0, 64, 4}, // [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled.,
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};
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static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = {
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{EFUSE_BLK0, 68, 2}, // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles,
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};
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static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = {
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{EFUSE_BLK0, 70, 4}, // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds,
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};
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static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = {
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{EFUSE_BLK0, 74, 4}, // [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds,
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};
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static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = {
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{EFUSE_BLK0, 78, 1}, // [] Set this bit to disable software written init key; and force use efuse_init_key,
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{EFUSE_BLK0, 58, 1}, // [] Represents whether VDD SPI pin is functioned as GPIO.1: Functioned0: Not functioned,
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};
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static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
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{EFUSE_BLK0, 80, 2}, // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16,
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{EFUSE_BLK0, 59, 2}, // [] Represents RTC watchdog timeout threshold.0: The originally configured STG0 threshold × 21: The originally configured STG0 threshold × 42: The originally configured STG0 threshold × 83: The originally configured STG0 threshold × 16,
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};
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static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO[] = {
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{EFUSE_BLK0, 61, 3}, // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader (the low part of the field),
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};
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static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = {
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{EFUSE_BLK0, 64, 4}, // [] Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled,
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};
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static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = {
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{EFUSE_BLK0, 68, 2}, // [] Represents the cycle at which the Key Manager switches random numbers.0: Controlled by the \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For more information; please refer to Chapter \ref{mod:keymng} \textit{\nameref{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Key Manager clock cycles3: 32 Key Manager clock cycles,
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};
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static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = {
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{EFUSE_BLK0, 70, 4}, // [] Represents whether the corresponding key can be deployed only once.Bit0: Represents whether the ECDSA key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit2: Represents whether the HMAC key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit3: Represents whether the DS key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only once,
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};
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static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = {
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{EFUSE_BLK0, 74, 4}, // [] Represents whether the corresponding key must come from Key Manager. Bit0: Represents whether the ECDSA key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit2: Represents whether the HMAC key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit3: Represents whether the DS key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key Manager,
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};
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static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = {
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{EFUSE_BLK0, 78, 1}, // [] Represents whether to disable the use of the initialization key written by software and instead force use efuse\_init\_key.0: Enable1: Disable,
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};
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static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = {
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{EFUSE_BLK0, 79, 1}, // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable,
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};
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static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
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{EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
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{EFUSE_BLK0, 80, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
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};
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static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
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{EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key,
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{EFUSE_BLK0, 83, 1}, // [] Revoke 1st secure boot key,
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};
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static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
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{EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key,
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{EFUSE_BLK0, 84, 1}, // [] Revoke 2nd secure boot key,
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};
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static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
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{EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key,
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{EFUSE_BLK0, 85, 1}, // [] Revoke 3rd secure boot key,
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};
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static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
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{EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Represents the purpose of Key0,
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{EFUSE_BLK0, 86, 5}, // [KEY0_PURPOSE] Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose},
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};
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static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
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{EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Represents the purpose of Key1,
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{EFUSE_BLK0, 91, 5}, // [KEY1_PURPOSE] Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose},
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};
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static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
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{EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Represents the purpose of Key2,
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{EFUSE_BLK0, 96, 5}, // [KEY2_PURPOSE] Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose},
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};
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static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
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{EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Represents the purpose of Key3,
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{EFUSE_BLK0, 101, 5}, // [KEY3_PURPOSE] Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose},
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};
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static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
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{EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Represents the purpose of Key4,
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{EFUSE_BLK0, 106, 5}, // [KEY4_PURPOSE] Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose},
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};
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static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
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{EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Represents the purpose of Key5,
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{EFUSE_BLK0, 111, 5}, // [KEY5_PURPOSE] Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose},
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};
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static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
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{EFUSE_BLK0, 112, 2}, // [] Represents the spa secure level by configuring the clock random divide mode,
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{EFUSE_BLK0, 116, 2}, // [] Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode.0: Security level is SEC\_DPA\_OFF1: Security level is SEC\_DPA\_LOW2: Security level is SEC\_DPA\_MIDDLE3: Security level is SEC\_DPA\_HIGHFor more information; please refer to Chapter \ref{mod:sysreg} \textit{\nameref{mod:sysreg}} > Section \ref{sec:sysreg-anti-dpa-attack-security-control} \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}.,
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};
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static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_HI[] = {
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{EFUSE_BLK0, 118, 3}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The high part of the field),
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};
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static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
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{EFUSE_BLK0, 116, 1}, // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled,
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{EFUSE_BLK0, 121, 1}, // [] Represents whether Secure Boot is enabled.1: Enabled0: Disabled,
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};
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static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
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{EFUSE_BLK0, 117, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled,
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{EFUSE_BLK0, 122, 1}, // [] Represents whether aggressive revocation of Secure Boot is enabled.1: Enabled0: Disabled,
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};
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static const esp_efuse_desc_t KM_XTS_KEY_LENGTH_256[] = {
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{EFUSE_BLK0, 123, 1}, // [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key,
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{EFUSE_BLK0, 123, 1}, // [] Represents which key flash encryption uses.0: XTS-AES-256 key1: XTS-AES-128 key,
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};
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static const esp_efuse_desc_t FLASH_TPUW[] = {
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{EFUSE_BLK0, 124, 4}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value,
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{EFUSE_BLK0, 124, 4}, // [] Represents the flash waiting time after power-up. Measurement unit: ms. When the value is less than 15; the waiting time is the programmed value. Otherwise; the waiting time is a fixed value; i.e. 30 ms,
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};
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static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
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{EFUSE_BLK0, 128, 1}, // [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 128, 1}, // [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable,
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};
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static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
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{EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable,
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};
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static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
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{EFUSE_BLK0, 130, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled,
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{EFUSE_BLK0, 130, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable,
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};
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static const esp_efuse_desc_t LOCK_KM_KEY[] = {
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{EFUSE_BLK0, 131, 1}, // [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock,
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{EFUSE_BLK0, 131, 1}, // [] Represents whether the keys in the Key Manager are locked after deployment.0: Not locked1: Locked,
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};
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static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
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{EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable,
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{EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable,
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};
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static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
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{EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled,
|
||||
{EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled. Only downloading into flash is supported. Reading/writing RAM or registers is not supported (i.e. stub download is not supported).1: Enabled0: Disabled,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
|
||||
@ -620,31 +648,35 @@ static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
|
||||
{EFUSE_BLK0, 136, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced,
|
||||
{EFUSE_BLK0, 136, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot.1: Forced. 0: Not forced.,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t SECURE_VERSION[] = {
|
||||
{EFUSE_BLK0, 137, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature,
|
||||
{EFUSE_BLK0, 137, 9}, // [] Represents the app secure version used by ESP-IDF anti-rollback feature,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
|
||||
{EFUSE_BLK0, 153, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled,
|
||||
{EFUSE_BLK0, 153, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled.1: Disabled0: Enabled,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t HYS_EN_PAD[] = {
|
||||
{EFUSE_BLK0, 154, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled,
|
||||
{EFUSE_BLK0, 154, 1}, // [] Represents whether the hysteresis function of PAD0 – PAD27 is enabled.1: Enabled0: Disabled,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = {
|
||||
{EFUSE_BLK0, 155, 2}, // [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled,
|
||||
{EFUSE_BLK0, 155, 2}, // [] Represents the pseudo round level of XTS-AES anti-DPA attack.0: Disabled1: Low2: Moderate3: High,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = {
|
||||
{EFUSE_BLK0, 157, 1}, // [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable.,
|
||||
{EFUSE_BLK0, 157, 1}, // [] Represents whether XTS-AES anti-DPA attack clock is enabled.0: Disable1: Enabled,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t SECURE_BOOT_SHA384_EN[] = {
|
||||
{EFUSE_BLK0, 159, 1}, // [] Represents if the chip supports Secure Boot using SHA-384,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t HUK_GEN_STATE[] = {
|
||||
{EFUSE_BLK0, 160, 9}, // [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid.,
|
||||
{EFUSE_BLK0, 160, 9}, // [] Represents whether the HUK generate mode is valid.Odd count of bits with a value of 1: InvalidEven count of bits with a value of 1: Valid,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t XTAL_48M_SEL[] = {
|
||||
@ -652,15 +684,15 @@ static const esp_efuse_desc_t XTAL_48M_SEL[] = {
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t XTAL_48M_SEL_MODE[] = {
|
||||
{EFUSE_BLK0, 172, 1}, // [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ECDSA_DISABLE_P192[] = {
|
||||
{EFUSE_BLK0, 173, 1}, // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable,
|
||||
{EFUSE_BLK0, 172, 1}, // [] Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.0: Strapping PAD state1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = {
|
||||
{EFUSE_BLK0, 174, 1}, // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable,
|
||||
{EFUSE_BLK0, 173, 1}, // [] Represents whether to force ECC to use constant-time mode for point multiplication calculation. 0: Not force1: Force,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_LO[] = {
|
||||
{EFUSE_BLK0, 174, 9}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The low part of the field),
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t MAC[] = {
|
||||
@ -764,6 +796,14 @@ static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = {
|
||||
{EFUSE_BLK1, 129, 5}, // [] DBIAS gap between LP and HP,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t REF_CURR_CODE[] = {
|
||||
{EFUSE_BLK1, 134, 4}, // [] REF PADC Calibration Curr,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t RES_TUNE_CODE[] = {
|
||||
{EFUSE_BLK1, 138, 5}, // [] RES PADC Calibration Tune,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
|
||||
{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
|
||||
};
|
||||
@ -1032,8 +1072,8 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[] = {
|
||||
&WR_DIS_ECDSA_DISABLE_P192[0], // [] wr_dis of ECDSA_DISABLE_P192
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN[] = {
|
||||
&WR_DIS_SECURE_BOOT_SHA384_EN[0], // [] wr_dis of SECURE_BOOT_SHA384_EN
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -1247,6 +1287,16 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_REF_CURR_CODE[] = {
|
||||
&WR_DIS_REF_CURR_CODE[0], // [] wr_dis of REF_CURR_CODE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RES_TUNE_CODE[] = {
|
||||
&WR_DIS_RES_TUNE_CODE[0], // [] wr_dis of RES_TUNE_CODE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
|
||||
&WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
NULL
|
||||
@ -1432,88 +1482,108 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI[] = {
|
||||
&BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI[0], // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader (the high part of the field)
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
|
||||
&DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled
|
||||
&DIS_ICACHE[0], // [] Represents whether cache is disabled. 1: Disabled 0: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
|
||||
&DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled
|
||||
&DIS_USB_JTAG[0], // [] Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is configured to 0. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.1: Disabled0: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[] = {
|
||||
&BOOTLOADER_ANTI_ROLLBACK_EN[0], // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
|
||||
&DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled
|
||||
&DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into Download mode is disabled. 1: Disabled0: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = {
|
||||
&SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled
|
||||
&SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot\_mode\_download is disabled.0: Enabled1: Disabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
|
||||
&DIS_TWAI[0], // [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled
|
||||
&DIS_TWAI[0], // [] Represents whether TWAI$^®$ function is disabled.1: Disabled0: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
|
||||
&JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled
|
||||
&JTAG_SEL_ENABLE[0], // [] Represents whether the selection of a JTAG signal source through the strapping pin value is enabled when all of \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}; \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are configured to 0. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.1: Enabled0: Disabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
|
||||
&SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled
|
||||
&SOFT_DIS_JTAG[0], // [] Represents whether PAD JTAG is disabled in the soft way. It can be restarted via HMAC. Odd count of bits with a value of 1: DisabledEven count of bits with a value of 1: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
|
||||
&DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled
|
||||
&DIS_PAD_JTAG[0], // [] Represents whether PAD JTAG is disabled in the hard way (permanently).1: Disabled0: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
|
||||
&DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled
|
||||
&DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encryption is disabled (except in SPI boot mode).1: Disabled0: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
|
||||
&USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged
|
||||
&USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged.1: Exchanged0: Not exchanged
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
|
||||
&VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = {
|
||||
&KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled.
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = {
|
||||
&KM_RND_SWITCH_CYCLE[0], // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = {
|
||||
&KM_DEPLOY_ONLY_ONCE[0], // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = {
|
||||
&FORCE_USE_KEY_MANAGER_KEY[0], // [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = {
|
||||
&FORCE_DISABLE_SW_INIT_KEY[0], // [] Set this bit to disable software written init key; and force use efuse_init_key
|
||||
&VDD_SPI_AS_GPIO[0], // [] Represents whether VDD SPI pin is functioned as GPIO.1: Functioned0: Not functioned
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
|
||||
&WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16
|
||||
&WDT_DELAY_SEL[0], // [] Represents RTC watchdog timeout threshold.0: The originally configured STG0 threshold × 21: The originally configured STG0 threshold × 42: The originally configured STG0 threshold × 83: The originally configured STG0 threshold × 16
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO[] = {
|
||||
&BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO[0], // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader (the low part of the field)
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = {
|
||||
&KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = {
|
||||
&KM_RND_SWITCH_CYCLE[0], // [] Represents the cycle at which the Key Manager switches random numbers.0: Controlled by the \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For more information; please refer to Chapter \ref{mod:keymng} \textit{\nameref{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Key Manager clock cycles3: 32 Key Manager clock cycles
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = {
|
||||
&KM_DEPLOY_ONLY_ONCE[0], // [] Represents whether the corresponding key can be deployed only once.Bit0: Represents whether the ECDSA key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit2: Represents whether the HMAC key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit3: Represents whether the DS key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only once
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = {
|
||||
&FORCE_USE_KEY_MANAGER_KEY[0], // [] Represents whether the corresponding key must come from Key Manager. Bit0: Represents whether the ECDSA key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit2: Represents whether the HMAC key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit3: Represents whether the DS key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key Manager
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = {
|
||||
&FORCE_DISABLE_SW_INIT_KEY[0], // [] Represents whether to disable the use of the initialization key written by software and instead force use efuse\_init\_key.0: Enable1: Disable
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = {
|
||||
&BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[0], // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -1538,87 +1608,92 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
|
||||
&KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Represents the purpose of Key0
|
||||
&KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose}
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
|
||||
&KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Represents the purpose of Key1
|
||||
&KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose}
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
|
||||
&KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Represents the purpose of Key2
|
||||
&KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose}
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
|
||||
&KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Represents the purpose of Key3
|
||||
&KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose}
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
|
||||
&KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Represents the purpose of Key4
|
||||
&KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose}
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
|
||||
&KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Represents the purpose of Key5
|
||||
&KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose}
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
|
||||
&SEC_DPA_LEVEL[0], // [] Represents the spa secure level by configuring the clock random divide mode
|
||||
&SEC_DPA_LEVEL[0], // [] Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode.0: Security level is SEC\_DPA\_OFF1: Security level is SEC\_DPA\_LOW2: Security level is SEC\_DPA\_MIDDLE3: Security level is SEC\_DPA\_HIGHFor more information; please refer to Chapter \ref{mod:sysreg} \textit{\nameref{mod:sysreg}} > Section \ref{sec:sysreg-anti-dpa-attack-security-control} \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}.
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI[] = {
|
||||
&RECOVERY_BOOTLOADER_FLASH_SECTOR_HI[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The high part of the field)
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
|
||||
&SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled
|
||||
&SECURE_BOOT_EN[0], // [] Represents whether Secure Boot is enabled.1: Enabled0: Disabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
|
||||
&SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled
|
||||
&SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether aggressive revocation of Secure Boot is enabled.1: Enabled0: Disabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[] = {
|
||||
&KM_XTS_KEY_LENGTH_256[0], // [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key
|
||||
&KM_XTS_KEY_LENGTH_256[0], // [] Represents which key flash encryption uses.0: XTS-AES-256 key1: XTS-AES-128 key
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
|
||||
&FLASH_TPUW[0], // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
|
||||
&FLASH_TPUW[0], // [] Represents the flash waiting time after power-up. Measurement unit: ms. When the value is less than 15; the waiting time is the programmed value. Otherwise; the waiting time is a fixed value; i.e. 30 ms
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
|
||||
&DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled
|
||||
&DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
|
||||
&DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled
|
||||
&DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
|
||||
&DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled
|
||||
&DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = {
|
||||
&LOCK_KM_KEY[0], // [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock
|
||||
&LOCK_KM_KEY[0], // [] Represents whether the keys in the Key Manager are locked after deployment.0: Not locked1: Locked
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
|
||||
&DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable
|
||||
&DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
|
||||
&ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled
|
||||
&ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled. Only downloading into flash is supported. Reading/writing RAM or registers is not supported (i.e. stub download is not supported).1: Enabled0: Disabled
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -1628,37 +1703,42 @@ const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
|
||||
&FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced
|
||||
&FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot.1: Forced. 0: Not forced.
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
|
||||
&SECURE_VERSION[0], // [] Represents the version used by ESP-IDF anti-rollback feature
|
||||
&SECURE_VERSION[0], // [] Represents the app secure version used by ESP-IDF anti-rollback feature
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
|
||||
&SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled
|
||||
&SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled.1: Disabled0: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = {
|
||||
&HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled
|
||||
&HYS_EN_PAD[0], // [] Represents whether the hysteresis function of PAD0 – PAD27 is enabled.1: Enabled0: Disabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = {
|
||||
&XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled
|
||||
&XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the pseudo round level of XTS-AES anti-DPA attack.0: Disabled1: Low2: Moderate3: High
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = {
|
||||
&XTS_DPA_CLK_ENABLE[0], // [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable.
|
||||
&XTS_DPA_CLK_ENABLE[0], // [] Represents whether XTS-AES anti-DPA attack clock is enabled.0: Disable1: Enabled
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[] = {
|
||||
&SECURE_BOOT_SHA384_EN[0], // [] Represents if the chip supports Secure Boot using SHA-384
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[] = {
|
||||
&HUK_GEN_STATE[0], // [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid.
|
||||
&HUK_GEN_STATE[0], // [] Represents whether the HUK generate mode is valid.Odd count of bits with a value of 1: InvalidEven count of bits with a value of 1: Valid
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -1668,17 +1748,17 @@ const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL[] = {
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL_MODE[] = {
|
||||
&XTAL_48M_SEL_MODE[0], // [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[] = {
|
||||
&ECDSA_DISABLE_P192[0], // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable
|
||||
&XTAL_48M_SEL_MODE[0], // [] Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.0: Strapping PAD state1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = {
|
||||
&ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable
|
||||
&ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ECC to use constant-time mode for point multiplication calculation. 0: Not force1: Force
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO[] = {
|
||||
&RECOVERY_BOOTLOADER_FLASH_SECTOR_LO[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The low part of the field)
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -1807,6 +1887,16 @@ const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_REF_CURR_CODE[] = {
|
||||
&REF_CURR_CODE[0], // [] REF PADC Calibration Curr
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_RES_TUNE_CODE[] = {
|
||||
&RES_TUNE_CODE[0], // [] RES PADC Calibration Tune
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
|
||||
&OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
|
||||
NULL
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 287a0ed4951aba84b9571a5f31000275
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 31c7fe3f5f4e0a55b178a57126c0aca7
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
@ -43,7 +43,7 @@ WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.K
|
||||
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
|
||||
WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
|
||||
WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
|
||||
WR_DIS.ECDSA_DISABLE_P192, EFUSE_BLK0, 14, 1, [] wr_dis of ECDSA_DISABLE_P192
|
||||
WR_DIS.SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 14, 1, [] wr_dis of SECURE_BOOT_SHA384_EN
|
||||
WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
@ -86,6 +86,8 @@ WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis
|
||||
WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG
|
||||
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
|
||||
WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP
|
||||
WR_DIS.REF_CURR_CODE, EFUSE_BLK0, 20, 1, [] wr_dis of REF_CURR_CODE
|
||||
WR_DIS.RES_TUNE_CODE, EFUSE_BLK0, 20, 1, [] wr_dis of RES_TUNE_CODE
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||
@ -123,56 +125,62 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K
|
||||
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
|
||||
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
|
||||
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled\\
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\
|
||||
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\
|
||||
KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 64, 4, [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled.\\
|
||||
KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 68, 2, [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
|
||||
KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 70, 4, [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds
|
||||
FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 74, 4, [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds
|
||||
FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 78, 1, [] Set this bit to disable software written init key; and force use efuse_init_key
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5
|
||||
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the spa secure level by configuring the clock random divide mode
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\
|
||||
KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 123, 1, [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
LOCK_KM_KEY, EFUSE_BLK0, 131, 1, [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
|
||||
BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI, EFUSE_BLK0, 39, 1, [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader (the high part of the field)
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether cache is disabled. 1: Disabled 0: Enabled
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is configured to 0. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.1: Disabled0: Enabled
|
||||
BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 42, 1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into Download mode is disabled. 1: Disabled0: Enabled
|
||||
SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot\_mode\_download is disabled.0: Enabled1: Disabled
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, [] Represents whether TWAI$^®$ function is disabled.1: Disabled0: Enabled
|
||||
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection of a JTAG signal source through the strapping pin value is enabled when all of \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}; \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are configured to 0. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.1: Enabled0: Disabled
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether PAD JTAG is disabled in the soft way. It can be restarted via HMAC. Odd count of bits with a value of 1: DisabledEven count of bits with a value of 1: Enabled
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether PAD JTAG is disabled in the hard way (permanently).1: Disabled0: Enabled
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encryption is disabled (except in SPI boot mode).1: Disabled0: Enabled
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged.1: Exchanged0: Not exchanged
|
||||
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether VDD SPI pin is functioned as GPIO.1: Functioned0: Not functioned
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 59, 2, [] Represents RTC watchdog timeout threshold.0: The originally configured STG0 threshold × 21: The originally configured STG0 threshold × 42: The originally configured STG0 threshold × 83: The originally configured STG0 threshold × 16
|
||||
BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO, EFUSE_BLK0, 61, 3, [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader (the low part of the field)
|
||||
KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 64, 4, [] Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled
|
||||
KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 68, 2, [] Represents the cycle at which the Key Manager switches random numbers.0: Controlled by the \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For more information; please refer to Chapter \ref{mod:keymng} \textit{\nameref{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Key Manager clock cycles3: 32 Key Manager clock cycles
|
||||
KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 70, 4, [] Represents whether the corresponding key can be deployed only once.Bit0: Represents whether the ECDSA key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit2: Represents whether the HMAC key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit3: Represents whether the DS key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only once
|
||||
FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 74, 4, [] Represents whether the corresponding key must come from Key Manager. Bit0: Represents whether the ECDSA key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit2: Represents whether the HMAC key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit3: Represents whether the DS key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key Manager
|
||||
FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 78, 1, [] Represents whether to disable the use of the initialization key written by software and instead force use efuse\_init\_key.0: Enable1: Disable
|
||||
BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 79, 1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 80, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 83, 1, [] Revoke 1st secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 84, 1, [] Revoke 2nd secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 85, 1, [] Revoke 3rd secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 86, 5, [KEY0_PURPOSE] Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose}
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 91, 5, [KEY1_PURPOSE] Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose}
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 5, [KEY2_PURPOSE] Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose}
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 101, 5, [KEY3_PURPOSE] Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose}
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 106, 5, [KEY4_PURPOSE] Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose}
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 111, 5, [KEY5_PURPOSE] Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose}
|
||||
SEC_DPA_LEVEL, EFUSE_BLK0, 116, 2, [] Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode.0: Security level is SEC\_DPA\_OFF1: Security level is SEC\_DPA\_LOW2: Security level is SEC\_DPA\_MIDDLE3: Security level is SEC\_DPA\_HIGHFor more information; please refer to Chapter \ref{mod:sysreg} \textit{\nameref{mod:sysreg}} > Section \ref{sec:sysreg-anti-dpa-attack-security-control} \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}.
|
||||
RECOVERY_BOOTLOADER_FLASH_SECTOR_HI, EFUSE_BLK0, 118, 3, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The high part of the field)
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 121, 1, [] Represents whether Secure Boot is enabled.1: Enabled0: Disabled
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 122, 1, [] Represents whether aggressive revocation of Secure Boot is enabled.1: Enabled0: Disabled
|
||||
KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 123, 1, [] Represents which key flash encryption uses.0: XTS-AES-256 key1: XTS-AES-128 key
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up. Measurement unit: ms. When the value is less than 15; the waiting time is the programmed value. Otherwise; the waiting time is a fixed value; i.e. 30 ms
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable
|
||||
LOCK_KM_KEY, EFUSE_BLK0, 131, 1, [] Represents whether the keys in the Key Manager are locked after deployment.0: Not locked1: Locked
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled. Only downloading into flash is supported. Reading/writing RAM or registers is not supported (i.e. stub download is not supported).1: Enabled0: Disabled
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced\\
|
||||
SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Represents the version used by ESP-IDF anti-rollback feature
|
||||
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled\\
|
||||
HYS_EN_PAD, EFUSE_BLK0, 154, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\
|
||||
XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 155, 2, [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled\\
|
||||
XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 157, 1, [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable.\\
|
||||
HUK_GEN_STATE, EFUSE_BLK0, 160, 9, [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid.\\
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot.1: Forced. 0: Not forced.
|
||||
SECURE_VERSION, EFUSE_BLK0, 137, 9, [] Represents the app secure version used by ESP-IDF anti-rollback feature
|
||||
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled.1: Disabled0: Enabled
|
||||
HYS_EN_PAD, EFUSE_BLK0, 154, 1, [] Represents whether the hysteresis function of PAD0 – PAD27 is enabled.1: Enabled0: Disabled
|
||||
XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 155, 2, [] Represents the pseudo round level of XTS-AES anti-DPA attack.0: Disabled1: Low2: Moderate3: High
|
||||
XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 157, 1, [] Represents whether XTS-AES anti-DPA attack clock is enabled.0: Disable1: Enabled
|
||||
SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 159, 1, [] Represents if the chip supports Secure Boot using SHA-384
|
||||
HUK_GEN_STATE, EFUSE_BLK0, 160, 9, [] Represents whether the HUK generate mode is valid.Odd count of bits with a value of 1: InvalidEven count of bits with a value of 1: Valid
|
||||
XTAL_48M_SEL, EFUSE_BLK0, 169, 3, [] Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL
|
||||
XTAL_48M_SEL_MODE, EFUSE_BLK0, 172, 1, [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state
|
||||
ECDSA_DISABLE_P192, EFUSE_BLK0, 173, 1, [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable
|
||||
ECC_FORCE_CONST_TIME, EFUSE_BLK0, 174, 1, [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable
|
||||
XTAL_48M_SEL_MODE, EFUSE_BLK0, 172, 1, [] Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.0: Strapping PAD state1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse
|
||||
ECC_FORCE_CONST_TIME, EFUSE_BLK0, 173, 1, [] Represents whether to force ECC to use constant-time mode for point multiplication calculation. 0: Not force1: Force
|
||||
RECOVERY_BOOTLOADER_FLASH_SECTOR_LO, EFUSE_BLK0, 174, 9, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The low part of the field)
|
||||
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
|
||||
@ -202,6 +210,8 @@ LSLP_HP_DBIAS, EFUSE_BLK1, 116, 4, [] LSLP H
|
||||
DSLP_LP_DBG, EFUSE_BLK1, 120, 4, [] DSLP LP DBG of fixed voltage
|
||||
DSLP_LP_DBIAS, EFUSE_BLK1, 124, 5, [] DSLP LP DBIAS of fixed voltage
|
||||
LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 129, 5, [] DBIAS gap between LP and HP
|
||||
REF_CURR_CODE, EFUSE_BLK1, 134, 4, [] REF PADC Calibration Curr
|
||||
RES_TUNE_CODE, EFUSE_BLK1, 138, 5, [] RES PADC Calibration Tune
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -62,7 +62,10 @@ typedef enum {
|
||||
*/
|
||||
typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (P256) (Expected in little endian order)*/
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, /**< XTS_AES_256_KEY_1 (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, /**< XTS_AES_256_KEY_2 (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
|
||||
@ -71,6 +74,13 @@ typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY (Key Manager initialization key) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13, /**< XTS_AES_256_PSRAM_KEY_1 (PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14, /**< XTS_AES_256_PSRAM_KEY_2 (PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15, /**< XTS_AES_128_PSRAM_KEY (PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 = 16, /**< ECDSA private key (P192) */
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L = 17, /**< ECDSA private key (P384) */
|
||||
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H = 18, /**< ECDSA private key (P384) */
|
||||
ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */
|
||||
} esp_efuse_purpose_t;
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table b26e7466c400977081a142076ef1a5bb
|
||||
// md5_digest_table 0c453d200f282e320677c1ac46786658
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -55,7 +55,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
@ -99,6 +99,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_REF_CURR_CODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RES_TUNE_CODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
@ -153,8 +155,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
@ -164,12 +168,14 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
@ -187,6 +193,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[];
|
||||
@ -204,11 +211,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
|
||||
@ -234,6 +242,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_REF_CURR_CODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RES_TUNE_CODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -308,6 +308,20 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
|
||||
#if SOC_EFUSE_ECDSA_KEY
|
||||
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
|
||||
#endif
|
||||
#if SOC_EFUSE_ECDSA_KEY_P192
|
||||
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
|
||||
#endif
|
||||
#if SOC_EFUSE_ECDSA_KEY_P384
|
||||
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
|
||||
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
|
||||
#endif
|
||||
#if SOC_PSRAM_ENCRYPTION_XTS_AES_128
|
||||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
|
||||
#endif
|
||||
#if SOC_PSRAM_ENCRYPTION_XTS_AES_256
|
||||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
|
||||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
|
||||
#endif
|
||||
#if SOC_KEY_MANAGER_SUPPORTED
|
||||
purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY ||
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -11,6 +11,8 @@
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#define FLASH_SECTOR_SIZE (4096)
|
||||
|
||||
|
||||
void efuse_hal_get_mac(uint8_t *mac)
|
||||
{
|
||||
@ -66,3 +68,20 @@ void efuse_hal_set_ecdsa_key(ecdsa_curve_t curve, int efuse_blk)
|
||||
efuse_hal_read();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if SOC_RECOVERY_BOOTLOADER_SUPPORTED
|
||||
uint32_t efuse_hal_get_recovery_bootloader_address(void)
|
||||
{
|
||||
return efuse_ll_get_recovery_bootloader_sector() * FLASH_SECTOR_SIZE;
|
||||
}
|
||||
|
||||
uint32_t efuse_hal_convert_recovery_bootloader_address_to_flash_sectors(uint32_t address)
|
||||
{
|
||||
return address / FLASH_SECTOR_SIZE;
|
||||
}
|
||||
|
||||
bool efuse_hal_recovery_bootloader_enabled(void)
|
||||
{
|
||||
return EFUSE_RECOVERY_BOOTLOADER_ENABLED(efuse_ll_get_recovery_bootloader_sector());
|
||||
}
|
||||
#endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED
|
||||
|
||||
@ -149,6 +149,11 @@ __attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(
|
||||
return EFUSE.rd_mac_sys4.lp_hp_dbias_vol_gap;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_recovery_bootloader_sector(void)
|
||||
{
|
||||
return (EFUSE.rd_repeat_data2.recovery_bootloader_flash_sector_hi << 9) | EFUSE.rd_repeat_data4.recovery_bootloader_flash_sector_lo;
|
||||
}
|
||||
|
||||
/******************* eFuse control functions *************************/
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -87,6 +87,37 @@ uint32_t efuse_hal_get_chip_ver_pkg(void);
|
||||
void efuse_hal_set_ecdsa_key(ecdsa_curve_t curve, int efuse_key_blk);
|
||||
#endif
|
||||
|
||||
#if SOC_RECOVERY_BOOTLOADER_SUPPORTED
|
||||
|
||||
#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LEN (12)
|
||||
#define EFUSE_RECOVERY_BOOTLOADER_ENABLED(sector) ((sector) != 0 && (sector) != ((1 << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LEN) - 1))
|
||||
|
||||
/**
|
||||
* @brief Returns recovery bootloader flash address
|
||||
*
|
||||
* @return Recovery bootloader flash address.
|
||||
*/
|
||||
uint32_t efuse_hal_get_recovery_bootloader_address(void);
|
||||
|
||||
/**
|
||||
* @brief Converts a recovery bootloader address to the corresponding flash sector.
|
||||
*
|
||||
* This function translates a recovery bootloader address in bytes
|
||||
* into the equivalent flash sector number.
|
||||
*
|
||||
* @param address The recovery bootloader address in bytes.
|
||||
* @return The flash sector number corresponding to the given address.
|
||||
*/
|
||||
uint32_t efuse_hal_convert_recovery_bootloader_address_to_flash_sectors(uint32_t address);
|
||||
|
||||
/**
|
||||
* @brief Returns true if recovery bootloader address is configured
|
||||
*
|
||||
* @return True - Recovery bootloader address is configured.
|
||||
*/
|
||||
bool efuse_hal_recovery_bootloader_enabled(void);
|
||||
#endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1323,10 +1323,38 @@ config SOC_TWAI_SUPPORT_TIMESTAMP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_PAD_JTAG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_USB_JTAG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_DIRECT_BOOT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_SOFT_DIS_JTAG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_ICACHE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_ECDSA_KEY
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_ECDSA_KEY_P192
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_ECDSA_KEY_P384
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
|
||||
bool
|
||||
default y
|
||||
@ -1367,10 +1395,30 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES_256
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PSRAM_ENCRYPTION_XTS_AES_128
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PSRAM_ENCRYPTION_XTS_AES_256
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RECOVERY_BOOTLOADER_SUPPORTED
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_APM_CTRL_FILTER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -519,13 +519,15 @@
|
||||
#define SOC_TWAI_SUPPORT_TIMESTAMP 1
|
||||
|
||||
/*-------------------------- eFuse CAPS----------------------------*/
|
||||
// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
|
||||
// #define SOC_EFUSE_DIS_PAD_JTAG 1
|
||||
// #define SOC_EFUSE_DIS_USB_JTAG 1
|
||||
// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
|
||||
// #define SOC_EFUSE_SOFT_DIS_JTAG 1
|
||||
// #define SOC_EFUSE_DIS_ICACHE 1
|
||||
#define SOC_EFUSE_DIS_PAD_JTAG 1
|
||||
#define SOC_EFUSE_DIS_USB_JTAG 1
|
||||
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
|
||||
#define SOC_EFUSE_SOFT_DIS_JTAG 1
|
||||
#define SOC_EFUSE_DIS_ICACHE 1
|
||||
// ECDSA_P256_KEY
|
||||
#define SOC_EFUSE_ECDSA_KEY 1
|
||||
#define SOC_EFUSE_ECDSA_KEY_P192 1
|
||||
#define SOC_EFUSE_ECDSA_KEY_P384 1
|
||||
|
||||
/*-------------------------- Key Manager CAPS----------------------------*/
|
||||
#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */
|
||||
@ -542,8 +544,19 @@
|
||||
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND 1
|
||||
|
||||
/*-------------------------- PSRAM Encryption CAPS----------------------------*/
|
||||
#define SOC_PSRAM_ENCRYPTION_XTS_AES_128 (1)
|
||||
#define SOC_PSRAM_ENCRYPTION_XTS_AES_256 (1)
|
||||
|
||||
/*------------------------Bootloader CAPS---------------------------------*/
|
||||
/* Support Recovery Bootloader */
|
||||
#define SOC_RECOVERY_BOOTLOADER_SUPPORTED (0)
|
||||
/* Support Anti-rollback */
|
||||
#define SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED (0)
|
||||
|
||||
/*-------------------------- APM CAPS-----------------------------------------*/
|
||||
#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */
|
||||
#define SOC_APM_LP_APM0_SUPPORTED 1 /*!< Support for LP APM0 control filter */
|
||||
|
||||
@ -674,6 +674,13 @@ extern "C" {
|
||||
#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
|
||||
#define EFUSE_SECURE_VERSION_V 0x000001FFU
|
||||
#define EFUSE_SECURE_VERSION_S 9
|
||||
/** EFUSE_RD_RESERVE_0_146 : RW; bitpos: [24:18]; default: 0;
|
||||
* Reserved, it was created by set_missed_fields_in_regs func
|
||||
*/
|
||||
#define EFUSE_RD_RESERVE_0_146 0x0000007FU
|
||||
#define EFUSE_RD_RESERVE_0_146_M (EFUSE_RD_RESERVE_0_146_V << EFUSE_RD_RESERVE_0_146_S)
|
||||
#define EFUSE_RD_RESERVE_0_146_V 0x0000007FU
|
||||
#define EFUSE_RD_RESERVE_0_146_S 18
|
||||
/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
|
||||
* Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled.
|
||||
* 1: Disabled
|
||||
@ -712,13 +719,20 @@ extern "C" {
|
||||
#define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S)
|
||||
#define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U
|
||||
#define EFUSE_XTS_DPA_CLK_ENABLE_S 29
|
||||
/** EFUSE_ECDSA_P384_ENABLE : RO; bitpos: [31]; default: 0;
|
||||
* Represents if the chip supports ECDSA P384
|
||||
/** EFUSE_RD_RESERVE_0_158 : RW; bitpos: [30]; default: 0;
|
||||
* Reserved, it was created by set_missed_fields_in_regs func
|
||||
*/
|
||||
#define EFUSE_ECDSA_P384_ENABLE (BIT(31))
|
||||
#define EFUSE_ECDSA_P384_ENABLE_M (EFUSE_ECDSA_P384_ENABLE_V << EFUSE_ECDSA_P384_ENABLE_S)
|
||||
#define EFUSE_ECDSA_P384_ENABLE_V 0x00000001U
|
||||
#define EFUSE_ECDSA_P384_ENABLE_S 31
|
||||
#define EFUSE_RD_RESERVE_0_158 (BIT(30))
|
||||
#define EFUSE_RD_RESERVE_0_158_M (EFUSE_RD_RESERVE_0_158_V << EFUSE_RD_RESERVE_0_158_S)
|
||||
#define EFUSE_RD_RESERVE_0_158_V 0x00000001U
|
||||
#define EFUSE_RD_RESERVE_0_158_S 30
|
||||
/** EFUSE_ECDSA_P384_ENABLE : RO; bitpos: [31]; default: 0;
|
||||
* Represents if the chip supports Secure Boot using SHA-384
|
||||
*/
|
||||
#define EFUSE_SECURE_BOOT_SHA384_EN (BIT(31))
|
||||
#define EFUSE_SECURE_BOOT_SHA384_EN_M (EFUSE_SECURE_BOOT_SHA384_EN_V << EFUSE_SECURE_BOOT_SHA384_EN_S)
|
||||
#define EFUSE_SECURE_BOOT_SHA384_EN_V 0x00000001U
|
||||
#define EFUSE_SECURE_BOOT_SHA384_EN_S 31
|
||||
|
||||
/** EFUSE_RD_REPEAT_DATA4_REG register
|
||||
* Represents rd_repeat_data
|
||||
@ -775,6 +789,13 @@ extern "C" {
|
||||
#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_S)
|
||||
#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_V 0x000001FFU
|
||||
#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_S 14
|
||||
/** EFUSE_RD_RESERVE_0_183 : RW; bitpos: [31:23]; default: 0;
|
||||
* Reserved, it was created by set_missed_fields_in_regs func
|
||||
*/
|
||||
#define EFUSE_RD_RESERVE_0_183 0x000001FFU
|
||||
#define EFUSE_RD_RESERVE_0_183_M (EFUSE_RD_RESERVE_0_183_V << EFUSE_RD_RESERVE_0_183_S)
|
||||
#define EFUSE_RD_RESERVE_0_183_V 0x000001FFU
|
||||
#define EFUSE_RD_RESERVE_0_183_S 23
|
||||
|
||||
/** EFUSE_RD_MAC_SYS0_REG register
|
||||
* Represents rd_mac_sys
|
||||
@ -813,22 +834,97 @@ extern "C" {
|
||||
* applications.
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c)
|
||||
/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0;
|
||||
* Reserved.
|
||||
* This field is only for internal debugging purposes. Do not use it in applications.
|
||||
/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
#define EFUSE_MAC_RESERVED_0 0x00003FFFU
|
||||
#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S)
|
||||
#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU
|
||||
#define EFUSE_MAC_RESERVED_0_S 0
|
||||
/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0;
|
||||
* Reserved.
|
||||
* This field is only for internal debugging purposes. Do not use it in applications.
|
||||
#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU
|
||||
#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
|
||||
#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU
|
||||
#define EFUSE_WAFER_VERSION_MINOR_S 0
|
||||
/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
#define EFUSE_MAC_RESERVED_1 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S)
|
||||
#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_1_S 14
|
||||
#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_S 4
|
||||
/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
|
||||
* Disables check of wafer version major
|
||||
*/
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6))
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6
|
||||
/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7))
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7
|
||||
/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
|
||||
* BLK_VERSION_MINOR of BLOCK2
|
||||
*/
|
||||
#define EFUSE_BLK_VERSION_MINOR 0x00000007U
|
||||
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
|
||||
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
|
||||
#define EFUSE_BLK_VERSION_MINOR_S 8
|
||||
/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
|
||||
* BLK_VERSION_MAJOR of BLOCK2
|
||||
*/
|
||||
#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
|
||||
#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
|
||||
#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
|
||||
#define EFUSE_BLK_VERSION_MAJOR_S 11
|
||||
/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
|
||||
* Flash capacity
|
||||
*/
|
||||
#define EFUSE_FLASH_CAP 0x00000007U
|
||||
#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
|
||||
#define EFUSE_FLASH_CAP_V 0x00000007U
|
||||
#define EFUSE_FLASH_CAP_S 13
|
||||
/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0;
|
||||
* Flash vendor
|
||||
*/
|
||||
#define EFUSE_FLASH_VENDOR 0x00000007U
|
||||
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
|
||||
#define EFUSE_FLASH_VENDOR_V 0x00000007U
|
||||
#define EFUSE_FLASH_VENDOR_S 16
|
||||
/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0;
|
||||
* Psram capacity
|
||||
*/
|
||||
#define EFUSE_PSRAM_CAP 0x00000007U
|
||||
#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
|
||||
#define EFUSE_PSRAM_CAP_V 0x00000007U
|
||||
#define EFUSE_PSRAM_CAP_S 19
|
||||
/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0;
|
||||
* Psram vendor
|
||||
*/
|
||||
#define EFUSE_PSRAM_VENDOR 0x00000003U
|
||||
#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
|
||||
#define EFUSE_PSRAM_VENDOR_V 0x00000003U
|
||||
#define EFUSE_PSRAM_VENDOR_S 22
|
||||
/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0;
|
||||
* Temp (die embedded inside)
|
||||
*/
|
||||
#define EFUSE_TEMP 0x00000003U
|
||||
#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S)
|
||||
#define EFUSE_TEMP_V 0x00000003U
|
||||
#define EFUSE_TEMP_S 24
|
||||
/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0;
|
||||
* Package version
|
||||
*/
|
||||
#define EFUSE_PKG_VERSION 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
|
||||
#define EFUSE_PKG_VERSION_V 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_S 26
|
||||
/** EFUSE_PA_TRIM_VERSION : R; bitpos: [31:29]; default: 0;
|
||||
* PADC CAL PA trim version
|
||||
*/
|
||||
#define EFUSE_PA_TRIM_VERSION 0x00000007U
|
||||
#define EFUSE_PA_TRIM_VERSION_M (EFUSE_PA_TRIM_VERSION_V << EFUSE_PA_TRIM_VERSION_S)
|
||||
#define EFUSE_PA_TRIM_VERSION_V 0x00000007U
|
||||
#define EFUSE_PA_TRIM_VERSION_S 29
|
||||
|
||||
/** EFUSE_RD_MAC_SYS3_REG register
|
||||
* Represents rd_mac_sys
|
||||
@ -909,13 +1005,27 @@ extern "C" {
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S)
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 1
|
||||
/** EFUSE_RESERVED_1_134 : R; bitpos: [31:6]; default: 0;
|
||||
/** EFUSE_REF_CURR_CODE : R; bitpos: [9:6]; default: 0;
|
||||
* REF PADC Calibration Curr
|
||||
*/
|
||||
#define EFUSE_REF_CURR_CODE 0x0000000FU
|
||||
#define EFUSE_REF_CURR_CODE_M (EFUSE_REF_CURR_CODE_V << EFUSE_REF_CURR_CODE_S)
|
||||
#define EFUSE_REF_CURR_CODE_V 0x0000000FU
|
||||
#define EFUSE_REF_CURR_CODE_S 6
|
||||
/** EFUSE_RES_TUNE_CODE : R; bitpos: [14:10]; default: 0;
|
||||
* RES PADC Calibration Tune
|
||||
*/
|
||||
#define EFUSE_RES_TUNE_CODE 0x0000001FU
|
||||
#define EFUSE_RES_TUNE_CODE_M (EFUSE_RES_TUNE_CODE_V << EFUSE_RES_TUNE_CODE_S)
|
||||
#define EFUSE_RES_TUNE_CODE_V 0x0000001FU
|
||||
#define EFUSE_RES_TUNE_CODE_S 10
|
||||
/** EFUSE_RESERVED_1_143 : R; bitpos: [31:15]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_134 0x03FFFFFFU
|
||||
#define EFUSE_RESERVED_1_134_M (EFUSE_RESERVED_1_134_V << EFUSE_RESERVED_1_134_S)
|
||||
#define EFUSE_RESERVED_1_134_V 0x03FFFFFFU
|
||||
#define EFUSE_RESERVED_1_134_S 6
|
||||
#define EFUSE_RESERVED_1_143 0x0001FFFFU
|
||||
#define EFUSE_RESERVED_1_143_M (EFUSE_RESERVED_1_143_V << EFUSE_RESERVED_1_143_S)
|
||||
#define EFUSE_RESERVED_1_143_V 0x0001FFFFU
|
||||
#define EFUSE_RESERVED_1_143_S 15
|
||||
|
||||
/** EFUSE_RD_MAC_SYS5_REG register
|
||||
* Represents rd_mac_sys
|
||||
@ -933,49 +1043,49 @@ extern "C" {
|
||||
* Represents rd_sys_part1_data0
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
|
||||
/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
|
||||
#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_0_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA1_REG register
|
||||
* Represents rd_sys_part1_data1
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
|
||||
/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
|
||||
#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_1_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA2_REG register
|
||||
* Represents rd_sys_part1_data2
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
|
||||
/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
|
||||
#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_2_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA3_REG register
|
||||
* Represents rd_sys_part1_data3
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
|
||||
/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
|
||||
#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_3_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA4_REG register
|
||||
* Represents rd_sys_part1_data4
|
||||
@ -1014,37 +1124,128 @@ extern "C" {
|
||||
* Represents rd_sys_part1_data5
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
|
||||
/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
|
||||
#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_S 0
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S 0
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 5
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 15
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA6_REG register
|
||||
* Represents rd_sys_part1_data6
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
|
||||
/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
|
||||
#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
|
||||
* HI DOUT of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
|
||||
* HI DOUT of ADC1 atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA7_REG register
|
||||
* Represents rd_sys_part1_data7
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
|
||||
/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
|
||||
#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0))
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0
|
||||
/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1
|
||||
/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5
|
||||
/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9
|
||||
/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13
|
||||
/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0;
|
||||
* Gap between ADC1 CH4 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 17
|
||||
/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [24:21]; default: 0;
|
||||
* Gap between ADC1 CH5 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 21
|
||||
/** EFUSE_RESERVED_2_249 : R; bitpos: [31:25]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_249 0x0000007FU
|
||||
#define EFUSE_RESERVED_2_249_M (EFUSE_RESERVED_2_249_V << EFUSE_RESERVED_2_249_S)
|
||||
#define EFUSE_RESERVED_2_249_V 0x0000007FU
|
||||
#define EFUSE_RESERVED_2_249_S 25
|
||||
|
||||
/** EFUSE_RD_USR_DATA0_REG register
|
||||
* Represents rd_usr_data0
|
||||
@ -1122,25 +1323,39 @@ extern "C" {
|
||||
* Represents rd_usr_data6
|
||||
*/
|
||||
#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
|
||||
/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of block3 (user).
|
||||
/** EFUSE_RESERVED_3_192 : RO; bitpos: [7:0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_USR_DATA6 0xFFFFFFFFU
|
||||
#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
|
||||
#define EFUSE_USR_DATA6_V 0xFFFFFFFFU
|
||||
#define EFUSE_USR_DATA6_S 0
|
||||
#define EFUSE_RESERVED_3_192 0x000000FFU
|
||||
#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
|
||||
#define EFUSE_RESERVED_3_192_V 0x000000FFU
|
||||
#define EFUSE_RESERVED_3_192_S 0
|
||||
/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
|
||||
* Custom MAC
|
||||
*/
|
||||
#define EFUSE_CUSTOM_MAC 0x00FFFFFFU
|
||||
#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
|
||||
#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU
|
||||
#define EFUSE_CUSTOM_MAC_S 8
|
||||
|
||||
/** EFUSE_RD_USR_DATA7_REG register
|
||||
* Represents rd_usr_data7
|
||||
*/
|
||||
#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
|
||||
/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of block3 (user).
|
||||
/** EFUSE_CUSTOM_MAC_1 : RO; bitpos: [23:0]; default: 0;
|
||||
* Custom MAC
|
||||
*/
|
||||
#define EFUSE_USR_DATA7 0xFFFFFFFFU
|
||||
#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
|
||||
#define EFUSE_USR_DATA7_V 0xFFFFFFFFU
|
||||
#define EFUSE_USR_DATA7_S 0
|
||||
#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU
|
||||
#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
|
||||
#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU
|
||||
#define EFUSE_CUSTOM_MAC_1_S 0
|
||||
/** EFUSE_RESERVED_3_248 : RO; bitpos: [31:24]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_3_248 0x000000FFU
|
||||
#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
|
||||
#define EFUSE_RESERVED_3_248_V 0x000000FFU
|
||||
#define EFUSE_RESERVED_3_248_S 24
|
||||
|
||||
/** EFUSE_RD_KEY0_DATA0_REG register
|
||||
* Represents rd_key0_data0
|
||||
|
||||
@ -434,7 +434,10 @@ typedef union {
|
||||
* Represents the app secure version used by ESP-IDF anti-rollback feature.
|
||||
*/
|
||||
uint32_t secure_version:9;
|
||||
uint32_t reserved_18:7;
|
||||
/** rd_reserve_0_146 : RW; bitpos: [24:18]; default: 0;
|
||||
* Reserved, it was created by set_missed_fields_in_regs func
|
||||
*/
|
||||
uint32_t rd_reserve_0_146:7;
|
||||
/** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
|
||||
* Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled.
|
||||
* 1: Disabled
|
||||
@ -461,11 +464,14 @@ typedef union {
|
||||
* 1: Enabled
|
||||
*/
|
||||
uint32_t xts_dpa_clk_enable:1;
|
||||
uint32_t reserved_30:1;
|
||||
/** ecdsa_p384_enable : RO; bitpos: [31]; default: 0;
|
||||
* Represents if the chip supports ECDSA P384
|
||||
/** rd_reserve_0_158 : RW; bitpos: [30]; default: 0;
|
||||
* Reserved, it was created by set_missed_fields_in_regs func
|
||||
*/
|
||||
uint32_t ecdsa_p384_enable:1;
|
||||
uint32_t rd_reserve_0_158:1;
|
||||
/** secure_boot_sha384_en : RO; bitpos: [31]; default: 0;
|
||||
* Represents if the chip supports Secure Boot using SHA-384
|
||||
*/
|
||||
uint32_t secure_boot_sha384_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_repeat_data3_reg_t;
|
||||
@ -511,7 +517,10 @@ typedef union {
|
||||
* - this feature is disabled. (The low part of the field).
|
||||
*/
|
||||
uint32_t recovery_bootloader_flash_sector_lo:9;
|
||||
uint32_t reserved_23:9;
|
||||
/** rd_reserve_0_183 : RW; bitpos: [31:23]; default: 0;
|
||||
* Reserved, it was created by set_missed_fields_in_regs func
|
||||
*/
|
||||
uint32_t rd_reserve_0_183:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_repeat_data4_reg_t;
|
||||
@ -663,10 +672,18 @@ typedef union {
|
||||
* DBIAS gap between LP and HP
|
||||
*/
|
||||
uint32_t lp_hp_dbias_vol_gap:5;
|
||||
/** reserved_1_134 : R; bitpos: [31:6]; default: 0;
|
||||
/** ref_curr_code : R; bitpos: [9:6]; default: 0;
|
||||
* REF PADC Calibration Curr
|
||||
*/
|
||||
uint32_t ref_curr_code:4;
|
||||
/** res_tune_code : R; bitpos: [14:10]; default: 0;
|
||||
* RES PADC Calibration Tune
|
||||
*/
|
||||
uint32_t res_tune_code:5;
|
||||
/** reserved_1_143 : R; bitpos: [31:15]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_134:26;
|
||||
uint32_t reserved_1_143:17;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys4_reg_t;
|
||||
@ -854,19 +871,119 @@ typedef union {
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
|
||||
|
||||
/** Group: block3 registers */
|
||||
/** Type of rd_usr_datan register
|
||||
* Represents rd_usr_datan
|
||||
/** Type of rd_usr_data0 register
|
||||
* Represents rd_usr_data0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usr_datan : RO; bitpos: [31:0]; default: 0;
|
||||
/** usr_data0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of block3 (user).
|
||||
*/
|
||||
uint32_t usr_datan:32;
|
||||
uint32_t usr_data0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_datan_reg_t;
|
||||
} efuse_rd_usr_data0_reg_t;
|
||||
|
||||
/** Type of rd_usr_data1 register
|
||||
* Represents rd_usr_data1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usr_data1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of block3 (user).
|
||||
*/
|
||||
uint32_t usr_data1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data1_reg_t;
|
||||
|
||||
/** Type of rd_usr_data2 register
|
||||
* Represents rd_usr_data2
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usr_data2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of block3 (user).
|
||||
*/
|
||||
uint32_t usr_data2:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data2_reg_t;
|
||||
|
||||
/** Type of rd_usr_data3 register
|
||||
* Represents rd_usr_data3
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usr_data3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of block3 (user).
|
||||
*/
|
||||
uint32_t usr_data3:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data3_reg_t;
|
||||
|
||||
/** Type of rd_usr_data4 register
|
||||
* Represents rd_usr_data4
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usr_data4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of block3 (user).
|
||||
*/
|
||||
uint32_t usr_data4:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data4_reg_t;
|
||||
|
||||
/** Type of rd_usr_data5 register
|
||||
* Represents rd_usr_data5
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usr_data5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of block3 (user).
|
||||
*/
|
||||
uint32_t usr_data5:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data5_reg_t;
|
||||
|
||||
/** Type of rd_usr_data6 register
|
||||
* Represents rd_usr_data6
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** reserved_3_192 : R; bitpos: [7:0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_3_192:8;
|
||||
/** custom_mac : R; bitpos: [31:8]; default: 0;
|
||||
* Custom MAC
|
||||
*/
|
||||
uint32_t custom_mac:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data6_reg_t;
|
||||
|
||||
/** Type of rd_usr_data7 register
|
||||
* Represents rd_usr_data7
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** custom_mac_1 : R; bitpos: [23:0]; default: 0;
|
||||
* Custom MAC
|
||||
*/
|
||||
uint32_t custom_mac_1:24;
|
||||
/** reserved_3_248 : R; bitpos: [31:24]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_3_248:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data7_reg_t;
|
||||
|
||||
|
||||
/** Group: block4 registers */
|
||||
@ -3781,7 +3898,14 @@ typedef struct {
|
||||
volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
|
||||
volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
|
||||
volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
|
||||
volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8];
|
||||
volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
|
||||
volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
|
||||
volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
|
||||
volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
|
||||
volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
|
||||
volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
|
||||
volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
|
||||
volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
|
||||
volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8];
|
||||
volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];
|
||||
volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8];
|
||||
|
||||
Reference in New Issue
Block a user