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fix(i2s): reserve some invalid registers on S2

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This commit is contained in:
laokaiyao
2024-05-24 14:13:17 +08:00
parent d2468b8d0e
commit 42cee2b94a
5 changed files with 16 additions and 98 deletions
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1
components/esp_lcd/i80/esp_lcd_panel_io_i2s.c
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@@ -184,7 +184,6 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc
// enable I2S LCD master mode (refer to I2S TRM)
i2s_ll_enable_lcd(bus->hal.dev, true);
i2s_ll_tx_stop_on_fifo_empty(bus->hal.dev, true);
i2s_ll_tx_bypass_pcm(bus->hal.dev, true);
i2s_ll_tx_set_slave_mod(bus->hal.dev, false);
i2s_ll_tx_set_bits_mod(bus->hal.dev, bus_config->bus_width);
i2s_ll_tx_select_std_slot(bus->hal.dev, I2S_STD_SLOT_BOTH, true); // copy mono

25
components/hal/esp32/include/hal/i2s_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -74,7 +74,7 @@ static inline void i2s_ll_dma_enable_auto_write_back(i2s_dev_t *hw, bool en)
}
/**
* @brief I2S DMA generate EOF event on data in FIFO poped out
* @brief I2S DMA generate EOF event on data in FIFO popped out
*
* @param hw Peripheral I2S hardware instance address.
* @param en True to enable, False to disable
@@ -695,17 +695,6 @@ static inline void i2s_ll_tx_stop_on_fifo_empty(i2s_dev_t *hw, bool en)
hw->conf1.tx_stop_en = en;
}
/**
* @brief Set whether to bypass the internal PCM module
*
* @param hw Peripheral I2S hardware instance address.
* @param bypass whether to bypass the PCM module
*/
static inline void i2s_ll_tx_bypass_pcm(i2s_dev_t *hw, bool bypass)
{
hw->conf1.tx_pcm_bypass = bypass;
}
/**
* @brief Enable I2S DMA
*
@@ -932,7 +921,7 @@ static inline void i2s_ll_share_bck_ws(i2s_dev_t *hw, bool loopback_en)
* @brief Configure RX PDM downsample
*
* @param hw Peripheral I2S hardware instance address.
* @param dsr PDM downsample configuration paramater
* @param dsr PDM downsample configuration parameter
*/
static inline void i2s_ll_rx_set_pdm_dsr(i2s_dev_t *hw, i2s_pdm_dsr_t dsr)
{
@@ -1080,11 +1069,11 @@ static inline void i2s_ll_tx_set_pdm_fpfs(i2s_dev_t *hw, uint32_t fp, uint32_t f
}
/**
* @brief Get I2S TX PDM fp configuration paramater
* @brief Get I2S TX PDM fp configuration parameter
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - fp configuration paramater
* - fp configuration parameter
*/
static inline uint32_t i2s_ll_tx_get_pdm_fp(i2s_dev_t *hw)
{
@@ -1092,11 +1081,11 @@ static inline uint32_t i2s_ll_tx_get_pdm_fp(i2s_dev_t *hw)
}
/**
* @brief Get I2S TX PDM fs configuration paramater
* @brief Get I2S TX PDM fs configuration parameter
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - fs configuration paramater
* - fs configuration parameter
*/
static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
{

15
components/hal/esp32s2/include/hal/i2s_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -72,7 +72,7 @@ static inline void i2s_ll_dma_enable_auto_write_back(i2s_dev_t *hw, bool en)
}
/**
* @brief I2S DMA generate EOF event on data in FIFO poped out
* @brief I2S DMA generate EOF event on data in FIFO popped out
*
* @param hw Peripheral I2S hardware instance address.
* @param en True to enable, False to disable
@@ -997,17 +997,6 @@ static inline void i2s_ll_tx_stop_on_fifo_empty(i2s_dev_t *hw, bool en)
hw->conf1.tx_stop_en = en;
}
/**
* @brief Set whether to bypass the internal PCM module
*
* @param hw Peripheral I2S hardware instance address.
* @param bypass whether to bypass the PCM module
*/
static inline void i2s_ll_tx_bypass_pcm(i2s_dev_t *hw, bool bypass)
{
hw->conf1.tx_pcm_bypass = bypass;
}
#ifdef __cplusplus
}
#endif

56
components/soc/esp32s2/include/soc/i2s_reg.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -723,26 +723,6 @@ extern "C" {
#define I2S_TX_BCK_IN_DELAY_S 0
#define I2S_FIFO_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020)
/* I2S_TX_24MSB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: Only useful in tx 24bit mode. 1: the high 24 bits are effective
in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
#define I2S_TX_24MSB_EN (BIT(23))
#define I2S_TX_24MSB_EN_M (BIT(23))
#define I2S_TX_24MSB_EN_V 0x1
#define I2S_TX_24MSB_EN_S 23
/* I2S_RX_24MSB_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: Only useful in rx 24bit mode. 1: the high 24 bits are effective
in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
#define I2S_RX_24MSB_EN (BIT(22))
#define I2S_RX_24MSB_EN_M (BIT(22))
#define I2S_RX_24MSB_EN_V 0x1
#define I2S_RX_24MSB_EN_S 22
/* I2S_RX_FIFO_SYNC : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: force write back rx data to memory*/
#define I2S_RX_FIFO_SYNC (BIT(21))
#define I2S_RX_FIFO_SYNC_M (BIT(21))
#define I2S_RX_FIFO_SYNC_V 0x1
#define I2S_RX_FIFO_SYNC_S 21
/* I2S_RX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: The bit should always be set to 1*/
#define I2S_RX_FIFO_MOD_FORCE_EN (BIT(20))
@@ -1192,45 +1172,13 @@ extern "C" {
#define I2S_LC_FIFO_TIMEOUT_S 0
#define I2S_CONF1_REG(i) (REG_I2S_BASE(i) + 0x00a0)
/* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: don't use*/
#define I2S_TX_ZEROS_RM_EN (BIT(9))
#define I2S_TX_ZEROS_RM_EN_M (BIT(9))
#define I2S_TX_ZEROS_RM_EN_V 0x1
#define I2S_TX_ZEROS_RM_EN_S 9
/* I2S_TX_STOP_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
/*description: Set this bit to stop disable output BCK signal and WS signal
when tx FIFO is emtpy*/
when tx FIFO is empty*/
#define I2S_TX_STOP_EN (BIT(8))
#define I2S_TX_STOP_EN_M (BIT(8))
#define I2S_TX_STOP_EN_V 0x1
#define I2S_TX_STOP_EN_S 8
/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[7] ;default: 1'h1 ; */
/*description: Set this bit to bypass Compress/Decompress module for received data.*/
#define I2S_RX_PCM_BYPASS (BIT(7))
#define I2S_RX_PCM_BYPASS_M (BIT(7))
#define I2S_RX_PCM_BYPASS_V 0x1
#define I2S_RX_PCM_BYPASS_S 7
/* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
/*description: Compress/Decompress module configuration bits. 0: decompress
received data 1:compress received data*/
#define I2S_RX_PCM_CONF 0x00000007
#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
#define I2S_RX_PCM_CONF_V 0x7
#define I2S_RX_PCM_CONF_S 4
/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[3] ;default: 1'h1 ; */
/*description: Set this bit to bypass Compress/Decompress module for transmitted data.*/
#define I2S_TX_PCM_BYPASS (BIT(3))
#define I2S_TX_PCM_BYPASS_M (BIT(3))
#define I2S_TX_PCM_BYPASS_V 0x1
#define I2S_TX_PCM_BYPASS_S 3
/* I2S_TX_PCM_CONF : R/W ;bitpos:[2:0] ;default: 3'h1 ; */
/*description: Compress/Decompress module configuration bits. 0: decompress
transmitted data 1:compress transmitted data*/
#define I2S_TX_PCM_CONF 0x00000007
#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
#define I2S_TX_PCM_CONF_V 0x7
#define I2S_TX_PCM_CONF_S 0
#define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4)
/* I2S_DMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'h0 ; */

17
components/soc/esp32s2/include/soc/i2s_struct.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -175,10 +175,7 @@ typedef volatile struct i2s_dev_s {
uint32_t rx_fifo_mod: 3; /*Receiver FIFO mode configuration bits*/
uint32_t tx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_sync: 1; /*force write back rx data to memory*/
uint32_t rx_24msb_en: 1; /*Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t tx_24msb_en: 1; /*Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t reserved24: 8;
uint32_t reserved21: 11;
};
uint32_t val;
} fifo_conf;
@@ -314,13 +311,9 @@ typedef volatile struct i2s_dev_s {
uint32_t reserved_9c;
union {
struct {
uint32_t tx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data*/
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t rx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data*/
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t tx_zeros_rm_en: 1; /*don't use*/
uint32_t reserved10: 22;
uint32_t reserved0: 8;
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty*/
uint32_t reserved9: 23;
};
uint32_t val;
} conf1;