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usb: update LL to support PHY selection

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ESP32-S3 has two USB peripheral, one is USB_OTG, another is
USB_JTAG_SERIAL

A new mux has been introduced to select internal/external PHY interface.
This commit is contained in:
morris
2021-07-09 11:09:28 +08:00
parent a9db7831b0
commit 42f3bca5a1
2 changed files with 12 additions and 0 deletions
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1
components/esp32s3/ld/esp32s3.peripherals.ld
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@@ -37,5 +37,6 @@ PROVIDE ( DMA = 0x6003F000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( LCD_CAM = 0x60041000 );
PROVIDE ( USB_SERIAL_JTAG = 0x60038000 );
PROVIDE ( USB0 = 0x60080000 );
PROVIDE ( USBH = 0x60080000 );
PROVIDE ( USB_WRAP = 0x60039000 );

11
components/hal/esp32s3/include/hal/usb_ll.h
View File

@@ -17,17 +17,28 @@
#include "soc/system_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_periph.h"
#include "soc/rtc_cntl_struct.h"
static inline void usb_ll_int_phy_enable(void)
{
USB_WRAP.otg_conf.pad_enable = 1;
// USB_OTG use internal PHY
USB_WRAP.otg_conf.phy_sel = 0;
// phy_sel is controlled by the following register value
RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
// phy_sel=sw_usb_phy_sel=1, USB_OTG is connected with internal PHY
RTCCNTL.usb_conf.sw_usb_phy_sel = 1;
}
static inline void usb_ll_ext_phy_enable(void)
{
USB_WRAP.otg_conf.pad_enable = 1;
// USB_OTG use external PHY
USB_WRAP.otg_conf.phy_sel = 1;
// phy_sel is controlled by the following register value
RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
// phy_sel=sw_usb_phy_sel=0, USB_OTG is connected with external PHY through GPIO Matrix
RTCCNTL.usb_conf.sw_usb_phy_sel = 0;
}
static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)