forked from espressif/esp-idf
usb: update LL to support PHY selection
ESP32-S3 has two USB peripheral, one is USB_OTG, another is USB_JTAG_SERIAL A new mux has been introduced to select internal/external PHY interface.
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@@ -37,5 +37,6 @@ PROVIDE ( DMA = 0x6003F000 );
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PROVIDE ( APB_SARADC = 0x60040000 );
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PROVIDE ( APB_SARADC = 0x60040000 );
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PROVIDE ( LCD_CAM = 0x60041000 );
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PROVIDE ( LCD_CAM = 0x60041000 );
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PROVIDE ( USB_SERIAL_JTAG = 0x60038000 );
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PROVIDE ( USB_SERIAL_JTAG = 0x60038000 );
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PROVIDE ( USB0 = 0x60080000 );
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PROVIDE ( USBH = 0x60080000 );
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PROVIDE ( USBH = 0x60080000 );
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PROVIDE ( USB_WRAP = 0x60039000 );
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PROVIDE ( USB_WRAP = 0x60039000 );
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@@ -17,17 +17,28 @@
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#include "soc/system_reg.h"
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#include "soc/system_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/usb_periph.h"
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#include "soc/usb_periph.h"
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#include "soc/rtc_cntl_struct.h"
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static inline void usb_ll_int_phy_enable(void)
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static inline void usb_ll_int_phy_enable(void)
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{
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{
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USB_WRAP.otg_conf.pad_enable = 1;
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USB_WRAP.otg_conf.pad_enable = 1;
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// USB_OTG use internal PHY
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USB_WRAP.otg_conf.phy_sel = 0;
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USB_WRAP.otg_conf.phy_sel = 0;
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// phy_sel is controlled by the following register value
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RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
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// phy_sel=sw_usb_phy_sel=1, USB_OTG is connected with internal PHY
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RTCCNTL.usb_conf.sw_usb_phy_sel = 1;
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}
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}
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static inline void usb_ll_ext_phy_enable(void)
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static inline void usb_ll_ext_phy_enable(void)
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{
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{
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USB_WRAP.otg_conf.pad_enable = 1;
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USB_WRAP.otg_conf.pad_enable = 1;
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// USB_OTG use external PHY
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USB_WRAP.otg_conf.phy_sel = 1;
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USB_WRAP.otg_conf.phy_sel = 1;
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// phy_sel is controlled by the following register value
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RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
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// phy_sel=sw_usb_phy_sel=0, USB_OTG is connected with external PHY through GPIO Matrix
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RTCCNTL.usb_conf.sw_usb_phy_sel = 0;
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}
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}
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static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
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static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
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