forked from espressif/esp-idf
change(dw_gdma): add a case to test memset from psram to sram
This commit is contained in:
@@ -1,10 +1,10 @@
|
||||
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
|
||||
|
||||
components/esp_hw_support/test_apps/dma:
|
||||
disable_test:
|
||||
disable:
|
||||
- if: IDF_TARGET in ["esp32"]
|
||||
temporary: false
|
||||
reason: Neither GDMA nor CPDMA is supported on ESP32
|
||||
reason: No general DMA controller on ESP32
|
||||
|
||||
components/esp_hw_support/test_apps/esp_hw_support_unity_tests:
|
||||
disable:
|
||||
|
@@ -1,2 +1,2 @@
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
|
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -12,6 +12,7 @@
|
||||
#include "esp_private/dw_gdma.h"
|
||||
#include "hal/dw_gdma_ll.h"
|
||||
#include "esp_cache.h"
|
||||
#include "esp_private/esp_cache_private.h"
|
||||
|
||||
TEST_CASE("DW_GDMA channel allocation", "[DW_GDMA]")
|
||||
{
|
||||
@@ -499,6 +500,8 @@ TEST_CASE("DW_GDMA M2M Test: Link-List Mode", "[DW_GDMA]")
|
||||
TEST_ESP_OK(dw_gdma_channel_enable_ctrl(m2m_chan, true));
|
||||
|
||||
TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(1000)));
|
||||
// should only go into the block invalid callback for once
|
||||
TEST_ASSERT_EQUAL_UINT8(1, user_data.count);
|
||||
|
||||
printf("check the memory copy result\r\n");
|
||||
#if CONFIG_IDF_TARGET_ESP32P4
|
||||
@@ -515,3 +518,78 @@ TEST_CASE("DW_GDMA M2M Test: Link-List Mode", "[DW_GDMA]")
|
||||
free(dst_buf);
|
||||
vSemaphoreDelete(done_sem);
|
||||
}
|
||||
|
||||
TEST_CASE("DW_GDMA M2M Test: memory set with fixed address", "[DW_GDMA]")
|
||||
{
|
||||
printf("prepare the source and destination buffers\r\n");
|
||||
// memset: source in psram and destination in sram
|
||||
size_t ext_mem_alignment = 0;
|
||||
size_t int_mem_alignment = 0;
|
||||
TEST_ESP_OK(esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &ext_mem_alignment));
|
||||
TEST_ESP_OK(esp_cache_get_alignment(0, &int_mem_alignment));
|
||||
uint8_t *src_buf = heap_caps_aligned_calloc(ext_mem_alignment, 1, 256, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
|
||||
uint8_t *dst_buf = heap_caps_aligned_calloc(int_mem_alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
|
||||
TEST_ASSERT_NOT_NULL(src_buf);
|
||||
TEST_ASSERT_NOT_NULL(dst_buf);
|
||||
// prepare the source buffer, only the first byte has a non-zero value
|
||||
for (int i = 0; i < 256; i++) {
|
||||
src_buf[i] = 0;
|
||||
}
|
||||
src_buf[0] = 66;
|
||||
#if CONFIG_IDF_TARGET_ESP32P4
|
||||
// do write-back for the source data because it's in the cache
|
||||
TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
|
||||
#endif
|
||||
|
||||
printf("allocate a channel for memory set\r\n");
|
||||
dw_gdma_channel_static_config_t static_config = {
|
||||
.block_transfer_type = DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS,
|
||||
.role = DW_GDMA_ROLE_MEM,
|
||||
.num_outstanding_requests = 1,
|
||||
};
|
||||
dw_gdma_channel_alloc_config_t alloc_config = {
|
||||
.src = static_config,
|
||||
.dst = static_config,
|
||||
.flow_controller = DW_GDMA_FLOW_CTRL_SELF, // DMA as the flow controller
|
||||
.chan_priority = 1,
|
||||
};
|
||||
dw_gdma_channel_handle_t m2m_chan = NULL;
|
||||
TEST_ESP_OK(dw_gdma_new_channel(&alloc_config, &m2m_chan));
|
||||
|
||||
printf("set up memory set transaction\r\n");
|
||||
dw_gdma_block_transfer_config_t transfer_config = {
|
||||
.src = {
|
||||
.addr = (uint32_t)src_buf,
|
||||
.burst_mode = DW_GDMA_BURST_MODE_FIXED,
|
||||
.width = DW_GDMA_TRANS_WIDTH_8,
|
||||
.burst_items = 4,
|
||||
.burst_len = 1, // Note for ESP32P4, if the buffer is in PSRAM and the burst mode is fixed, we can't set the burst length larger than 1
|
||||
},
|
||||
.dst = {
|
||||
.addr = (uint32_t)dst_buf,
|
||||
.burst_mode = DW_GDMA_BURST_MODE_INCREMENT,
|
||||
.width = DW_GDMA_TRANS_WIDTH_8,
|
||||
.burst_items = 4,
|
||||
.burst_len = 1,
|
||||
},
|
||||
.size = 256,
|
||||
};
|
||||
TEST_ESP_OK(dw_gdma_channel_config_transfer(m2m_chan, &transfer_config));
|
||||
|
||||
printf("start the DMA engine\r\n");
|
||||
TEST_ESP_OK(dw_gdma_channel_enable_ctrl(m2m_chan, true));
|
||||
vTaskDelay(pdMS_TO_TICKS(100));
|
||||
|
||||
printf("check the memory set result\r\n");
|
||||
#if CONFIG_IDF_TARGET_ESP32P4
|
||||
// the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
|
||||
TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
|
||||
#endif
|
||||
for (int i = 0; i < 256; i++) {
|
||||
TEST_ASSERT_EQUAL_UINT8(66, dst_buf[i]);
|
||||
}
|
||||
|
||||
TEST_ESP_OK(dw_gdma_del_channel(m2m_chan));
|
||||
free(src_buf);
|
||||
free(dst_buf);
|
||||
}
|
||||
|
@@ -0,0 +1,3 @@
|
||||
CONFIG_SPIRAM=y
|
||||
CONFIG_SPIRAM_MODE_HEX=y
|
||||
CONFIG_SPIRAM_SPEED_20M=y
|
Reference in New Issue
Block a user