fix(system): fixed issues with unused variable warnings when compiling with NDEBUG

components/bt/host/bluedroid/stack/btu/btu_hcif.c

@@ -1748,6 +1748,7 @@ static void btu_hcif_command_status_evt_on_task(BT_HDR *event)
     // check the HCI command integrity: opcode
     hci_cmd_metadata_t *metadata = HCI_GET_CMD_METAMSG(hack->command);
     assert(metadata->opcode == opcode);
+    (void)metadata;
 
     HCI_FREE_CMD_BUF(hack->command);
     osi_free(event);

components/console/esp_console_common.c

@@ -166,8 +166,7 @@ void esp_console_repl_task(void *args)
     ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
 
     if (repl_com->state_mux != NULL) {
-        BaseType_t ret_val = xSemaphoreTake(repl_com->state_mux, portMAX_DELAY);
-        assert(ret_val == pdTRUE);
+        xSemaphoreTake(repl_com->state_mux, portMAX_DELAY);
     }
 
     /* Change standard input and output of the task if the requested UART is

components/console/esp_console_repl_internal.c

@@ -121,8 +121,7 @@ esp_err_t esp_console_common_deinit(esp_console_repl_com_t *repl_com)
     // wait for the task to notify that
     // esp_console_repl_task returned
     assert(repl_com->state_mux != NULL);
-    BaseType_t ret_val = xSemaphoreTake(repl_com->state_mux, portMAX_DELAY);
-    assert(ret_val == pdTRUE);
+    xSemaphoreTake(repl_com->state_mux, portMAX_DELAY);
 
     // delete the semaphore for the repl state
     vSemaphoreDelete(repl_com->state_mux);

components/driver/test_apps/components/test_driver_utils/test_spi_utils.c

@@ -76,6 +76,7 @@ void spitest_slave_task(void* arg)
     while (1) {
         BaseType_t ret = xQueueReceive(queue, &txdata, portMAX_DELAY);
         assert(ret);
+        (void)ret;
 
         spi_slave_transaction_t t = {};
         t.length = txdata.len;

components/esp_adc/adc_cali_curve_fitting.c

@@ -163,6 +163,8 @@ static void get_first_step_reference_point(int version_num, adc_unit_t unit_id,
     uint32_t digi = 0;
     ret = esp_efuse_rtc_calib_get_cal_voltage(version_num, unit_id, (int)atten, &digi, &voltage);
     assert(ret == ESP_OK);
+    (void)ret;
+
     calib_info->ref_data.ver1.voltage = voltage;
     calib_info->ref_data.ver1.digi = digi;
 }

components/esp_adc/adc_continuous.c

@@ -79,6 +79,7 @@ static IRAM_ATTR bool adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx)
         else {
             esp_err_t msync_ret = esp_cache_msync((void *)finished_buffer, finished_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
             assert(msync_ret == ESP_OK);
+            (void)msync_ret;
         }
 #endif
 
@@ -126,6 +127,7 @@ static IRAM_ATTR bool adc_dma_intr(adc_continuous_ctx_t *adc_digi_ctx)
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
     esp_err_t msync_ret = esp_cache_msync((void *)(adc_digi_ctx->hal.rx_desc), adc_digi_ctx->adc_desc_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
     assert(msync_ret == ESP_OK);
+    (void)msync_ret;
 #endif
     return need_yield;
 }
@@ -337,6 +339,7 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
     esp_err_t ret = esp_cache_msync(handle->hal.rx_desc, handle->adc_desc_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
     assert(ret == ESP_OK);
+    (void)ret;
 #endif
 
     adc_dma_start(handle->adc_dma, handle->hal.rx_desc);

components/esp_adc/esp32s2/adc_cali_line_fitting.c

@@ -107,6 +107,7 @@ esp_err_t adc_cali_create_scheme_line_fitting(const adc_cali_line_fitting_config
     adc_calib_parsed_info_t efuse_parsed_data = {0};
     bool success = prepare_calib_data_for(config->unit_id, config->atten, &efuse_parsed_data);
     assert(success);
+    (void)success;
     success = calculate_characterization_coefficients(&efuse_parsed_data, chars);
     assert(success);
     ESP_LOGD(TAG, "adc%d (atten leven %d) calibration done: A:%" PRId32" B:%" PRId32, config->unit_id, config->atten, chars->coeff_a, chars->coeff_b);

components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c

@@ -369,6 +369,7 @@ IRAM_ATTR static bool csi_dma_trans_done_callback(dw_gdma_channel_handle_t chan,
     if ((ctlr->trans.buffer != ctlr->backup_buffer) || ctlr->bk_buffer_exposed) {
         esp_err_t ret = esp_cache_msync((void *)(ctlr->trans.buffer), ctlr->trans.received_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
         assert(ret == ESP_OK);
+        (void)ret;
         assert(ctlr->cbs.on_trans_finished);
         if (ctlr->cbs.on_trans_finished) {
             ctlr->trans.received_size = ctlr->fb_size_in_bytes;

components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c

@@ -233,6 +233,8 @@ static uint32_t IRAM_ATTR esp_cam_ctlr_dvp_get_recved_size(esp_cam_ctlr_dvp_cam_
     if (esp_ptr_external_ram(rx_buffer)) {
         esp_err_t ret = esp_cache_msync(rx_buffer, recv_buffer_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
         assert(ret == ESP_OK);
+        (void)ret;
+
     }
 
     if (ctlr->pic_format_jpeg) {

components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c

@@ -170,6 +170,7 @@ esp_err_t IRAM_ATTR esp_cam_ctlr_dvp_dma_start(esp_cam_ctlr_dvp_dma_t *dma, uint
     if (esp_ptr_external_ram(dma->desc)) {
         esp_err_t ret = esp_cache_msync(dma->desc, dma->desc_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
         assert(ret == ESP_OK);
+        (void)ret;
     }
 
     return gdma_start(dma->dma_chan, (intptr_t)dma->desc);

components/esp_driver_cam/isp_dvp/src/esp_cam_ctlr_isp_dvp.c

@@ -503,6 +503,7 @@ IRAM_ATTR static bool s_dvp_dma_trans_done_callback(dw_gdma_channel_handle_t cha
     if ((dvp_ctlr->trans.buffer != dvp_ctlr->backup_buffer) || dvp_ctlr->bk_buffer_exposed) {
         esp_err_t ret = esp_cache_msync((void *)(dvp_ctlr->trans.buffer), dvp_ctlr->trans.received_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
         assert(ret == ESP_OK);
+        (void)ret;
         assert(dvp_ctlr->cbs.on_trans_finished);
         if (dvp_ctlr->cbs.on_trans_finished) {
             dvp_ctlr->trans.received_size = dvp_ctlr->fb_size_in_bytes;

components/esp_driver_i2s/lp_i2s_vad.c

@@ -74,7 +74,7 @@ esp_err_t lp_i2s_vad_new_unit(lp_vad_t vad_id, const lp_vad_init_config_t *init_
 err:
     bool success_free = s_vad_free(vad_id);
     assert(success_free);
-
+    (void)success_free;
     return ret;
 }
 

components/esp_driver_i3c/i3c_master.c

@@ -744,6 +744,7 @@ static esp_err_t do_async_transaction(i3c_master_i2c_device_handle_t dev_handle,
         if (xQueueReceive(bus_handle->trans_queues[I3C_TRANS_QUEUE_PROGRESS], &t, 0)) {
             atomic_store(&bus_handle->fsm, I3C_FSM_RUN);
             ret = bus_handle->transaction_handler(bus_handle, t);
+            (void)ret;
             assert(ret == ESP_OK);
         } else {
             atomic_store(&bus_handle->fsm, I3C_FSM_ENABLE);

components/esp_driver_jpeg/jpeg_decode.c

@@ -382,6 +382,7 @@ static void cfg_desc(jpeg_decoder_handle_t decoder_engine, dma2d_descriptor_t *d
     dsc->next       = next_dsc;
     esp_err_t ret = esp_cache_msync((void*)dsc, decoder_engine->dma_desc_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
     assert(ret == ESP_OK);
+    (void)ret;
 }
 
 static esp_err_t jpeg_dec_config_dma_descriptor(jpeg_decoder_handle_t decoder_engine)

components/esp_driver_jpeg/jpeg_encode.c

@@ -506,6 +506,7 @@ static void s_cfg_desc(jpeg_encoder_handle_t encoder_engine, dma2d_descriptor_t
     dsc->next       = next_dsc;
     esp_err_t ret = esp_cache_msync((void*)dsc, encoder_engine->dma_desc_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
     assert(ret == ESP_OK);
+    (void)ret;
 }
 
 static void s_jpeg_enc_config_picture_color_space(jpeg_encoder_handle_t encoder_engine)

components/esp_driver_ppa/src/ppa_core.c

@@ -379,6 +379,7 @@ static bool ppa_malloc_transaction(QueueHandle_t trans_elm_ptr_queue, uint32_t t
         // Fill the queue with allocated transaction element pointer
         BaseType_t sent = xQueueSend(trans_elm_ptr_queue, &new_trans_elm, 0);
         assert(sent);
+        (void)sent;
     }
     return res;
 }
@@ -400,6 +401,7 @@ bool ppa_recycle_transaction(ppa_client_handle_t ppa_client, ppa_trans_t *trans_
     BaseType_t HPTaskAwoken;
     BaseType_t sent = xQueueSendFromISR(ppa_client->trans_elm_ptr_queue, &trans_elm, &HPTaskAwoken);
     assert(sent);
+    (void)sent;
     return HPTaskAwoken;
 }
 

components/esp_driver_sdio/src/sdio_slave.c

@@ -327,6 +327,7 @@ static void recover_pin(int pin, int sdio_func)
     gpio_io_config_t io_cfg = {};
     esp_err_t ret = gpio_get_io_config(pin, &io_cfg);
     assert(ret == ESP_OK);
+    (void)ret;
 
     if (io_cfg.fun_sel == sdio_func) {
         gpio_set_direction(pin, GPIO_MODE_INPUT);

components/esp_driver_sdmmc/legacy/src/sdmmc_host.c

@@ -201,6 +201,7 @@ size_t sdmmc_host_get_slot_width(int slot)
     sd_host_slot_info_t info = {};
     esp_err_t ret = sd_host_slot_get_info(hdl, &info);
     assert(ret == ESP_OK);
+    (void)ret;
 
     return info.width;
 }

components/esp_driver_sdmmc/src/sd_host_sdmmc.c

@@ -477,6 +477,7 @@ bool sd_host_check_buffer_alignment(sd_host_sdmmc_slot_t *slot, const void *buf,
     }
     ret = esp_cache_get_alignment(cache_flags, &cache_alignment_bytes);
     assert(ret == ESP_OK);
+    (void)ret;
 
     bool is_aligned = false;
     size_t alignment = 0;
@@ -1019,6 +1020,7 @@ static void sd_host_slot_get_clk_dividers(sd_host_sdmmc_slot_t *slot, uint32_t f
 
     esp_err_t ret = esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
     assert(ret == ESP_OK);
+    (void)ret;
     ESP_LOGD(TAG, "clk_src_freq_hz: %"PRId32" hz", clk_src_freq_hz);
 
 #if SDMMC_LL_MAX_FREQ_KHZ_FPGA
@@ -1073,6 +1075,7 @@ static int sd_host_calc_freq(soc_periph_sdmmc_clk_src_t src, const int host_div,
     uint32_t clk_src_freq_hz = 0;
     esp_err_t ret = esp_clk_tree_src_get_freq_hz(src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
     assert(ret == ESP_OK);
+    (void)ret;
 
     return clk_src_freq_hz / host_div / ((card_div == 0) ? 1 : card_div * 2) / 1000;
 }

components/esp_driver_sdmmc/src/sd_trans_sdmmc.c

@@ -90,6 +90,7 @@ size_t sd_host_get_free_descriptors_count(sd_host_sdmmc_slot_t *slot)
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
         esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_M2C);
         assert(ret == ESP_OK);
+        (void)ret;
 #endif
         if (desc->owned_by_idmac) {
             break;
@@ -134,6 +135,7 @@ void sd_host_fill_dma_descriptors(sd_host_sdmmc_slot_t *slot, size_t num_desc)
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
         esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M);
         assert(ret == ESP_OK);
+        (void)ret;
 #endif
     }
 }

components/esp_driver_spi/src/gpspi/spi_master.c

@@ -975,6 +975,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
                 // invalidate priv_trans.buffer_to_rcv anyway, only user provide aligned buffer can rcv correct data in post_cb
                 esp_err_t ret = esp_cache_msync((void *)host->cur_trans_buf.buffer_to_rcv, buffer_byte_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
                 assert(ret == ESP_OK);
+                (void)ret;
             }
 #endif
         }
@@ -1201,6 +1202,7 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
         esp_err_t ret = esp_cache_msync((void *)send_ptr, tx_byte_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
         assert(ret == ESP_OK);
+        (void)ret;
 #endif
     }
 
@@ -1219,6 +1221,7 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans
         // do invalid here to hold on cache status to avoid hardware auto write back during dma transaction
         esp_err_t ret = esp_cache_msync((void *)rcv_ptr, rx_byte_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
         assert(ret == ESP_OK);
+        (void)ret;
 #endif
     }
     priv_desc->buffer_to_send = send_ptr;

components/esp_driver_spi/src/gpspi/spi_slave.c

@@ -722,6 +722,7 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
             // invalidate priv_trans.buffer_to_rcv anyway, only user provide aligned buffer can rcv correct data in post_cb
             esp_err_t ret = esp_cache_msync((void *)host->cur_trans.rx_buffer, buffer_byte_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
             assert(ret == ESP_OK);
+            (void)ret;
         }
 #endif
         if (host->cfg.post_trans_cb) {

components/esp_driver_spi/src/gpspi/spi_slave_hd.c

@@ -475,6 +475,7 @@ static SPI_SLAVE_ISR_ATTR void s_spi_slave_hd_segment_isr(void *arg)
         uint32_t buff_len = (host->rx_curr_trans.trans->len + alignment - 1) & (~(alignment - 1));
         esp_err_t ret = esp_cache_msync((void *)host->rx_curr_trans.aligned_buffer, buff_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
         assert(ret == ESP_OK);
+        (void)ret;
 #endif
         if (callback->cb_recv) {
             spi_slave_hd_event_t ev = {
@@ -617,6 +618,7 @@ static SPI_SLAVE_ISR_ATTR void spi_slave_hd_append_rx_isr(void *arg)
         uint32_t buff_len = (ret_priv_trans.trans->len + alignment - 1) & (~(alignment - 1));
         esp_err_t ret = esp_cache_msync((void *)ret_priv_trans.aligned_buffer, buff_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
         assert(ret == ESP_OK);
+        (void)ret;
 #endif
         bool ret_queue = true;
         if (callback->cb_recv) {

components/esp_eth/src/mac/esp_eth_mac_esp_dma.c

@@ -25,6 +25,7 @@
 #define DMA_CACHE_WB(addr, size) do {                                                           \
     esp_err_t msync_ret = esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_DIR_C2M);    \
     assert(msync_ret == ESP_OK);                                                                \
+    (void)msync_ret;                                                                            \
     } while(0)
 #else
 #define DMA_CACHE_WB(addr, size)
@@ -34,6 +35,7 @@
 #define DMA_CACHE_INVALIDATE(addr, size) do {                                                   \
     esp_err_t msync_ret = esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_DIR_M2C);    \
     assert(msync_ret == ESP_OK);                                                                \
+    (void)msync_ret;                                                                            \
     } while(0)
 #else
 #define DMA_CACHE_INVALIDATE(addr, size)

components/esp_psram/system_layer/esp_psram.c

@@ -251,6 +251,7 @@ static void s_psram_mapping(uint32_t psram_available_size, uint32_t start_page)
     const void *v_start_8bit_aligned = NULL;
     ret = esp_mmu_map_reserve_block_with_caps(size_to_map, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_8BIT | MMU_MEM_CAP_32BIT, MMU_TARGET_PSRAM0, &v_start_8bit_aligned);
     assert(ret == ESP_OK);
+    (void)ret;
 
 #if CONFIG_IDF_TARGET_ESP32
     s_mapping((int)v_start_8bit_aligned, size_to_map);
@@ -663,6 +664,7 @@ static size_t esp_psram_get_effective_mapped_size(void)
         uint32_t psram_available_size = 0;
         esp_err_t ret = esp_psram_impl_get_available_size(&psram_available_size);
         assert(ret == ESP_OK);
+        (void)ret;
 
 #if CONFIG_SPIRAM_RODATA
         psram_available_size -= mmu_psram_get_rodata_segment_length();

components/sdmmc/sdmmc_common.c

@@ -412,6 +412,7 @@ esp_err_t sdmmc_allocate_aligned_buf(sdmmc_card_t* card)
         actual_size = heap_caps_get_allocated_size(buf);
 
         assert(actual_size == SDMMC_IO_BLOCK_SIZE);
+        (void)actual_size;
         card->host.dma_aligned_buffer = buf;
     }
     return ESP_OK;

components/usb/hcd_dwc.c

@@ -281,6 +281,7 @@ static inline void cache_sync_frame_list(void *frame_list)
 {
     esp_err_t ret = esp_cache_msync(frame_list, FRAME_LIST_LEN * sizeof(uint32_t), 0);
     assert(ret == ESP_OK);
+    (void)ret;
 }
 
 /**
@@ -293,6 +294,7 @@ static inline void cache_sync_xfer_descriptor_list(dma_buffer_block_t *buffer, b
 {
     esp_err_t ret = esp_cache_msync(buffer->xfer_desc_list, buffer->xfer_desc_list_len_bytes, mem_to_cache ? ESP_CACHE_MSYNC_FLAG_DIR_M2C : 0);
     assert(ret == ESP_OK);
+    (void)ret;
 }
 
 /**
@@ -315,6 +317,7 @@ static inline void cache_sync_data_buffer(pipe_t *pipe, urb_t *urb, bool done)
         uint32_t flags = (done) ? ESP_CACHE_MSYNC_FLAG_DIR_M2C : ESP_CACHE_MSYNC_FLAG_UNALIGNED;
         esp_err_t ret = esp_cache_msync(urb->transfer.data_buffer, urb->transfer.data_buffer_size, flags);
         assert(ret == ESP_OK);
+        (void)ret;
     }
 }
 #endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE

components/usb/usb_host.c

@@ -956,6 +956,7 @@ esp_err_t usb_host_client_handle_events(usb_host_client_handle_t client_hdl, Tic
             usb_host_client_event_msg_t event_msg;
             BaseType_t queue_ret = xQueueReceive(client_obj->constant.event_msg_queue, &event_msg, 0);
             assert(queue_ret == pdTRUE);
+            (void)queue_ret;
             client_obj->constant.event_callback(&event_msg, client_obj->constant.callback_arg);
         }