feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

Merge branch 'fix/sleep_cpu_mspi_freq_mismatch_issue_p4_v5.3' into 'release/v5.3'

Browse Source 
mspi: fixed cpu and mspi freq mismatch issue when in dfs/sleep on p4 (v5.3)

See merge request espressif/esp-idf!37584
This commit is contained in:
Jiang Jiang Jian
2025-03-08 18:45:20 +08:00
parent d5b8419620 fbda052593
commit 4d62ea01b6
9 changed files with 153 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
components/esp_hw_support/CMakeLists.txt
View File

@@ -41,7 +41,8 @@ if(NOT BOOTLOADER_BUILD)
"dma/esp_dma_utils.c"
"dma/gdma_link.c"
"spi_share_hw_ctrl.c"
"spi_bus_lock.c")
"spi_bus_lock.c"
"clk_utils.c")
if(CONFIG_SOC_ADC_SUPPORTED)
list(APPEND srcs "adc_share_hw_ctrl.c")

71
components/esp_hw_support/clk_utils.c Normal file
View File

@@ -0,0 +1,71 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/param.h>
#include <inttypes.h>
#include <string.h>
#include "sdkconfig.h"
#include "esp_check.h"
#include "esp_log.h"
#include "soc/soc_caps.h"
#include "soc/rtc.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/mspi_timing_tuning.h"
#include "esp_private/esp_clk_utils.h"
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
void esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq)
{
#if CONFIG_IDF_TARGET_ESP32S3
(void) target_cpu_freq;
if (target_cpu_src_freq <= clk_ll_xtal_load_freq_mhz()) {
mspi_timing_change_speed_mode_cache_safe(true);
}
#elif CONFIG_IDF_TARGET_ESP32P4
(void) target_cpu_src_freq;
/**
* Workaround for ESP32P4,
* f_cpu >= f_mspi
*/
if (((target_cpu_freq) < CONFIG_ESPTOOLPY_FLASHFREQ_VAL)
#if CONFIG_SPIRAM
|| ((target_cpu_freq) < CONFIG_SPIRAM_SPEED)
#endif
) {
mspi_timing_change_speed_mode_cache_safe(true);
}
#else
(void) target_cpu_src_freq;
(void) target_cpu_freq;
#endif
}
void esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq)
{
#if CONFIG_IDF_TARGET_ESP32S3
(void) target_cpu_freq;
if (target_cpu_src_freq > clk_ll_xtal_load_freq_mhz()) {
mspi_timing_change_speed_mode_cache_safe(false);
}
#elif CONFIG_IDF_TARGET_ESP32P4
(void) target_cpu_src_freq;
/**
* Workaround for ESP32P4,
* f_cpu >= f_mspi
*/
if (((target_cpu_freq) >= CONFIG_ESPTOOLPY_FLASHFREQ_VAL)
#if CONFIG_SPIRAM
&& ((target_cpu_freq) >= CONFIG_SPIRAM_SPEED)
#endif
) {
mspi_timing_change_speed_mode_cache_safe(false);
}
#else
(void) target_cpu_src_freq;
(void) target_cpu_freq;
#endif
}
#endif

36
components/esp_hw_support/include/esp_private/esp_clk_utils.h Normal file
View File

@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
#include "soc/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
/**
* @brief Sync MSPI speed mode before CPU frequency switching, only needed when frequency is decreasing.
*
* @param target_cpu_src_freq Target clock source frequency for CPU frequency switching
* @param target_cpu_freq CPU frequency switching target frequency
*/
void esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq);
/**
* @brief Sync MSPI speed mode after CPU frequency switching, only needed when frequency is upcreasing.
*
* @param target_cpu_src_freq Target clock source frequency for CPU frequency switching
* @param target_cpu_freq CPU frequency switching target frequency
*/
void esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq);
#endif
#ifdef __cplusplus
}
#endif

1
components/esp_hw_support/linker.lf
View File

@@ -13,6 +13,7 @@ entries:
cpu: esp_cpu_compare_and_set (noflash)
esp_memory_utils (noflash)
rtc_clk (noflash)
clk_utils (noflash)
if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED = y:
rtc_init:rtc_vddsdio_get_config (noflash)
rtc_init:rtc_vddsdio_set_config (noflash)

30
components/esp_hw_support/port/esp32p4/pmu_sleep.c
View File

@@ -368,23 +368,25 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
// the return process, which results in dirty cachelines in L1 Cache again.
pmu_sleep_cache_sync_items(SMMU_GID_DEFAULT, CACHE_SYNC_WRITEBACK, CACHE_MAP_L1_DCACHE, 0, 0);
if (!dslp) {
#if CONFIG_SPIRAM
psram_ctrlr_ll_wait_all_transaction_done();
psram_ctrlr_ll_wait_all_transaction_done();
#endif
s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq();
if (s_mpll_freq_mhz_before_sleep) {
s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq();
if (s_mpll_freq_mhz_before_sleep) {
#if CONFIG_SPIRAM
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL);
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL);
if (!s_pmu_sleep_regdma_backup_enabled) {
// MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.
// If it's a PD_TOP sleep, psram MSPI core clock will be disabled by REGDMA
// !!! Need to manually check that data in PSRAM will not be accessed from now on. !!!
_psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
_psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL);
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL);
if (!s_pmu_sleep_regdma_backup_enabled) {
// MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.
// If it's a PD_TOP sleep, psram MSPI core clock will be disabled by REGDMA
// !!! Need to manually check that data in PSRAM will not be accessed from now on. !!!
_psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
_psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
}
#endif
rtc_clk_mpll_disable();
}
#endif
rtc_clk_mpll_disable();
}
@@ -438,7 +440,7 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
pmu_ll_imm_set_pad_slp_sel(PMU_instance()->hal->dev, false);
if (s_mpll_freq_mhz_before_sleep) {
if (s_mpll_freq_mhz_before_sleep && !dslp) {
rtc_clk_mpll_enable();
rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep);
#if CONFIG_SPIRAM

20
components/esp_hw_support/sleep_modes.c
View File

@@ -14,6 +14,7 @@
#include "esp_memory_utils.h"
#include "esp_sleep.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/esp_clk_utils.h"
#include "esp_private/esp_sleep_internal.h"
#include "esp_private/esp_timer_private.h"
#include "esp_private/rtc_clk.h"
@@ -79,9 +80,6 @@
#include "esp_private/esp_clk.h"
#include "esp_private/esp_task_wdt.h"
#include "esp_private/sar_periph_ctrl.h"
#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
#include "esp_private/mspi_timing_tuning.h"
#endif
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
@@ -94,7 +92,6 @@
#include "esp_private/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#include "esp_private/mspi_timing_tuning.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C2
@@ -807,9 +804,9 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
}
#endif
#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
// Will switch to XTAL turn down MSPI speed
mspi_timing_change_speed_mode_cache_safe(true);
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
uint32_t xtal_freq = rtc_clk_xtal_freq_get();
esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(xtal_freq, xtal_freq);
#endif
#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
@@ -1098,14 +1095,9 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
}
misc_modules_wake_prepare(pd_flags);
}
#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
if (cpu_freq_config.source_freq_mhz > clk_ll_xtal_load_freq_mhz()) {
// Turn up MSPI speed if switch to PLL
mspi_timing_change_speed_mode_cache_safe(false);
}
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(cpu_freq_config.source_freq_mhz, cpu_freq_config.freq_mhz);
#endif
// re-enable UART output
resume_uarts();
return result ? ESP_ERR_SLEEP_REJECT : ESP_OK;

20
components/esp_pm/pm_impl.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -47,9 +47,7 @@
#include "esp_private/sleep_gpio.h"
#include "esp_private/sleep_modem.h"
#include "esp_private/uart_share_hw_ctrl.h"
#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
#include "esp_private/mspi_timing_tuning.h"
#endif
#include "esp_private/esp_clk_utils.h"
#include "esp_sleep.h"
#include "esp_memory_utils.h"
@@ -668,16 +666,12 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
if (switch_down) {
on_freq_update(old_ticks_per_us, new_ticks_per_us);
}
#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
if (new_config.source_freq_mhz > clk_ll_xtal_load_freq_mhz()) {
rtc_clk_cpu_freq_set_config_fast(&new_config);
mspi_timing_change_speed_mode_cache_safe(false);
} else {
mspi_timing_change_speed_mode_cache_safe(true);
rtc_clk_cpu_freq_set_config_fast(&new_config);
}
#else
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(new_config.source_freq_mhz, new_config.freq_mhz);
#endif
rtc_clk_cpu_freq_set_config_fast(&new_config);
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(new_config.source_freq_mhz, new_config.freq_mhz);
#endif
if (!switch_down) {
on_freq_update(old_ticks_per_us, new_ticks_per_us);

17
components/esp_system/port/esp_system_chip.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,10 +8,11 @@
#include "esp_cpu.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/esp_clk_utils.h"
#include "esp_private/rtc_clk.h"
#include "esp_private/panic_internal.h"
#include "esp_private/system_internal.h"
#include "esp_private/mspi_timing_tuning.h"
#include "esp_heap_caps.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
@@ -35,15 +36,9 @@ void IRAM_ATTR esp_restart_noos_dig(void)
}
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
/**
* Turn down MSPI speed
*
* We set MSPI clock to a high speed one before, ROM doesn't have such high speed clock source option.
* This function will change clock source to a ROM supported one when system restarts.
*/
mspi_timing_change_speed_mode_cache_safe(true);
#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
uint32_t xtal_freq = clk_ll_xtal_load_freq_mhz();
esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(xtal_freq, xtal_freq);
#endif
// switch to XTAL (otherwise we will keep running from the PLL)
rtc_clk_cpu_set_to_default_config();

8
components/esptool_py/Kconfig.projbuild
View File

@@ -149,6 +149,14 @@ menu "Serial flasher config"
depends on SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED
endchoice
config ESPTOOLPY_FLASHFREQ_VAL
int
depends on IDF_TARGET_ESP32P4
default 20 if ESPTOOLPY_FLASHFREQ_20M
default 40 if ESPTOOLPY_FLASHFREQ_40M
default 80 if ESPTOOLPY_FLASHFREQ_80M
default 120 if ESPTOOLPY_FLASHFREQ_120M
config ESPTOOLPY_FLASHFREQ_80M_DEFAULT
bool
default y if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6