feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

Merge branch 'feature/esp32c5_eco2_gdma_update' into 'master'

Browse Source 
feat(gdma): apply c5 eco2 gdma minor modification

Closes IDF-12637, IDF-12835, and IDF-10407

See merge request espressif/esp-idf!38602
This commit is contained in:
Chen Ji Chang
2025-04-22 19:11:15 +08:00
parent 206fe63029 917868d5b7
commit 4fd84d4e63
6 changed files with 1844 additions and 8674 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
components/hal/esp32c5/include/hal/ahb_dma_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -26,8 +26,8 @@ extern "C" {
#define GDMA_LL_RX_EVENT_MASK (0x7F)
#define GDMA_LL_TX_EVENT_MASK (0x3F)
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC31)
// for M2M mode, hardware will automatically assign peri_sel ID depends on the channel number (ch0: 10, ch1: 11, ch2: 12)
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1C00)
#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
@@ -220,6 +220,9 @@ static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;
@@ -470,6 +473,9 @@ static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;

49
components/soc/esp32c5/gdma_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -34,19 +34,19 @@ const gdma_signal_conn_t gdma_periph_signals = {
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG
AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG
AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
AHB_DMA_MODULE_CLK_EN_REG
*/
#define G0P0_RETENTION_REGS_CNT_0 13
#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
#define G0P0_RETENTION_REGS_CNT_1 12
#define G0P0_RETENTION_REGS_CNT_1 11
#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x2dc)
static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0x0c900000, 0x601, 0x0};
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
@@ -72,19 +72,19 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG
AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG
AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
AHB_DMA_MODULE_CLK_EN_REG
*/
#define G0P1_RETENTION_REGS_CNT_0 13
#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
#define G0P1_RETENTION_REGS_CNT_1 12
#define G0P1_RETENTION_REGS_CNT_1 11
#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x304)
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x434800, 0x18, 0x0};
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
@@ -107,23 +107,24 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
/* AHB_DMA Channel (Group0, Pair2) Registers Context
Include: AHB_DMA_MISC_CONF_REG
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
AHB_DMA_IN_PERI_SEL_CH2_REG
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_PRI_CH2_REG
AHB_DMA_OUT_PERI_SEL_CH2_REG
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG
AHB_DMA_RX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH2_REG
AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
AHB_DMA_MODULE_CLK_EN_REG
*/
#define G0P2_RETENTION_REGS_CNT_0 3
#define G0P2_RETENTION_REGS_CNT_0 8
#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
#define G0P2_RETENTION_REGS_CNT_1 22
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x1f0)
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x0};
static const uint32_t g0p2_regs_map1[4] = {0x13001813, 0x18, 0x18000, 0x7f26000};
#define G0P2_RETENTION_REGS_CNT_1 16
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x250)
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x604c0000};
static const uint32_t g0p2_regs_map1[4] = {0x1813, 0x1800000, 0x72600000, 0x3008};
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \

1686
components/soc/esp32c5/register/soc/ahb_dma_reg.h
View File

File diff suppressed because it is too large Load Diff

3977
components/soc/esp32c5/register/soc/ahb_dma_reg_eco2.h
View File

File diff suppressed because it is too large Load Diff

1220
components/soc/esp32c5/register/soc/ahb_dma_struct.h
View File

File diff suppressed because it is too large Load Diff

3574
components/soc/esp32c5/register/soc/ahb_dma_struct_eco2.h
View File

File diff suppressed because it is too large Load Diff