feat(driver_spi): add h21 spi drivers supports

2025-03-18 17:14:18 +08:00
parent 8994f8fe70
commit 51873d46aa
57 changed files with 2056 additions and 266 deletions
--- a/components/esp_driver_sdspi/test_apps/sdspi/README.md
+++ b/components/esp_driver_sdspi/test_apps/sdspi/README.md
@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/src/gpspi/spi_master.c
+++ b/components/esp_driver_spi/src/gpspi/spi_master.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -115,8 +115,8 @@ We have two bits to control the interrupt:
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/spi_common_internal.h"
 #include "esp_private/spi_master_internal.h"
+#include "esp_private/esp_clk_tree_common.h"
 #include "driver/spi_master.h"
-#include "esp_clk_tree.h"
 #include "clk_ctrl_os.h"
 #include "esp_log.h"
 #include "esp_check.h"
@ -415,12 +415,10 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
        SPI_CHECK(periph_rtc_dig_clk8m_enable(), "the selected clock not available", ESP_ERR_INVALID_STATE);
    }
 #endif
-    spi_clock_source_t clk_src = SPI_CLK_SRC_DEFAULT;
+    spi_clock_source_t clk_src = dev_config->clock_source ? dev_config->clock_source : SPI_CLK_SRC_DEFAULT;
    uint32_t clock_source_hz = 0;
    uint32_t clock_source_div = 1;
-    if (dev_config->clock_source) {
-        clk_src = dev_config->clock_source;
-    }
+    esp_clk_tree_enable_src(clk_src, true);
    esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz);
 #if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
    SPI_CHECK((dev_config->clock_speed_hz > 0) && (dev_config->clock_speed_hz <= MIN(clock_source_hz / 2, (80 * 1000000))), "invalid sclk speed", ESP_ERR_INVALID_ARG);
@ -584,7 +582,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
    }

 #if SOC_SPI_SUPPORT_CLK_RC_FAST
-    if (handle->cfg.clock_source == SPI_CLK_SRC_RC_FAST) {
+    if (handle->hal_dev.timing_conf.clock_source == SPI_CLK_SRC_RC_FAST) {
        // If no transactions from other device, acquire the bus to switch module clock to `SPI_CLK_SRC_DEFAULT`
        // because `SPI_CLK_SRC_RC_FAST` will be disabled then, which block following transactions
        if (handle->host->cur_cs == DEV_NUM_MAX) {
@ -597,6 +595,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
        periph_rtc_dig_clk8m_disable();
    }
 #endif
+    esp_clk_tree_enable_src(handle->hal_dev.timing_conf.clock_source, false);

    //return
    int spics_io_num = handle->cfg.spics_io_num;
--- a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
+++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -7,87 +7,103 @@
 #pragma once

 #if CONFIG_IDF_TARGET_ESP32
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            16*1000*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            15
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 16*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          15
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15
 #if !CONFIG_FREERTOS_SMP // IDF-5223
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                34      // TODO: IDF-5180
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         30      // TODO: IDF-5180
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          34      // TODO: IDF-5180
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          30      // TODO: IDF-5180
 #else
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                50
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         50
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          50
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          50
 #endif

 #elif CONFIG_IDF_TARGET_ESP32S2
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            40*1000*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                32
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         30
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          15
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          32
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          30

 #elif CONFIG_IDF_TARGET_ESP32S3
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            40*1000*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                32
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         30
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          15
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          32
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          30

 #elif CONFIG_IDF_TARGET_ESP32C2
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            40*1000*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   23
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            18
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                47
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         42
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          23
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          18
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          47
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          42

 #elif CONFIG_IDF_TARGET_ESP32C3
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            40*1000*1000
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
 #if !CONFIG_FREERTOS_SMP // IDF-5223
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                33
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         30
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          15
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          33
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          30
 #else
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   17
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            17
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                60
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         60
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          17
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          17
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          60
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          60
 #endif

 #elif CONFIG_IDF_TARGET_ESP32C6
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            26666*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                35  //TODO: IDF-9551, check perform
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   17
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         32
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            15
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 26666*1000
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          35  //TODO: IDF-9551, check perform
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          17
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          32
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          15

 #elif CONFIG_IDF_TARGET_ESP32H2
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            24*1000*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   32
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            25
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                61
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         54
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 24*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          32
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          25
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          61
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          54

 #elif CONFIG_IDF_TARGET_ESP32P4
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            20*1000*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                44
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   28
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         26
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            12
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 20*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          44
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          28
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          26
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          12

 #elif CONFIG_IDF_TARGET_ESP32C5
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            40*1000*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                24
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         22
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            12
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          24
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          15
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          22
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          12

 #elif CONFIG_IDF_TARGET_ESP32C61
-#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            40*1000*1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                32
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   19
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         29
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            14
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          32
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          19
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          29
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          14

+#elif CONFIG_IDF_TARGET_ESP32H21
+#if SOC_CLK_TREE_SUPPORTED
+//TODO: [ESP32H21] IDF-11521 update perform data according to `TEST_CASE("spi_speed", "[spi]")`
+//Also update this value in doc spi_master.rst:535
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 32*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          0   // need update to real_val + 3
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          0   // need update to real_val + 3
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          0   // need update to real_val + 3
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          0   // need update to real_val + 3
 #else
-#pragma message "`spi_performance.h` is not updated with your target"
+// Remove after SOC_CLK_TREE_SUPPORTED
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 32*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          1000
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          1000
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          1000
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          1000
+#endif
+
 #endif
--- a/components/esp_driver_spi/test_apps/master/README.md
+++ b/components/esp_driver_spi/test_apps/master/README.md
@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
+++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -114,6 +114,8 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
        for (int i = 0; i < TEST_CLK_TIMES; i++) {
            check_spi_pre_n_for(clk_param_40m[i][0], clk_param_40m[i][1], clk_param_40m[i][2]);
        }
+    } else {
+        ESP_LOGW(TAG, "Don't find any routing param!!");
    }

    TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
@ -147,7 +149,7 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
            spi_device_handle_t handle;
            spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
            devcfg.clock_source = spi_clk_sour[sour_idx];
-            devcfg.clock_speed_hz = MIN(IDF_PERFORMANCE_MAX_SPI_CLK_FREQ, clock_source_hz) >> test_time;
+            devcfg.clock_speed_hz = MIN(IDF_TARGET_MAX_SPI_CLK_FREQ, clock_source_hz) >> test_time;
            devcfg.flags |= SPI_DEVICE_HALFDUPLEX;  //esp32 half duplex to work on high freq
 #if SOC_SPI_SUPPORT_CLK_RC_FAST
            if (devcfg.clock_source == SPI_CLK_SRC_RC_FAST) {
@ -170,6 +172,9 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
            end = esp_timer_get_time();
            int trans_cost = end - start;
            int time_tolerance = trans_cost_us_predict * TEST_TRANS_TIME_BIAS_RATIO;
+#if !SOC_CLK_TREE_SUPPORTED
+            time_tolerance *= 2;    //cpu is executing too slow before clock supported
+#endif
            printf("real_freq %dk predict_cost %d real_cost_us %d diff %d tolerance %d us\n", real_freq_khz, trans_cost_us_predict, trans_cost, (trans_cost - trans_cost_us_predict), time_tolerance);

            TEST_ASSERT_LESS_THAN_UINT32(time_tolerance, abs(trans_cost - trans_cost_us_predict));
@ -197,7 +202,7 @@ TEST_CASE("test_device_dynamic_freq_update", "[spi]")
        .length = sizeof(master_send) * 8,
    };

-    trans_cfg.override_freq_hz = IDF_PERFORMANCE_MAX_SPI_CLK_FREQ;
+    trans_cfg.override_freq_hz = IDF_TARGET_MAX_SPI_CLK_FREQ;
    for (int i = 1; i < 15; i++) {
        TEST_ESP_OK(spi_device_transmit(dev0, &trans_cfg));
        spi_device_get_actual_freq(dev0, &master_send);
@ -1463,7 +1468,7 @@ TEST_CASE("spi_speed", "[spi]")
    }
 #ifndef CONFIG_SPIRAM
    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_NO_POLLING", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
-    TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
+    TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_INTR_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif

    //acquire the bus to send polling transactions faster
@ -1481,7 +1486,7 @@ TEST_CASE("spi_speed", "[spi]")
    }
 #ifndef CONFIG_SPIRAM
    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLLING", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
-    TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
+    TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_POLL_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif

    //release the bus
@ -1501,7 +1506,7 @@ TEST_CASE("spi_speed", "[spi]")
    }
 #ifndef CONFIG_SPIRAM
    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_NO_POLLING_NO_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
-    TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
+    TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_INTR_CPU, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif

    //acquire the bus to send polling transactions faster
@ -1519,7 +1524,7 @@ TEST_CASE("spi_speed", "[spi]")
    }
 #ifndef CONFIG_SPIRAM
    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLLING_NO_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
-    TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
+    TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_POLL_CPU, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif

    //release the bus
@ -1830,6 +1835,7 @@ TEST_CASE("test_bus_free_safty_to_remain_devices", "[spi]")
    TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
 }

+#if SOC_LIGHT_SLEEP_SUPPORTED
 TEST_CASE("test_spi_master_sleep_retention", "[spi]")
 {
    // Prepare a TOP PD sleep
@ -1959,3 +1965,4 @@ TEST_CASE("test_spi_master_auto_sleep_retention", "[spi]")
    TEST_ESP_OK(esp_pm_configure(&pm_config));
 }
 #endif  //CONFIG_PM_ENABLE
+#endif  //SOC_LIGHT_SLEEP_SUPPORTED
--- a/components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c
+++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c
@ -292,6 +292,7 @@ TEST_CASE("spi_master: test_sct_dma_desc_oob_on_tail", "[spi]")
    TEST_ESP_OK(spi_bus_free(SPI2_HOST));
 }

+#if SOC_LIGHT_SLEEP_SUPPORTED
 /*-----------------------------------------------------------
 * Sleep Retention Test
 *-----------------------------------------------------------*/
@ -416,3 +417,4 @@ static void sleep_slave(void)
    TEST_ESP_OK(spi_slave_hd_deinit(SPI2_HOST));
 }
 TEST_CASE_MULTIPLE_DEVICES("test_spi_master_sct_sleep_retention", "[spi_ms]", sleep_master, sleep_slave);
+#endif  //SOC_LIGHT_SLEEP_SUPPORTED
--- a/components/esp_driver_spi/test_apps/param/README.md
+++ b/components/esp_driver_spi/test_apps/param/README.md
@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
+++ b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -1269,12 +1269,12 @@ TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "")
 #define TEST_STEP_LEN         96
 #define TEST_STEP             2
 static int s_spi_bus_freq[] = {
-    IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 10,
-    IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 7,
-    IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 4,
-    IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 2,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 10,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 7,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 4,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 2,
 #if !CONFIG_IDF_TARGET_ESP32P4      //TODO: IDF-8313, update P4 defaulte clock source
-    IDF_PERFORMANCE_MAX_SPI_CLK_FREQ,
+    IDF_TARGET_MAX_SPI_CLK_FREQ,
 #endif
 };

--- a/components/esp_driver_spi/test_apps/slave/README.md
+++ b/components/esp_driver_spi/test_apps/slave/README.md
@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
+++ b/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
@ -782,6 +782,7 @@ TEST_CASE("test_slave_isr_pin_to_core", "[spi]")
 }
 #endif

+#if SOC_LIGHT_SLEEP_SUPPORTED
 TEST_CASE("test_spi_slave_sleep_retention", "[spi]")
 {
    // Prepare a TOP PD sleep
@ -842,3 +843,4 @@ TEST_CASE("test_spi_slave_sleep_retention", "[spi]")
    TEST_ESP_OK(sleep_cpu_configure(false));
 #endif
 }
+#endif  //SOC_LIGHT_SLEEP_SUPPORTED
--- a/components/esp_driver_spi/test_apps/slave_hd/README.md
+++ b/components/esp_driver_spi/test_apps/slave_hd/README.md
@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
+++ b/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -1063,6 +1063,7 @@ void master_run_essl(void)
 }
 TEST_CASE_MULTIPLE_DEVICES("SPI Slave HD: Append mode", "[spi_ms]", master_run_essl, slave_run_append);

+#if SOC_LIGHT_SLEEP_SUPPORTED
 #define TEST_SLP_BUF_ID                 12
 #define TEST_SLP_BUF_VAL                0xDEADBEEF
 TEST_CASE("test_spi_slave_hd_sleep_retention", "[spi]")
@ -1238,3 +1239,4 @@ TEST_CASE("test_spi_slave_hd_append_sleep_retention", "[spi]")
    TEST_ESP_OK(sleep_cpu_configure(false));
 #endif
 }
+#endif  //SOC_LIGHT_SLEEP_SUPPORTED
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt
@ -3,6 +3,7 @@ set(srcs "test_app_main.c"
          "test_fp.c"
          "test_dport_xt_highint5.S"
          "test_random.c"
+          "test_intr_alloc.c"
           )

 if(CONFIG_SOC_GP_LDO_SUPPORTED)
@ -21,10 +22,6 @@ if(CONFIG_SOC_ETM_SUPPORTED)
    list(APPEND srcs "test_etm_core.c")
 endif()

-if(CONFIG_SOC_GPTIMER_SUPPORTED AND CONFIG_SOC_GPSPI_SUPPORTED)
-    list(APPEND srcs "test_intr_alloc.c")
-endif()
-
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -19,11 +19,16 @@
 #include "esp_intr_alloc.h"
 #include "driver/gptimer.h"
 #include "soc/soc_caps.h"
+#include "soc/system_intr.h"
+#if SOC_GPSPI_SUPPORTED
 #include "soc/spi_periph.h"
 #include "hal/spi_ll.h"
+#endif
+#include "hal/gpio_ll.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/gptimer.h"

+#if SOC_GPTIMER_SUPPORTED
 static bool on_timer_alarm(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_ctx)
 {
    volatile int *count = (volatile int *)user_ctx;
@ -116,6 +121,7 @@ TEST_CASE("Intr_alloc test, shared ints", "[intr_alloc]")
 {
    timer_test(ESP_INTR_FLAG_SHARED);
 }
+#endif //SOC_GPTIMER_SUPPORTED

 void static test_isr(void*arg)
 {
@ -130,13 +136,13 @@ TEST_CASE("Intr_alloc test, shared interrupts don't affect level", "[intr_alloc]
    intr_handle_t handle_lvl_2;

    /* Allocate an interrupt of level 1 that will be shared with another source */
-    esp_err_t err = esp_intr_alloc(ETS_FROM_CPU_INTR2_SOURCE,
+    esp_err_t err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_2_SOURCE,
                                   ESP_INTR_FLAG_LEVEL1 | ESP_INTR_FLAG_SHARED,
                                   test_isr, NULL, &handle_lvl_1);
    TEST_ESP_OK(err);

    /* Allocate a shared interrupt of a different level */
-    err = esp_intr_alloc(ETS_FROM_CPU_INTR3_SOURCE,
+    err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_3_SOURCE,
                         ESP_INTR_FLAG_LEVEL2  | ESP_INTR_FLAG_SHARED,
                         test_isr, NULL, &handle_lvl_2);
    TEST_ESP_OK(err);
@ -163,7 +169,7 @@ TEST_CASE("Intr_alloc test, shared interrupts custom level cleared", "[intr_allo
 {
    intr_handle_t handle;

-    esp_err_t err = esp_intr_alloc(ETS_FROM_CPU_INTR2_SOURCE,
+    esp_err_t err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_2_SOURCE,
                                   ESP_INTR_FLAG_LEVEL1 | ESP_INTR_FLAG_SHARED,
                                   test_isr, NULL, &handle);
    TEST_ESP_OK(err);
@ -174,7 +180,7 @@ TEST_CASE("Intr_alloc test, shared interrupts custom level cleared", "[intr_allo
    /* Free the shared interrupt and try to reallocate it with another level */
    TEST_ESP_OK(esp_intr_free(handle));

-    err = esp_intr_alloc(ETS_FROM_CPU_INTR3_SOURCE,
+    err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_3_SOURCE,
                         ESP_INTR_FLAG_LEVEL2  | ESP_INTR_FLAG_SHARED,
                         test_isr, NULL, &handle);
    TEST_ESP_OK(err);
@ -199,13 +205,13 @@ TEST_CASE("Intr_alloc test, shared interrupt line for two sources", "[intr_alloc
    intr_handle_t handle_1;
    intr_handle_t handle_2;

-    esp_err_t err = esp_intr_alloc(ETS_FROM_CPU_INTR2_SOURCE,
+    esp_err_t err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_2_SOURCE,
                                   ESP_INTR_FLAG_LEVEL1 | ESP_INTR_FLAG_SHARED,
                                   test_isr, NULL, &handle_1);
    TEST_ESP_OK(err);

    /* Map another source to the exact same interrupt line */
-    err = esp_intr_alloc_bind(ETS_FROM_CPU_INTR3_SOURCE,
+    err = esp_intr_alloc_bind(SYS_CPU_INTR_FROM_CPU_3_SOURCE,
                              ESP_INTR_FLAG_LEVEL1  | ESP_INTR_FLAG_SHARED,
                              test_isr, NULL, handle_1, &handle_2);
    TEST_ESP_OK(err);
@ -214,7 +220,7 @@ TEST_CASE("Intr_alloc test, shared interrupt line for two sources", "[intr_alloc

    /* Reallocate the second interrupt source with a higher level, it must fail */
    TEST_ESP_OK(esp_intr_free(handle_2));
-    err = esp_intr_alloc_bind(ETS_FROM_CPU_INTR3_SOURCE,
+    err = esp_intr_alloc_bind(SYS_CPU_INTR_FROM_CPU_3_SOURCE,
                              ESP_INTR_FLAG_LEVEL2  | ESP_INTR_FLAG_SHARED,
                              test_isr, NULL, handle_1, &handle_2);
    TEST_ASSERT(err != ESP_OK);
@ -227,11 +233,7 @@ TEST_CASE("Intr_alloc test, shared interrupt line for two sources", "[intr_alloc
 TEST_CASE("Allocate previously freed interrupt, with different flags", "[intr_alloc]")
 {
    intr_handle_t intr;
-#if CONFIG_IDF_TARGET_ESP32P4
-    int test_intr_source = ETS_GPIO_INTR0_SOURCE;
-#else
-    int test_intr_source = ETS_GPIO_INTR_SOURCE;
-#endif
+    int test_intr_source = GPIO_LL_INTR_SOURCE0;
    int isr_flags = ESP_INTR_FLAG_LEVEL2;

    TEST_ESP_OK(esp_intr_alloc(test_intr_source, isr_flags, test_isr, NULL, &intr));
@ -242,6 +244,7 @@ TEST_CASE("Allocate previously freed interrupt, with different flags", "[intr_al
    TEST_ESP_OK(esp_intr_free(intr));
 }

+#if SOC_GPSPI_SUPPORTED
 typedef struct {
    bool flag1;
    bool flag2;
@ -418,7 +421,8 @@ TEST_CASE("alloc and free isr handle on different core when isr_free_task is NO_
 {
    isr_alloc_free_test(true);
 }
-#endif
+#endif //CONFIG_FREERTOS_UNICORE
+#endif //SOC_GPSPI_SUPPORTED

 #if __XTENSA__
 static volatile int int_timer_ctr;
--- a/components/esp_lcd/test_apps/spi_lcd/README.md
+++ b/components/esp_lcd/test_apps/spi_lcd/README.md
@ -1,4 +1,4 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 This test app is used to test LCDs with SPI interface.
--- a/components/esp_system/port/arch/riscv/esp_ipc_isr_port.c
+++ b/components/esp_system/port/arch/riscv/esp_ipc_isr_port.c
@ -5,7 +5,7 @@
 */

 #include "soc/soc.h"
-#include "soc/interrupts.h"
+#include "soc/system_intr.h"
 #include "soc/hp_system_reg.h"
 #include "esp_intr_alloc.h"
 #include "riscv/interrupt.h"
@ -16,7 +16,7 @@

 void esp_ipc_isr_port_init(const int cpuid)
 {
-    uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE + cpuid; // ETS_FROM_CPU_INTR2_SOURCE and ETS_FROM_CPU_INTR3_SOURCE
+    uint32_t intr_source = SYS_CPU_INTR_FROM_CPU_2_SOURCE + cpuid; // ETS_FROM_CPU_INTR2_SOURCE and ETS_FROM_CPU_INTR3_SOURCE

    esp_intr_disable_source(ETS_IPC_ISR_INUM);

--- a/components/esp_system/port/arch/xtensa/esp_ipc_isr_port.c
+++ b/components/esp_system/port/arch/xtensa/esp_ipc_isr_port.c
@ -5,7 +5,7 @@
 */

 #include "soc/soc.h"
-#include "soc/interrupts.h"
+#include "soc/system_intr.h"
 #include "soc/dport_reg.h"
 #ifndef CONFIG_IDF_TARGET_ESP32
 #include "soc/system_reg.h"
@ -17,7 +17,7 @@

 void esp_ipc_isr_port_init(const int cpuid)
 {
-    uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE + cpuid; // ETS_FROM_CPU_INTR2_SOURCE and ETS_FROM_CPU_INTR3_SOURCE
+    uint32_t intr_source = SYS_CPU_INTR_FROM_CPU_2_SOURCE + cpuid; // ETS_FROM_CPU_INTR2_SOURCE and ETS_FROM_CPU_INTR3_SOURCE
    ESP_INTR_DISABLE(ETS_IPC_ISR_INUM);
    esp_rom_route_intr_matrix(cpuid, intr_source, ETS_IPC_ISR_INUM);
    ESP_INTR_ENABLE(ETS_IPC_ISR_INUM);
--- a/components/hal/esp32h21/include/hal/spi_ll.h
+++ b/components/hal/esp32h21/include/hal/spi_ll.h
--- a/components/soc/esp32/include/soc/system_intr.h
+++ b/components/soc/esp32/include/soc/system_intr.h
@ -5,9 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
 #define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32c2/include/soc/system_intr.h
+++ b/components/soc/esp32c2/include/soc/system_intr.h
@ -5,8 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32c3/include/soc/system_intr.h
+++ b/components/soc/esp32c3/include/soc/system_intr.h
@ -5,8 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32c5/include/soc/system_intr.h
+++ b/components/soc/esp32c5/include/soc/system_intr.h
@ -5,8 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32c6/include/soc/system_intr.h
+++ b/components/soc/esp32c6/include/soc/system_intr.h
@ -5,8 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32c61/include/soc/system_intr.h
+++ b/components/soc/esp32c61/include/soc/system_intr.h
@ -5,8 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32h2/include/soc/system_intr.h
+++ b/components/soc/esp32h2/include/soc/system_intr.h
@ -5,8 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@ -35,6 +35,10 @@ config SOC_RTC_MEM_SUPPORTED
    bool
    default y

+config SOC_GPSPI_SUPPORTED
+    bool
+    default y
+
 config SOC_I2C_SUPPORTED
    bool
    default y
@ -467,10 +471,6 @@ config SOC_SPI_MAXIMUM_BUFFER_SIZE
    int
    default 64

-config SOC_SPI_SUPPORT_DDRCLK
-    bool
-    default y
-
 config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
    bool
    default y
@ -483,6 +483,10 @@ config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
    bool
    default y

+config SOC_SPI_SUPPORT_SLAVE_HD_VER2
+    bool
+    default y
+
 config SOC_SPI_SUPPORT_CLK_XTAL
    bool
    default y
--- a/components/soc/esp32h21/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h
@ -237,13 +237,21 @@ typedef enum {
 /**
 * @brief Array initializer for all supported clock sources of SPI
 */
-#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M}
+#if SOC_CLK_TREE_SUPPORTED
+#define SOC_SPI_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL}
+#else
+#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL}
+#endif

 /**
 * @brief Type of SPI clock source.
 */
 typedef enum {
+#if SOC_CLK_TREE_SUPPORTED
    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,     /*!< Select PLL_48M as SPI source clock */
+#else
+    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as SPI source clock */
+#endif
    SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M,    /*!< Select PLL_48M as SPI source clock */
    SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,            /*!< Select XTAL as SPI source clock */
    SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,      /*!< Select RC_FAST as SPI source clock */
--- a/components/soc/esp32h21/include/soc/soc.h
+++ b/components/soc/esp32h21/include/soc/soc.h
@ -25,7 +25,6 @@
 #define DR_REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                       // only one I2S on H21
 #define DR_REG_TIMG_BASE(i)                        (DR_REG_TIMERG0_BASE + (i)*0x1000)
 #define DR_REG_SPI_MEM_BASE(i)                     (DR_REG_SPIMEM0_BASE + (i) * 0x1000)
-#define DR_REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))    // only one GPSPI
 #define DR_REG_I2C_BASE(i)                         (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)

 //Registers Operation {{
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@ -38,7 +38,7 @@
 #define SOC_RTC_MEM_SUPPORTED           1       //TODO: [ESP32H21] IDF-11548
 // #define SOC_I2S_SUPPORTED               1    //TODO: [ESP32H21] IDF-11606, IDF-11608
 // #define SOC_SDM_SUPPORTED               1    //TODO: [ESP32H21] IDF-11573
-// #define SOC_GPSPI_SUPPORTED             1    //TODO: [ESP32H21] IDF-11583, IDF-11584, IDF-11587
+#define SOC_GPSPI_SUPPORTED             1
 // #define SOC_LEDC_SUPPORTED              1    //TODO: [ESP32H21] IDF-11568
 #define SOC_I2C_SUPPORTED               1
 #define SOC_SYSTIMER_SUPPORTED          1       //TODO: [ESP32H21] IDF-11596, IDF-11598
@ -382,17 +382,16 @@
 #define SOC_SPI_PERIPH_NUM          2
 #define SOC_SPI_PERIPH_CS_NUM(i)    6
 #define SOC_SPI_MAX_CS_NUM          6
-
-#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
-
-#define SOC_SPI_SUPPORT_DDRCLK              1
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
 #define SOC_SPI_SUPPORT_CD_SIG              1
 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
-// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1 // TODO IDF-11587
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_SUPPORT_CLK_XTAL            1
+#if SOC_CLK_TREE_SUPPORTED  //TODO: [ESP32H21] IDF-11521
 #define SOC_SPI_SUPPORT_CLK_PLL_F48M        1
 #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
+#endif

 // Peripheral supports DIO, DOUT, QIO, or QOUT
 // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
@ -404,8 +403,8 @@
 #define SOC_SPI_SCT_BUFFER_NUM_MAX                (1 + SOC_SPI_SCT_REG_NUM)  //1-word-bitmap + 14-word-regs
 #define SOC_SPI_SCT_CONF_BITLEN_MAX               0x3FFFA       //18 bits wide reg

-#define SOC_MEMSPI_IS_INDEPENDENT 1
-#define SOC_SPI_MAX_PRE_DIVIDER 16
+#define SOC_MEMSPI_IS_INDEPENDENT           1
+#define SOC_SPI_MAX_PRE_DIVIDER             16

 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
--- a/components/soc/esp32h21/include/soc/spi_pins.h
+++ b/components/soc/esp32h21/include/soc/spi_pins.h
@ -18,11 +18,11 @@

 // GPSPI2 IOMUX PINs
 #define SPI2_FUNC_NUM               2
-#define SPI2_IOMUX_PIN_NUM_MISO     4
-#define SPI2_IOMUX_PIN_NUM_HD       1
 #define SPI2_IOMUX_PIN_NUM_WP       0
+#define SPI2_IOMUX_PIN_NUM_HD       1
 #define SPI2_IOMUX_PIN_NUM_CLK      2
 #define SPI2_IOMUX_PIN_NUM_MOSI     3
+#define SPI2_IOMUX_PIN_NUM_MISO     4
 #define SPI2_IOMUX_PIN_NUM_CS       12

 #endif
--- a/components/soc/esp32h21/include/soc/system_intr.h
+++ b/components/soc/esp32h21/include/soc/system_intr.h
@ -5,8 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_CPU_INTR_FROM_CPU_0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_CPU_INTR_FROM_CPU_1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_CPU_INTR_FROM_CPU_2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_CPU_INTR_FROM_CPU_3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_INTR_SOURCE
--- a/components/soc/esp32h21/register/soc/pcr_struct.h
+++ b/components/soc/esp32h21/register/soc/pcr_struct.h
@ -1059,7 +1059,7 @@ typedef union {
    struct {
        uint32_t reserved_0:20;
        /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  set this field to select clock-source. 0(default): XTAL, 1: 48MHz, 2: FOSC, 3:
         *  reserved.
         */
        uint32_t spi2_clkm_sel:2;
--- a/components/soc/esp32h21/register/soc/spi_reg.h
+++ b/components/soc/esp32h21/register/soc/spi_reg.h
@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0
 */
@ -7,14 +7,17 @@

 #include <stdint.h>
 #include "soc/soc.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif

+#define DR_REG_SPI_BASE(i)      (((i)==2) ? (DR_REG_GPSPI2_BASE) : (0))    // only one GPSPI
+
 /** SPI_CMD_REG register
 *  Command control register
 */
-#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0)
+#define SPI_CMD_REG(i) (DR_REG_SPI_BASE(i) + 0x0)
 /** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
 *  Configures the SPI_CLK cycles of SPI CONF state.
 *  Measurement unit: SPI_CLK clock cycle.
@ -50,7 +53,7 @@ extern "C" {
 /** SPI_ADDR_REG register
 *  Address value register
 */
-#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4)
+#define SPI_ADDR_REG(i) (DR_REG_SPI_BASE(i) + 0x4)
 /** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
 *  Configures the address to slave.
 *  Can be configured in CONF state.
@ -63,7 +66,7 @@ extern "C" {
 /** SPI_CTRL_REG register
 *  SPI control register
 */
-#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8)
+#define SPI_CTRL_REG(i) (DR_REG_SPI_BASE(i) + 0x8)
 /** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
 *  Configures whether or not to output the FSPI bus signals in DUMMY state.
 *  0: Not output
@ -232,7 +235,7 @@ extern "C" {
 /** SPI_CLOCK_REG register
 *  SPI clock control register
 */
-#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc)
+#define SPI_CLOCK_REG(i) (DR_REG_SPI_BASE(i) + 0xc)
 /** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
 *  In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it
 *  must be 0. Can be configured in CONF state.
@ -295,7 +298,7 @@ extern "C" {
 /** SPI_USER_REG register
 *  SPI USER control register
 */
-#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10)
+#define SPI_USER_REG(i) (DR_REG_SPI_BASE(i) + 0x10)
 /** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable full-duplex communication.
 *  0: Disable
@ -511,7 +514,7 @@ extern "C" {
 /** SPI_USER1_REG register
 *  SPI USER control register 1
 */
-#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14)
+#define SPI_USER1_REG(i) (DR_REG_SPI_BASE(i) + 0x14)
 /** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
 *  Configures the length of DUMMY state.
 *  Measurement unit: SPI_CLK clock cycles.
@ -562,7 +565,7 @@ extern "C" {
 /** SPI_USER2_REG register
 *  SPI USER control register 2
 */
-#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18)
+#define SPI_USER2_REG(i) (DR_REG_SPI_BASE(i) + 0x18)
 /** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
 *  Configures the command value.
 *  Can be configured in CONF state.
@ -593,7 +596,7 @@ extern "C" {
 /** SPI_MS_DLEN_REG register
 *  SPI data bit length control register
 */
-#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c)
+#define SPI_MS_DLEN_REG(i) (DR_REG_SPI_BASE(i) + 0x1c)
 /** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
 *  Configures the data bit length of SPI transfer in DMA-controlled master transfer or
 *  in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer
@ -608,7 +611,7 @@ extern "C" {
 /** SPI_MISC_REG register
 *  SPI misc register
 */
-#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20)
+#define SPI_MISC_REG(i) (DR_REG_SPI_BASE(i) + 0x20)
 /** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to disable SPI_CS$n pin.
 *  0: SPI_CS$n signal is from/to SPI_CS$n pin.
@ -773,7 +776,7 @@ extern "C" {
 /** SPI_DIN_MODE_REG register
 *  SPI input delay mode configuration
 */
-#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24)
+#define SPI_DIN_MODE_REG(i) (DR_REG_SPI_BASE(i) + 0x24)
 /** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures the input mode for FSPID signal.
 *  0: Input without delay
@ -882,7 +885,7 @@ extern "C" {
 /** SPI_DIN_NUM_REG register
 *  SPI input delay number configuration
 */
-#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28)
+#define SPI_DIN_NUM_REG(i) (DR_REG_SPI_BASE(i) + 0x28)
 /** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
 *  Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.
 *  0: Delayed by 1 clock cycle
@ -967,7 +970,7 @@ extern "C" {
 /** SPI_DOUT_MODE_REG register
 *  SPI output delay mode configuration
 */
-#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c)
+#define SPI_DOUT_MODE_REG(i) (DR_REG_SPI_BASE(i) + 0x2c)
 /** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
 *  Configures the output mode for FSPID signal.
 *  0: Output without delay
@ -1057,7 +1060,7 @@ extern "C" {
 /** SPI_DMA_CONF_REG register
 *  SPI DMA control register
 */
-#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30)
+#define SPI_DMA_CONF_REG(i) (DR_REG_SPI_BASE(i) + 0x30)
 /** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
 *  Represents whether or not the DMA TX FIFO is ready for sending data.
 *  0: Ready
@ -1178,7 +1181,7 @@ extern "C" {
 /** SPI_DMA_INT_ENA_REG register
 *  SPI interrupt enable register
 */
-#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34)
+#define SPI_DMA_INT_ENA_REG(i) (DR_REG_SPI_BASE(i) + 0x34)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@ -1330,7 +1333,7 @@ extern "C" {
 /** SPI_DMA_INT_CLR_REG register
 *  SPI interrupt clear register
 */
-#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38)
+#define SPI_DMA_INT_CLR_REG(i) (DR_REG_SPI_BASE(i) + 0x38)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
 *  Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@ -1482,7 +1485,7 @@ extern "C" {
 /** SPI_DMA_INT_RAW_REG register
 *  SPI interrupt raw register
 */
-#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c)
+#define SPI_DMA_INT_RAW_REG(i) (DR_REG_SPI_BASE(i) + 0x3c)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@ -1638,7 +1641,7 @@ extern "C" {
 /** SPI_DMA_INT_ST_REG register
 *  SPI interrupt status register
 */
-#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40)
+#define SPI_DMA_INT_ST_REG(i) (DR_REG_SPI_BASE(i) + 0x40)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
 *  The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@ -1790,7 +1793,7 @@ extern "C" {
 /** SPI_DMA_INT_SET_REG register
 *  SPI interrupt software set register
 */
-#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44)
+#define SPI_DMA_INT_SET_REG(i) (DR_REG_SPI_BASE(i) + 0x44)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
 *  Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@ -1942,7 +1945,7 @@ extern "C" {
 /** SPI_W0_REG register
 *  SPI CPU-controlled buffer0
 */
-#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98)
+#define SPI_W0_REG(i) (DR_REG_SPI_BASE(i) + 0x98)
 /** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -1954,7 +1957,7 @@ extern "C" {
 /** SPI_W1_REG register
 *  SPI CPU-controlled buffer1
 */
-#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c)
+#define SPI_W1_REG(i) (DR_REG_SPI_BASE(i) + 0x9c)
 /** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -1966,7 +1969,7 @@ extern "C" {
 /** SPI_W2_REG register
 *  SPI CPU-controlled buffer2
 */
-#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0)
+#define SPI_W2_REG(i) (DR_REG_SPI_BASE(i) + 0xa0)
 /** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -1978,7 +1981,7 @@ extern "C" {
 /** SPI_W3_REG register
 *  SPI CPU-controlled buffer3
 */
-#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4)
+#define SPI_W3_REG(i) (DR_REG_SPI_BASE(i) + 0xa4)
 /** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -1990,7 +1993,7 @@ extern "C" {
 /** SPI_W4_REG register
 *  SPI CPU-controlled buffer4
 */
-#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8)
+#define SPI_W4_REG(i) (DR_REG_SPI_BASE(i) + 0xa8)
 /** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2002,7 +2005,7 @@ extern "C" {
 /** SPI_W5_REG register
 *  SPI CPU-controlled buffer5
 */
-#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac)
+#define SPI_W5_REG(i) (DR_REG_SPI_BASE(i) + 0xac)
 /** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2014,7 +2017,7 @@ extern "C" {
 /** SPI_W6_REG register
 *  SPI CPU-controlled buffer6
 */
-#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0)
+#define SPI_W6_REG(i) (DR_REG_SPI_BASE(i) + 0xb0)
 /** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2026,7 +2029,7 @@ extern "C" {
 /** SPI_W7_REG register
 *  SPI CPU-controlled buffer7
 */
-#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4)
+#define SPI_W7_REG(i) (DR_REG_SPI_BASE(i) + 0xb4)
 /** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2038,7 +2041,7 @@ extern "C" {
 /** SPI_W8_REG register
 *  SPI CPU-controlled buffer8
 */
-#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8)
+#define SPI_W8_REG(i) (DR_REG_SPI_BASE(i) + 0xb8)
 /** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2050,7 +2053,7 @@ extern "C" {
 /** SPI_W9_REG register
 *  SPI CPU-controlled buffer9
 */
-#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc)
+#define SPI_W9_REG(i) (DR_REG_SPI_BASE(i) + 0xbc)
 /** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2062,7 +2065,7 @@ extern "C" {
 /** SPI_W10_REG register
 *  SPI CPU-controlled buffer10
 */
-#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0)
+#define SPI_W10_REG(i) (DR_REG_SPI_BASE(i) + 0xc0)
 /** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2074,7 +2077,7 @@ extern "C" {
 /** SPI_W11_REG register
 *  SPI CPU-controlled buffer11
 */
-#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4)
+#define SPI_W11_REG(i) (DR_REG_SPI_BASE(i) + 0xc4)
 /** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2086,7 +2089,7 @@ extern "C" {
 /** SPI_W12_REG register
 *  SPI CPU-controlled buffer12
 */
-#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8)
+#define SPI_W12_REG(i) (DR_REG_SPI_BASE(i) + 0xc8)
 /** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2098,7 +2101,7 @@ extern "C" {
 /** SPI_W13_REG register
 *  SPI CPU-controlled buffer13
 */
-#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc)
+#define SPI_W13_REG(i) (DR_REG_SPI_BASE(i) + 0xcc)
 /** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2110,7 +2113,7 @@ extern "C" {
 /** SPI_W14_REG register
 *  SPI CPU-controlled buffer14
 */
-#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0)
+#define SPI_W14_REG(i) (DR_REG_SPI_BASE(i) + 0xd0)
 /** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2122,7 +2125,7 @@ extern "C" {
 /** SPI_W15_REG register
 *  SPI CPU-controlled buffer15
 */
-#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4)
+#define SPI_W15_REG(i) (DR_REG_SPI_BASE(i) + 0xd4)
 /** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@ -2134,7 +2137,7 @@ extern "C" {
 /** SPI_SLAVE_REG register
 *  SPI slave control register
 */
-#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0)
+#define SPI_SLAVE_REG(i) (DR_REG_SPI_BASE(i) + 0xe0)
 /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures SPI clock mode.
 *  0: SPI clock is off when CS becomes inactive.
@ -2265,7 +2268,7 @@ extern "C" {
 /** SPI_SLAVE1_REG register
 *  SPI slave control register 1
 */
-#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4)
+#define SPI_SLAVE1_REG(i) (DR_REG_SPI_BASE(i) + 0xe4)
 /** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
 *  Configures the transferred data bit length in SPI slave full-/half-duplex modes.
 */
@ -2291,7 +2294,7 @@ extern "C" {
 /** SPI_CLK_GATE_REG register
 *  SPI module clock and register clock control
 */
-#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8)
+#define SPI_CLK_GATE_REG(i) (DR_REG_SPI_BASE(i) + 0xe8)
 /** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable clock gate.
 *  0: Disable
@ -2320,7 +2323,7 @@ extern "C" {
 /** SPI_DATE_REG register
 *  Version control
 */
-#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0)
+#define SPI_DATE_REG(i) (DR_REG_SPI_BASE(i) + 0xf0)
 /** SPI_DATE : R/W; bitpos: [27:0]; default: 37761424;
 *  Version control register.
 */
--- a/components/soc/esp32h21/spi_periph.c
+++ b/components/soc/esp32h21/spi_periph.c
@ -0,0 +1,85 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include "soc/spi_periph.h"
+
+/*
+ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
+    {
+        // MSPI has dedicated iomux pins
+    }, {
+        .spiclk_out = FSPICLK_OUT_IDX,
+        .spiclk_in = FSPICLK_IN_IDX,
+        .spid_out = FSPID_OUT_IDX,
+        .spiq_out = FSPIQ_OUT_IDX,
+        .spiwp_out = FSPIWP_OUT_IDX,
+        .spihd_out = FSPIHD_OUT_IDX,
+        .spid_in = FSPID_IN_IDX,
+        .spiq_in = FSPIQ_IN_IDX,
+        .spiwp_in = FSPIWP_IN_IDX,
+        .spihd_in = FSPIHD_IN_IDX,
+        .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
+        .spics_in = FSPICS0_IN_IDX,
+        .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
+        .irq = ETS_GPSPI2_INTR_SOURCE,
+        .irq_dma = -1,
+        .hw = &GPSPI2,
+        .func = SPI2_FUNC_NUM,
+    }
+};
+
+/**
+ * Backup registers in Light sleep: (total cnt 29)
+ *
+ * cmd
+ * addr
+ * ctrl
+ * clock
+ * user
+ * user1
+ * user2
+ * ms_dlen
+ * misc
+ * dma_conf
+ * dma_int_ena
+ * data_buf[0-15]   // slave driver only
+ * slave
+ * slave1
+ */
+#define SPI_RETENTION_REGS_CNT 29
+static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0};
+#define SPI_REG_RETENTION_ENTRIES(num) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
+                                               DR_REG_SPI_BASE(num), DR_REG_SPI_BASE(num), \
+                                               SPI_RETENTION_REGS_CNT, 0, 0, \
+                                               spi_regs_map[0], spi_regs_map[1], \
+                                               spi_regs_map[2], spi_regs_map[3]), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+    /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
+                                            SPI_DMA_INT_SET_REG(num), \
+                                            SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \
+                                            UINT32_MAX, 1, 0), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2);   // '2' for GPSPI2
+
+const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = {   // '-1' to except mspi
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI2,
+        .entry_array = spi2_regs_retention,
+        .array_size = ARRAY_SIZE(spi2_regs_retention),
+    },
+};
--- a/components/soc/esp32h4/include/soc/system_intr.h
+++ b/components/soc/esp32h4/include/soc/system_intr.h
@ -5,9 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_CPU_INTR_FROM_CPU_0_SOURCE
 #define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_CPU_INTR_FROM_CPU_1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_CPU_INTR_FROM_CPU_2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_CPU_INTR_FROM_CPU_3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_INTR_SOURCE
--- a/components/soc/esp32p4/include/soc/system_intr.h
+++ b/components/soc/esp32p4/include/soc/system_intr.h
@ -5,9 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
 #define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32s2/include/soc/system_intr.h
+++ b/components/soc/esp32s2/include/soc/system_intr.h
@ -5,8 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/components/soc/esp32s3/include/soc/system_intr.h
+++ b/components/soc/esp32s3/include/soc/system_intr.h
@ -5,9 +5,13 @@
 */
 #pragma once

+#include "soc/interrupts.h"
+
 // Maps misc system interrupt to hardware interrupt names
 #define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_FROM_CPU_INTR0_SOURCE
 #define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_FROM_CPU_INTR1_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_2_SOURCE  ETS_FROM_CPU_INTR2_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_3_SOURCE  ETS_FROM_CPU_INTR3_SOURCE

 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_LEVEL_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_LEVEL_INTR_SOURCE
--- a/docs/docs_not_updated/esp32h21.txt
+++ b/docs/docs_not_updated/esp32h21.txt
@ -91,7 +91,6 @@ api-reference/protocols/esp_sdio_slave_protocol.rst
 api-reference/protocols/esp_https_server.rst
 api-reference/protocols/esp_local_ctrl.rst
 api-reference/protocols/esp_tls.rst
-api-reference/protocols/esp_spi_slave_protocol.rst
 api-reference/protocols/esp_http_client.rst
 api-reference/protocols/mqtt.rst
 api-reference/protocols/esp_http_server.rst
@ -151,7 +150,6 @@ api-reference/peripherals/usb_host.rst
 api-reference/peripherals/clk_tree.rst
 api-reference/peripherals/camera_driver.rst
 api-reference/peripherals/touch_element.rst
-api-reference/peripherals/spi_master.rst
 api-reference/peripherals/adc_oneshot.rst
 api-reference/peripherals/twai.rst
 api-reference/peripherals/etm.rst
@ -161,7 +159,6 @@ api-reference/peripherals/i2c_slave_v1.rst
 api-reference/peripherals/adc_continuous.rst
 api-reference/peripherals/hmac.rst
 api-reference/peripherals/sdspi_host.rst
-api-reference/peripherals/spi_slave_hd.rst
 api-reference/peripherals/vad.rst
 api-reference/peripherals/i2s.rst
 api-reference/peripherals/isp.rst
@ -180,7 +177,6 @@ api-reference/peripherals/adc_calibration.rst
 api-reference/peripherals/lp_i2s.rst
 api-reference/peripherals/ecdsa.rst
 api-reference/peripherals/dac.rst
-api-reference/peripherals/spi_slave.rst
 api-reference/peripherals/spi_flash/index.rst
 api-reference/peripherals/spi_flash/spi_flash_concurrency.rst
 api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
--- a/docs/en/api-reference/peripherals/spi_master.rst
+++ b/docs/en/api-reference/peripherals/spi_master.rst
@ -481,12 +481,12 @@ GPIO Matrix and IO_MUX

 .. only:: not esp32

-    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8", esp32h21="12"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6", esp32h21="2"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7", esp32h21="3"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2", esp32h21="4"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3", esp32h21="1"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4", esp32h21="0"}

    Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.

@ -532,10 +532,10 @@ The main parameter that determines the transfer speed for large transactions is
 Transaction Duration
 ^^^^^^^^^^^^^^^^^^^^

-{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32"}
-{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9",  esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17"}
-{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29"}
-{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8",  esp32s2="8",  esp32c3="9",  esp32s3="9",  esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14"}
+{IDF_TARGET_MAX_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32"}
+{IDF_TARGET_MAX_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9",  esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17"}
+{IDF_TARGET_MAX_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29"}
+{IDF_TARGET_MAX_TRANS_TIME_POLL_CPU:default="N/A", esp32="8",  esp32s2="8",  esp32c3="9",  esp32s3="9",  esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14"}

 Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transactions.

@ -547,10 +547,10 @@ If DMA is enabled, setting up the linked list requires about 2 µs per transacti

 The typical transaction duration for one byte of data is given below.

- Interrupt Transaction via DMA: {IDF_TARGET_TRANS_TIME_INTR_DMA} µs.
- Interrupt Transaction via CPU: {IDF_TARGET_TRANS_TIME_INTR_CPU} µs.
- Polling Transaction via DMA: {IDF_TARGET_TRANS_TIME_POLL_DMA} µs.
- Polling Transaction via CPU: {IDF_TARGET_TRANS_TIME_POLL_CPU} µs.
+- Interrupt Transaction via DMA: {IDF_TARGET_MAX_TRANS_TIME_INTR_DMA} µs.
+- Interrupt Transaction via CPU: {IDF_TARGET_MAX_TRANS_TIME_INTR_CPU} µs.
+- Polling Transaction via DMA: {IDF_TARGET_MAX_TRANS_TIME_POLL_DMA} µs.
+- Polling Transaction via CPU: {IDF_TARGET_MAX_TRANS_TIME_POLL_CPU} µs.

 Note that these data are tested with :ref:`CONFIG_SPI_MASTER_ISR_IN_IRAM` enabled. SPI transaction related code are placed in the internal memory. If this option is turned off (for example, for internal memory optimization), the transaction duration may be affected.

--- a/docs/en/api-reference/peripherals/spi_slave.rst
+++ b/docs/en/api-reference/peripherals/spi_slave.rst
@ -154,12 +154,12 @@ GPIO Matrix and IO_MUX

 .. only:: not esp32

-    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8", esp32h21="12"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6", esp32h21="2"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7", esp32h21="3"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2", esp32h21="4"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3", esp32h21="1"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4", esp32h21="0"}

    Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.

--- a/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst
+++ b/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst
@ -14,21 +14,31 @@ ESP SPI Slave HD (Half Duplex) Mode Protocol
 SPI Slave Capabilities of Espressif Chips
 -----------------------------------------

-+------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-|                  | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-C5 | ESP32-C61 |
-+------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| SPI Slave HD     | N     | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)    |
-+------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| Tohost intr      |       | N        | N        | N        | N        | N        | N        | N        | N        | N         |
-+------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| Frhost intr      |       | 2 \*     | 2 \*     | 2 \*     | 2 \*     | 2 \*     | 2 \*     | 2 \*     | 2 \*     | 2 \*      |
-+------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| TX DMA           |       | Y        | Y        | Y        | Y        | Y        | Y        | Y        | Y        | Y         |
-+------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| RX DMA           |       | Y        | Y        | Y        | Y        | Y        | Y        | Y        | Y        | Y         |
-+------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| Shared registers |       | 72       | 64       | 64       | 64       | 64       | 64       | 64       | 64       | 64        |
-+------------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
+---------+------------+-----------+-----------+------+------+----------------+
+|         |SPI Slave HD|Tohost intr|Frhost intr|TX DMA|RX DMA|Shared registers|
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32    |     N      |           |           |      |      |                |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-S2 |   Y(v2)    |     N     |   2 \*    |  Y   |  Y   |       72       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C3 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-S3 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C2 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C6 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-H2 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-P4 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C5 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C61|   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-H21|   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+

 Introduction
 ------------
--- a/docs/zh_CN/api-reference/peripherals/spi_master.rst
+++ b/docs/zh_CN/api-reference/peripherals/spi_master.rst
@ -481,12 +481,12 @@ GPIO 矩阵与 IO_MUX 管脚

 .. only:: not esp32

-    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8", esp32h21="12"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6", esp32h21="2"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7", esp32h21="3"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2", esp32h21="4"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3", esp32h21="1"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4", esp32h21="0"}

    芯片的大多数外围信号都与之专用的 IO_MUX 管脚连接，但这些信号也可以通过较不直接的 GPIO 矩阵路由到任何其他可用的管脚。只要有一个信号是通过 GPIO 矩阵路由的，那么所有的信号都将通过它路由。

@ -532,10 +532,10 @@ GPIO 矩阵与 IO_MUX 管脚
 传输事务持续时间
 ^^^^^^^^^^^^^^^^^^^^

-{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32"}
-{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9",  esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17"}
-{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29"}
-{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8",  esp32s2="8",  esp32c3="9",  esp32s3="9",  esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14"}
+{IDF_TARGET_MAX_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32"}
+{IDF_TARGET_MAX_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9",  esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17"}
+{IDF_TARGET_MAX_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29"}
+{IDF_TARGET_MAX_TRANS_TIME_POLL_CPU:default="N/A", esp32="8",  esp32s2="8",  esp32c3="9",  esp32s3="9",  esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14"}

 传输事务持续时间包括设置 SPI 外设寄存器，将数据复制到 FIFO 或设置 DMA 链接，以及 SPI 传输事务时间。

@ -547,10 +547,10 @@ GPIO 矩阵与 IO_MUX 管脚

 单个字节数据的典型传输事务持续时间如下。

- 使用 DMA 的中断传输事务：{IDF_TARGET_TRANS_TIME_INTR_DMA} µs。
- 使用 CPU 的中断传输事务：{IDF_TARGET_TRANS_TIME_INTR_CPU} µs。
- 使用 DMA 的轮询传输事务：{IDF_TARGET_TRANS_TIME_POLL_DMA} µs。
- 使用 CPU 的轮询传输事务：{IDF_TARGET_TRANS_TIME_POLL_CPU} µs。
+- 使用 DMA 的中断传输事务：{IDF_TARGET_MAX_TRANS_TIME_INTR_DMA} µs。
+- 使用 CPU 的中断传输事务：{IDF_TARGET_MAX_TRANS_TIME_INTR_CPU} µs。
+- 使用 DMA 的轮询传输事务：{IDF_TARGET_MAX_TRANS_TIME_POLL_DMA} µs。
+- 使用 CPU 的轮询传输事务：{IDF_TARGET_MAX_TRANS_TIME_POLL_CPU} µs。

 请注意，以上数据测试时，:ref:`CONFIG_SPI_MASTER_ISR_IN_IRAM` 选项处于启用状态，SPI 传输事务相关的代码放置在 IRAM 中。若关闭此选项（例如为了节省 IRAM），可能影响传输事务持续时间。

--- a/docs/zh_CN/api-reference/peripherals/spi_slave.rst
+++ b/docs/zh_CN/api-reference/peripherals/spi_slave.rst
@ -154,12 +154,12 @@ GPIO 交换矩阵和 IO_MUX

 .. only:: not esp32

-    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8", esp32h21="12"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6", esp32h21="2"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7", esp32h21="3"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2", esp32h21="4"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3", esp32h21="1"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4", esp32h21="0"}

    {IDF_TARGET_NAME} 的大多数外设信号都直接连接到其专用的 IO_MUX 管脚。不过，也可以使用 GPIO 交换矩阵，将信号路由到任何可用的其他管脚。如果通过 GPIO 交换矩阵路由了至少一个信号，则所有信号都将通过 GPIO 交换矩阵路由。

--- a/docs/zh_CN/api-reference/protocols/esp_serial_slave_link.rst
+++ b/docs/zh_CN/api-reference/protocols/esp_serial_slave_link.rst
@ -6,7 +6,7 @@ ESP 串行从机链路
 概述
 ----

-乐鑫有多款芯片可用作从机的芯片。这些从机依赖于一些通用总线，并在总线上实现了各自的通信协议。 ``esp_serial_slave_link`` 组件能让主机通过总线驱动和相应的协议与 ESP 从机进行通信。
+乐鑫有多款芯片可用作从机。这些从机依赖于一些通用总线，并在总线上实现了各自的通信协议。 ``esp_serial_slave_link`` 组件能让主机通过总线驱动和相应的协议与 ESP 从机进行通信。

 ``esp_serial_slave_link`` 设备初始化完成后，应用程序就能通过它与 ESP 从机方便地通信。

--- a/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst
+++ b/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst
@ -14,21 +14,31 @@ ESP SPI 从机 HD（半双工）模式协议
 乐鑫芯片的 SPI 从机功能支持概况
 ---------------------------------

-+-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-|             | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-C5 | ESP32-C61 |
-+-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| SPI 从机 HD | N     | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)   | Y (v2)    |
-+-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| Tohost intr |       | N        | N        | N        | N        | N        | N        | N        | N        | N         |
-+-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| Frhost intr |       | 2 *      | 2 *      | 2 *      | 2 *      | 2 *      | 2 *      | 2 \*     | 2 \*     | 2 \*      |
-+-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| TX DMA      |       | Y        | Y        | Y        | Y        | Y        | Y        | Y        | Y        | Y         |
-+-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| RX DMA      |       | Y        | Y        | Y        | Y        | Y        | Y        | Y        | Y        | Y         |
-+-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
-| 共享寄存器  |       | 72       | 64       | 64       | 64       | 64       | 64       | 64       | 64       | 64        |
-+-------------+-------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+
+---------+------------+-----------+-----------+------+------+----------------+
+|         |SPI Slave HD|Tohost intr|Frhost intr|TX DMA|RX DMA|Shared registers|
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32    |     N      |           |           |      |      |                |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-S2 |   Y(v2)    |     N     |   2 \*    |  Y   |  Y   |       72       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C3 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-S3 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C2 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C6 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-H2 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-P4 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C5 |   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-C61|   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+
+|ESP32-H21|   Y(v2)    |     N     |   2 \*    |   Y  |  Y   |       64       |
+---------+------------+-----------+-----------+------+------+----------------+

 概述
 ----
--- a/examples/get-started/blink/README.md
+++ b/examples/get-started/blink/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 # Blink Example

--- a/examples/peripherals/lcd/spi_lcd_touch/README.md
+++ b/examples/peripherals/lcd/spi_lcd_touch/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 # SPI LCD and Touch Panel Example

--- a/examples/peripherals/lcd/tjpgd/README.md
+++ b/examples/peripherals/lcd/tjpgd/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 ## LCD tjpgd example

--- a/examples/peripherals/spi_master/hd_eeprom/README.md
+++ b/examples/peripherals/spi_master/hd_eeprom/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 ## SPI master half duplex EEPROM example

--- a/examples/peripherals/spi_master/lcd/README.md
+++ b/examples/peripherals/spi_master/lcd/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 # SPI Host Driver Example

--- a/examples/peripherals/spi_slave/README.md
+++ b/examples/peripherals/spi_slave/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 ## SPI slave example

--- a/examples/peripherals/spi_slave_hd/append_mode/master/README.md
+++ b/examples/peripherals/spi_slave_hd/append_mode/master/README.md
@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 See README.md in the parent directory
--- a/examples/peripherals/spi_slave_hd/append_mode/slave/README.md
+++ b/examples/peripherals/spi_slave_hd/append_mode/slave/README.md
@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 See README.md in the parent directory
--- a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md
+++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md
@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 See README.md in the parent directory
--- a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md
+++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md
@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
--- a/examples/storage/sd_card/sdspi/README.md
+++ b/examples/storage/sd_card/sdspi/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

 # SD Card example (SDSPI)