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change(mpll): use fast write as reg is 8bit

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Armando
2023-12-25 11:00:04 +08:00
parent 71202c701f
commit 58d222e66c
1 changed files with 1 additions and 3 deletions
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4
components/hal/esp32p4/include/hal/clk_tree_ll.h
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@@ -302,9 +302,7 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_
// MPLL_Freq = XTAL_Freq * (div + 1) / (ref_div + 1) // MPLL_Freq = XTAL_Freq * (div + 1) / (ref_div + 1)
uint8_t ref_div = 1; uint8_t ref_div = 1;
uint8_t div = mpll_freq_mhz / 20 - 1; uint8_t div = mpll_freq_mhz / 20 - 1;
uint8_t val = ((div << 3) | ref_div);
uint32_t val = REGI2C_READ(I2C_MPLL, I2C_MPLL_DIV_REG_ADDR);
val |= ((div << 3) | ref_div);
REGI2C_WRITE(I2C_MPLL, I2C_MPLL_DIV_REG_ADDR, val); REGI2C_WRITE(I2C_MPLL, I2C_MPLL_DIV_REG_ADDR, val);
} }