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Merge branch 'fix/fix_ota_slowclock_switching_v5.2' into 'release/v5.2'

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fix(esp_hw_support): fix rtc slow clock missing after the OTA app changes the slow clock source (v5.2)

See merge request espressif/esp-idf!34472
This commit is contained in:
Jiang Jiang Jian
2024-11-12 19:25:47 +08:00
parent 458fb6e018 b8e796cb67
commit 5c07af3ed7
5 changed files with 34 additions and 21 deletions
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11
components/esp_hw_support/port/esp32c6/pmu_param.c
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@@ -367,21 +367,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
/** LP system default parameter */
#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
# define PMU_SLOW_CLK_USE_EXT_XTAL (1)
#else
# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
#endif
#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.mem_dslp = 0, \
.peri_pd_en = 0, \
}, \
.clk_power = { \
.xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \
.xpd_rc32k = 0, \
.xpd_xtal32k = 1, \
.xpd_rc32k = 1, \
.xpd_fosc = 1, \
.pd_osc = 0 \
} \

11
components/esp_hw_support/port/esp32h2/pmu_param.c
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@@ -366,21 +366,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
/** LP system default parameter */
#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
# define PMU_SLOW_CLK_USE_EXT_XTAL (1)
#else
# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
#endif
#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.mem_dslp = 0, \
.peri_pd_en = 0, \
}, \
.clk_power = { \
.xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \
.xpd_rc32k = 0, \
.xpd_xtal32k = 1, \
.xpd_rc32k = 1, \
.xpd_fosc = 1, \
.pd_osc = 0 \
} \

11
components/esp_system/port/soc/esp32c6/clk.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -163,6 +163,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
}
rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
rtc_clk_rc32k_enable(false);
}
if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable.

11
components/esp_system/port/soc/esp32h2/clk.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -165,6 +165,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
}
rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
rtc_clk_rc32k_enable(false);
}
if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable.

11
components/esp_system/port/soc/esp32p4/clk.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -150,6 +150,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
}
rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
rtc_clk_rc32k_enable(false);
}
if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable.