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change(mcpwm): remove mcpwm on esp32c61

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mcpwm is not supported on esp32c61
This commit is contained in:
Chen Jichang
2024-07-15 20:24:55 +08:00
parent 46e6db0251
commit 5e0c5e0ba5
4 changed files with 0 additions and 63 deletions
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44
components/soc/esp32c61/include/soc/clk_tree_defs.h
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@@ -231,50 +231,6 @@ typedef enum {
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Carrier
*/
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum {
MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**

2
components/soc/esp32c61/include/soc/pmu_icg_mapping.h
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@@ -19,7 +19,6 @@
#define PMU_ICG_APB_ENA_PARL 23
#define PMU_ICG_APB_ENA_PCNT 20
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_APB_ENA_PWM 21
#define PMU_ICG_APB_ENA_REGDMA 24
#define PMU_ICG_APB_ENA_SARADC 9
#define PMU_ICG_APB_ENA_SEC 0
@@ -44,7 +43,6 @@
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_PWM 22
#define PMU_ICG_FUNC_ENA_SARADC 20
#define PMU_ICG_FUNC_ENA_SEC 19
#define PMU_ICG_FUNC_ENA_SPI2 1

16
components/soc/esp32c61/include/soc/soc_caps.h
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@@ -64,7 +64,6 @@
// \#define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9276
// \#define SOC_PCNT_SUPPORTED 0 //TODO: [ESP32C61] IDF-9332
// \#define SOC_MCPWM_SUPPORTED 0 //TODO: [ESP32C61] IDF-9338
// \#define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336
// \#define SOC_ETM_SUPPORTED 0
// \#define SOC_LP_CORE_SUPPORTED 0 //TODO: [ESP32C61] IDF-9331
@@ -298,21 +297,6 @@
// #define SOC_PCNT_THRES_POINT_PER_UNIT 2
// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
/*-------------------------- MCPWM CAPS --------------------------------------*/
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// \#define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395

1
docs/docs_not_updated/esp32c61.txt
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@@ -99,7 +99,6 @@ api-reference/peripherals/gptimer.rst
api-reference/peripherals/pcnt.rst
api-reference/peripherals/touch_element.rst
api-reference/peripherals/ppa.rst
api-reference/peripherals/mcpwm.rst
api-reference/peripherals/ana_cmpr.rst
api-reference/peripherals/camera_driver.rst
api-reference/peripherals/ledc.rst