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Merge branch 'refactor/enable_rtc_clk_test' into 'master'

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refactor(clk): enable rtc_clk ci test for all supported targets

Closes IDF-8973, IDF-10309, IDF-10984, and IDF-11022

See merge request espressif/esp-idf!38330
This commit is contained in:
Song Ruo Jing
2025-04-24 15:07:59 +08:00
parent 066f6263fe 1b3680eff3
commit 5f050afdc1
7 changed files with 142 additions and 121 deletions
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4
components/esp_hw_support/test_apps/.build-test-rules.yml
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@ -32,9 +32,7 @@ components/esp_hw_support/test_apps/rtc_8md256:
components/esp_hw_support/test_apps/rtc_clk:
disable:
- if: IDF_TARGET in ["esp32c6", "esp32h2", "esp32p4", "esp32c5", "esp32c61", "esp32h21", "esp32h4"]
temporary: true
reason: Unsupported on C6 for now. #TODO IDF-5645, TODO IDF-7514, TODO C5 IDF-8667, TODO C61 IDF-9274, TODO H21 IDF-11548 [ESP32H4] IDF-12313
- if: SOC_CLK_TREE_SUPPORTED != 1
components/esp_hw_support/test_apps/rtc_power_modes:
enable:

4
components/esp_hw_support/test_apps/rtc_clk/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

202
components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,15 +11,12 @@
#include "soc/soc_caps.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_reg.h"
#endif
#include "soc/gpio_periph.h"
#include "hal/gpio_ll.h"
#include "soc/io_mux_reg.h"
#include "driver/rtc_io.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
@ -28,19 +25,10 @@
#include "esp_sleep.h"
#include "esp_system.h"
#include "esp_private/esp_clk.h"
#include "esp_clk_tree.h"
#include "esp_rtc_time.h"
#include "rom/rtc.h"
// ESP32C2 does not support SLOW_CLK_32K_XTAL, so no need to test related test cases
// Please notice this when enabling the rtc_clk test for ESP32C2!
#if !CONFIG_IDF_TARGET_ESP32C2
extern void rtc_clk_select_rtc_slow_clk(void);
#endif
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2)
#define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk)
static uint32_t calibrate_one(rtc_cal_sel_t cal_clk, const char* name)
@ -59,55 +47,70 @@ static uint32_t calibrate_one(rtc_cal_sel_t cal_clk, const char* name)
TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]")
{
#if !CONFIG_IDF_TARGET_ESP32C2
// Need to enable xtal32k/osc_slow explicitly. Other slow clocks enable/disable can be controlled internally.
#if SOC_CLK_XTAL32K_SUPPORTED
rtc_clk_32k_enable(true);
#endif
rtc_clk_8m_enable(true, true);
// By default Kconfig, RTC_SLOW_CLK source is RC_SLOW
soc_rtc_slow_clk_src_t default_rtc_slow_clk_src = rtc_clk_slow_src_get();
CALIBRATE_ONE(RTC_CAL_RTC_MUX);
#if SOC_CLK_RC_FAST_D256_SUPPORTED
CALIBRATE_ONE(RTC_CAL_8MD256);
#endif
#if CONFIG_IDF_TARGET_ESP32C2
uint32_t cal_ext_slow_clk = CALIBRATE_ONE(RTC_CAL_32K_OSC_SLOW);
if (cal_ext_slow_clk == 0) {
printf("EXT CLOCK by PIN has not started up");
} else {
printf("switching to SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: ");
rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX);
CALIBRATE_ONE(RTC_CAL_8MD256);
CALIBRATE_ONE(RTC_CAL_32K_OSC_SLOW);
}
#else
#if SOC_CLK_XTAL32K_SUPPORTED
uint32_t cal_32k = CALIBRATE_ONE(RTC_CAL_32K_XTAL);
if (cal_32k == 0) {
printf("32K XTAL OSC has not started up");
printf("32K XTAL OSC has not started up\n");
} else {
printf("switching to SOC_RTC_SLOW_CLK_SRC_XTAL32K: ");
rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX);
#if SOC_CLK_RC_FAST_D256_SUPPORTED
CALIBRATE_ONE(RTC_CAL_8MD256);
#endif
CALIBRATE_ONE(RTC_CAL_32K_XTAL);
}
#endif
#if SOC_CLK_RC_FAST_D256_SUPPORTED
printf("switching to SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256: ");
rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256);
printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX);
CALIBRATE_ONE(RTC_CAL_8MD256);
#if CONFIG_IDF_TARGET_ESP32C2
CALIBRATE_ONE(RTC_CAL_32K_OSC_SLOW);
#else
#if SOC_CLK_XTAL32K_SUPPORTED
CALIBRATE_ONE(RTC_CAL_32K_XTAL);
#endif
#endif
#if SOC_CLK_OSC_SLOW_SUPPORTED
rtc_clk_32k_enable_external();
uint32_t cal_ext_slow_clk = CALIBRATE_ONE(RTC_CAL_32K_OSC_SLOW);
if (cal_ext_slow_clk == 0) {
printf("EXT CLOCK by PIN has not started up\n");
} else {
printf("switching to SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: ");
rtc_clk_slow_src_set(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX);
#if SOC_CLK_RC_FAST_D256_SUPPORTED
CALIBRATE_ONE(RTC_CAL_8MD256);
#endif
CALIBRATE_ONE(RTC_CAL_32K_OSC_SLOW);
}
#endif
// Set back to default source
rtc_clk_slow_src_set(default_rtc_slow_clk_src);
}
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#if SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
TEST_CASE("Test RTC_SLOW_CLK sources switching", "[rtc_clk]")
{
soc_rtc_slow_clk_src_t clk_src_before_switch = rtc_clk_slow_src_get();
@ -127,44 +130,22 @@ TEST_CASE("Test RTC_SLOW_CLK sources switching", "[rtc_clk]")
}
#endif
/* The following two are not unit tests, but are added here to make it easy to
* check the frequency of 150k/32k oscillators. The following two "tests" will
* output either 32k or 150k clock to GPIO25.
*/
static void pull_out_clk(int sel)
#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
TEST_CASE("Calculate RC_FAST clock frequency", "[rtc_clk]")
{
REG_SET_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M);
REG_CLR_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_RDE_M | RTC_IO_PDAC1_RUE_M);
REG_SET_FIELD(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_FUN_SEL, 1);
REG_SET_FIELD(SENS_SAR_DAC_CTRL1_REG, SENS_DEBUG_BIT_SEL, 0);
REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel);
}
TEST_CASE("Output 150k clock to GPIO25", "[ignore]")
{
pull_out_clk(RTC_IO_DEBUG_SEL0_150K_OSC);
}
TEST_CASE("Output 32k XTAL clock to GPIO25", "[ignore]")
{
rtc_clk_32k_enable(true);
pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL);
}
TEST_CASE("Output 8M XTAL clock to GPIO25", "[ignore]")
{
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_12M_NO_GATING);
pull_out_clk(RTC_IO_DEBUG_SEL0_8M);
uint32_t rc_fast_freq_hz;
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_RC_FAST, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &rc_fast_freq_hz);
printf("RC_FAST_CLK = %"PRIu32" Hz\n", rc_fast_freq_hz);
TEST_ASSERT_INT32_WITHIN((uint32_t)(SOC_CLK_RC_FAST_FREQ_APPROX * 0.15), SOC_CLK_RC_FAST_FREQ_APPROX, rc_fast_freq_hz);
}
#endif
static void test_clock_switching(void (*switch_func)(const rtc_cpu_freq_config_t* config))
{
esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
const int test_duration_sec = 10;
ref_clock_init();
esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
uint64_t t_start = ref_clock_get();
rtc_cpu_freq_config_t cur_config;
@ -184,15 +165,6 @@ static void test_clock_switching(void (*switch_func)(const rtc_cpu_freq_config_t
ref_clock_deinit();
}
TEST_CASE("Calculate 8M clock frequency", "[rtc_clk]")
{
// calibrate 8M/256 clock against XTAL, get 8M/256 clock period
uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100);
uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period;
printf("RTC_FAST_CLK=%"PRIu32" Hz\n", rtc_fast_freq_hz);
TEST_ASSERT_INT32_WITHIN(650000, SOC_CLK_RC_FAST_FREQ_APPROX, rtc_fast_freq_hz);
}
TEST_CASE("Test switching between PLL and XTAL", "[rtc_clk]")
{
test_clock_switching(rtc_clk_cpu_freq_set_config);
@ -203,6 +175,10 @@ TEST_CASE("Test fast switching between PLL and XTAL", "[rtc_clk]")
test_clock_switching(rtc_clk_cpu_freq_set_config_fast);
}
#if SOC_CLK_XTAL32K_SUPPORTED
extern void rtc_clk_select_rtc_slow_clk(void);
/* In CI environments, the 32kXTAL runners don't have 8MB psram for bank switching.
So can only test one config or the other. */
#if !defined(CONFIG_IDF_CI_BUILD) || !CONFIG_SPIRAM_BANKSWITCH_ENABLE
@ -211,20 +187,23 @@ TEST_CASE("Test fast switching between PLL and XTAL", "[rtc_clk]")
#define TIMEOUT_TEST_MS (5 + CONFIG_RTC_CLK_CAL_CYCLES / 16)
void stop_rtc_external_quartz(void){
const uint8_t pin_32 = 32;
const uint8_t pin_33 = 33;
#if CONFIG_IDF_TARGET_ESP32
const uint8_t pin_xtal32k_p = XTAL32K_P_GPIO_NUM;
const uint8_t pin_xtal32k_n = XTAL32K_N_GPIO_NUM;
rtc_clk_32k_enable(false);
esp_rom_gpio_pad_select_gpio(pin_32);
esp_rom_gpio_pad_select_gpio(pin_33);
gpio_ll_output_enable(&GPIO, pin_32);
gpio_ll_output_enable(&GPIO, pin_33);
gpio_ll_set_level(&GPIO, pin_32, 0);
gpio_ll_set_level(&GPIO, pin_33, 0);
esp_rom_gpio_pad_select_gpio(pin_xtal32k_p);
esp_rom_gpio_pad_select_gpio(pin_xtal32k_n);
gpio_ll_output_enable(&GPIO, pin_xtal32k_p);
gpio_ll_output_enable(&GPIO, pin_xtal32k_n);
gpio_ll_set_level(&GPIO, pin_xtal32k_p, 0);
gpio_ll_set_level(&GPIO, pin_xtal32k_n, 0);
esp_rom_delay_us(500000);
gpio_ll_output_disable(&GPIO, pin_32);
gpio_ll_output_disable(&GPIO, pin_33);
gpio_ll_output_disable(&GPIO, pin_xtal32k_p);
gpio_ll_output_disable(&GPIO, pin_xtal32k_n);
#endif
// Other targets no need to do bootstrap
}
static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay_ms)
@ -289,7 +268,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
printf("Test passed successfully\n");
}
TEST_CASE("Test starting external RTC quartz", "[test_env=xtal32k]")
TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=xtal32k]")
{
int i = 0, fail = 0;
uint32_t start_time;
@ -330,16 +309,16 @@ TEST_CASE("Test starting external RTC quartz", "[test_env=xtal32k]")
printf("Test passed successfully\n");
}
TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[test_env=xtal32k]")
TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[rtc_clk][test_env=xtal32k]")
{
start_freq(SOC_RTC_SLOW_CLK_SRC_XTAL32K, 200);
start_freq(SOC_RTC_SLOW_CLK_SRC_XTAL32K, 0);
}
TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[test_env=noXtal32k]")
TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_clk][test_env=noXtal32k]")
{
printf("Tries to start the 'External 32kHz XTAL' on the board without it. "
"Clock switching to 'Internal 150 kHz RC oscillator'.\n");
"Clock switching to 'Internal RC SLOW oscillator'.\n");
printf("This test will be successful for boards without an external crystal or non-working crystal. "
"First, there will be an attempt to start from the external crystal after a failure "
@ -351,8 +330,7 @@ TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[test
}
#endif // !defined(CONFIG_IDF_CI_BUILD) || !CONFIG_SPIRAM_BANKSWITCH_ENABLE
#endif // !TEMPORARY_DISABLED_FOR_TARGETS(...)
#endif // SOC_CLK_XTAL32K_SUPPORTED
TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]")
{
@ -381,6 +359,7 @@ TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]")
TEST_ASSERT_GREATER_THAN(t1, t2);
}
#if SOC_DEEP_SLEEP_SUPPORTED
static RTC_NOINIT_ATTR int64_t start = 0;
static void trigger_deepsleep(void)
@ -430,4 +409,41 @@ static void check_time_deepsleep_2(void)
TEST_ASSERT_GREATER_THAN(start, end);
}
TEST_CASE_MULTIPLE_STAGES("Test rtc clk calibration compensation across deep sleep", "", trigger_deepsleep, check_time_deepsleep_1, check_time_deepsleep_2);
TEST_CASE_MULTIPLE_STAGES("Test rtc clk calibration compensation across deep sleep", "[rtc_clk]", trigger_deepsleep, check_time_deepsleep_1, check_time_deepsleep_2);
#endif
/* The following three are not unit tests, but are added here to make it easy to
* check the frequency of 150k/32k/8M oscillators. The following three "tests" will
* output either 150k, 32k, 8M clock to GPIO25.
*/
#if CONFIG_IDF_TARGET_ESP32
#include "soc/sens_reg.h"
static void pull_out_clk(int sel)
{
REG_SET_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M);
REG_CLR_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_RDE_M | RTC_IO_PDAC1_RUE_M);
REG_SET_FIELD(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_FUN_SEL, 1);
REG_SET_FIELD(SENS_SAR_DAC_CTRL1_REG, SENS_DEBUG_BIT_SEL, 0);
REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel);
}
TEST_CASE("Output 150k clock to GPIO25", "[ignore]")
{
pull_out_clk(RTC_IO_DEBUG_SEL0_150K_OSC);
}
TEST_CASE("Output 32k XTAL clock to GPIO25", "[ignore]")
{
rtc_clk_32k_enable(true);
pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL);
}
TEST_CASE("Output 8M clock to GPIO25", "[ignore]")
{
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_12M_NO_GATING);
pull_out_clk(RTC_IO_DEBUG_SEL0_8M);
}
#endif

24
components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py
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@ -1,33 +1,35 @@
# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
from typing import Any
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf import CaseTester
from pytest_embedded_idf import IdfDut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
@pytest.mark.generic
@idf_parametrize('target', ['esp32'], indirect=['target'])
def test_rtc_clk(dut: Dut) -> None:
dut.run_all_single_board_cases(group='rtc_clk')
@idf_parametrize('target', soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1'), indirect=['target'])
def test_rtc_clk(case_tester: CaseTester) -> None:
for case in case_tester.test_menu:
if 'test_env' in case.attributes:
continue
case_tester.run_normal_case(case=case)
@pytest.mark.xtal32k
@idf_parametrize('target', ['esp32'], indirect=['target'])
def test_rtc_xtal32k(dut: Dut) -> None:
def test_rtc_xtal32k(dut: IdfDut) -> None:
dut.run_all_single_board_cases(attributes={'test_env': 'xtal32k'})
@pytest.mark.no32kXtal
@idf_parametrize('target', ['esp32'], indirect=['target'])
def test_rtc_no_xtal32k(dut: Dut) -> None:
def test_rtc_no_xtal32k(dut: IdfDut) -> None:
dut.run_all_single_board_cases(attributes={'test_env': 'noXtal32k'})
@pytest.mark.generic
# TODO: [ESP32P4] IDF-8973 [ESP32C5] IDF-10309 [ESP32C61] IDF-9274 IDF-10984
@pytest.mark.temp_skip_ci(targets=['esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], reason='support TBD')
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
def test_rtc_calib(case_tester: Any) -> None:
@idf_parametrize('target', soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1'), indirect=['target'])
def test_rtc_calib_compensation_across_dslp(case_tester: CaseTester) -> None:
case_tester.run_all_multi_stage_cases()

3
components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h
View File

@ -46,7 +46,7 @@ extern "C" {
* LP_AON_STORE1_REG RTC_SLOW_CLK calibration value
* LP_AON_STORE2_REG Boot time, low word
* LP_AON_STORE3_REG Boot time, high word
* LP_AON_STORE4_REG External XTAL frequency
* LP_AON_STORE4_REG Status of whether to disable LOG from ROM at bit[0]
* LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
@ -58,7 +58,6 @@ extern "C" {
#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG
#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG
#define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG
#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG
#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG

19
components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -43,27 +43,34 @@ extern "C" {
*
*************************************************************************************
* RTC store registers usage
* LP_AON_STORE0_REG Reserved
* LP_AON_STORE0_REG RTC fix us, high 32 bits
* LP_AON_STORE1_REG RTC_SLOW_CLK calibration value
* LP_AON_STORE2_REG Boot time, low word
* LP_AON_STORE3_REG Boot time, high word
* LP_AON_STORE4_REG External XTAL frequency
* LP_AON_STORE4_REG Status of whether to disable LOG from ROM at bit[0]
* LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
* LP_AON_STORE7_REG RTC fix us, low 32 bits
* LP_AON_STORE8_REG Store light sleep wake stub addr
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
*************************************************************************************
*
* Since esp32c61 does not support RTC mem, so use LP_AON store regs to record rtc time:
*
* |------------------------|----------------------------------------|
* | LP_AON_STORE0_REG | LP_AON_STORE7_REG |
* | rtc_fix_us(MSB) | rtc_fix_us(LSB) |
* |------------------------|----------------------------------------|
*/
#define RTC_FIX_US_HIGH_REG LP_AON_STORE0_REG
#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG
#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG
#define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG
#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG
#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG
#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG
#define RTC_FIX_US_LOW_REG LP_AON_STORE7_REG
#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG
#define RTC_SLEEP_MODE_REG LP_AON_STORE8_REG

7
components/hal/esp32c61/include/hal/clk_tree_ll.h
View File

@ -556,8 +556,8 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
*/
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us)
{
// TODO IDF-11022
return;
REG_WRITE(RTC_FIX_US_LOW_REG, rtc_fix_us);
REG_WRITE(RTC_FIX_US_HIGH_REG, rtc_fix_us >> 32);
}
/**
@ -567,8 +567,7 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_
*/
static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void)
{
// TODO IDF-11022
return 0;
return REG_READ(RTC_FIX_US_LOW_REG) | ((uint64_t)REG_READ(RTC_FIX_US_HIGH_REG) << 32);
}
#ifdef __cplusplus