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feat(esp32p4): Support newer Key Manager key sources for ESP32-P4 V3

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This commit is contained in:
harshal.patil
2025-10-09 12:05:32 +05:30
parent ab149384e1
commit 609d52c6bf
26 changed files with 605 additions and 705 deletions
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components/esp_rom/esp32p4/include/esp32p4/rom/key_mgr.h
+17 -9
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,9 +17,10 @@
extern "C" {
#endif
// store huk info, occupy 96 words
struct huk_info {
#define HUK_INFO_LEN 384
// store huk info, occupy 165 words
#define HUK_INFO_LEN 660
uint8_t info[HUK_INFO_LEN];
uint32_t crc;
} PACKED_ATTR;
@@ -35,8 +36,7 @@ struct huk_key_block {
#define KEY_HUK_SECTOR_MAGIC 0xDEA5CE5A
uint32_t magic;
uint32_t version; // for backward compatibility
uint8_t key_type;
uint8_t reserved[15];
uint8_t reserved[16];
struct huk_info huk_info;
struct key_info key_info[2]; // at most 2 key info (XTS-512_1 and XTS-512_2), at least use 1
} WORD_ALIGNED_ATTR PACKED_ATTR;
@@ -56,10 +56,18 @@ struct huk_key_block {
#define KM_PERI_XTS (BIT(1))
struct km_deploy_ops {
#define KM_KEY_PURPOSE_ECDSA 1
#define KM_KEY_PURPOSE_XTS_256_1 2
#define KM_KEY_PURPOSE_XTS_256_2 3
#define KM_KEY_PURPOSE_XTS_128 4
#define KM_KEY_PURPOSE_ECDSA_KEY_192 1
#define KM_KEY_PURPOSE_ECDSA_KEY_256 2
#define KM_KEY_PURPOSE_FLASH_XTS_256_1 3
#define KM_KEY_PURPOSE_FLASH_XTS_256_2 4
#define KM_KEY_PURPOSE_FLASH_XTS_128 5
#define KM_KEY_PURPOSE_HMAC 6
#define KM_KEY_PURPOSE_DS 7
#define KM_KEY_PURPOSE_PSRAM_XTS_256_1 8
#define KM_KEY_PURPOSE_PSRAM_XTS_256_2 9
#define KM_KEY_PURPOSE_PSRAM_XTS_128 10
#define KM_KEY_PURPOSE_ECDSA_KEY_384_L 11
#define KM_KEY_PURPOSE_ECDSA_KEY_384_H 12
int km_key_purpose;
#define KM_DEPLOY_MODE_RANDOM 0
#define KM_DEPLOY_MODE_AES 1
components/esp_security/src/esp_ds.c
+5
View File
@@ -40,6 +40,7 @@
#ifdef SOC_KEY_MANAGER_DS_KEY_DEPLOY
#include "hal/key_mgr_hal.h"
#include "hal/key_mgr_ll.h"
#endif
/**
@@ -326,6 +327,10 @@ esp_err_t esp_ds_start_sign(const void *message,
ds_acquire_enable();
#if SOC_KEY_MANAGER_DS_KEY_DEPLOY
if (!key_mgr_ll_is_supported()) {
assert(false && "Key manager is not supported");
}
if (key_id == HMAC_KEY_KM) {
key_mgr_hal_set_key_usage(ESP_KEY_MGR_DS_KEY, ESP_KEY_MGR_USE_OWN_KEY);
ds_hal_set_key_source(DS_KEY_SOURCE_KEY_MGR);
components/esp_security/src/esp_key_mgr.c
+2
View File
@@ -21,6 +21,7 @@
#include "hal/huk_hal.h"
#include "rom/key_mgr.h"
#if SOC_KEY_MANAGER_SUPPORTED
static const char *TAG = "esp_key_mgr";
static _lock_t s_key_mgr_ecdsa_key_lock;
@@ -914,3 +915,4 @@ esp_err_t esp_key_mgr_deploy_key_in_random_mode(const esp_key_mgr_random_key_con
return esp_ret;
}
#endif
components/esp_security/src/init.c
+6 -2
View File
@@ -29,13 +29,13 @@
__attribute__((unused)) static const char *TAG = "esp_security";
#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
static void esp_key_mgr_init(void)
{
// The following code initializes the key manager.
// When Flash Encryption is already enabled, Key Manager is initialized by the
// ROM, and when Flash Encryption is enabled during boot up, Key Manager is
// initialized by the bootloader.
#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
if (!efuse_hal_flash_encryption_enabled()) {
// Enable key manager clock
key_mgr_ll_power_up();
@@ -50,13 +50,17 @@ static void esp_key_mgr_init(void)
// Force Key Manager to use eFuse key by-default for an XTS-AES operation.
key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
}
#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
}
#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
{
esp_crypto_clk_init();
#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
esp_key_mgr_init();
#endif
#if CONFIG_ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP
esp_crypto_dpa_protection_startup();
#endif
components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt
+1 -1
View File
@@ -8,7 +8,7 @@ if(CONFIG_SOC_DIG_SIGN_SUPPORTED)
list(APPEND srcs "test_ds.c")
endif()
if(CONFIG_SOC_KEY_MANAGER_SUPPORTED)
if(CONFIG_ESP_SECURITY_IS_KEY_MANAGER_SUPPORTED)
list(APPEND srcs "test_key_mgr.c")
endif()
components/esp_security/test_apps/crypto_drivers/main/Kconfig.projbuild
+8
View File
@@ -6,4 +6,12 @@ menu "ESP Security Tests"
help
This includes the esp_security tests that actually require burning some efuses.
It is better to run these tests on an FPGA to avoid mistakenly burning eFuses.
config ESP_SECURITY_IS_KEY_MANAGER_SUPPORTED
bool
default n if IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3
default y
depends on SOC_KEY_MANAGER_SUPPORTED
help
A hidden config to determine if the Key Manager tests should be included.
endmenu
components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c
+4
View File
@@ -19,6 +19,9 @@
#include "esp_system.h"
#include "unity_test_utils_memory.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include "hal/key_mgr_ll.h"
#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
#include "esp_hmac.h"
#include "hmac_test_cases.h"
@@ -394,3 +397,4 @@ TEST_CASE("Key Manager random mode: DS key deployment", "[hw_crypto] [key_mgr]")
free(key_recovery_info);
}
#endif /* SOC_KEY_MANAGER_DS_KEY_DEPLOY */
#endif /* SOC_KEY_MANAGER_SUPPORTED */
components/hal/ds_hal.c
+2 -1
View File
@@ -7,6 +7,7 @@
#include "hal/systimer_hal.h"
#include "hal/ds_hal.h"
#include "hal/ds_ll.h"
#include "hal/assert.h"
#include "soc/soc_caps.h"
void ds_hal_start(void)
@@ -29,7 +30,7 @@ void ds_hal_set_key_source(ds_key_source_t key_source)
{
ds_ll_set_key_source(key_source);
}
#endif
#endif /* SOC_KEY_MANAGER_DS_KEY_DEPLOY */
void ds_hal_write_message(const uint8_t *msg, size_t size)
{
components/hal/ecdsa_hal.c
+6
View File
@@ -19,6 +19,7 @@
#ifdef SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
#include "hal/key_mgr_hal.h"
#include "hal/key_mgr_ll.h"
#endif
#define ECDSA_HAL_P192_COMPONENT_LEN 24
@@ -40,9 +41,14 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf)
{
if (conf->use_km_key == 0) {
ecdsa_hal_set_efuse_key(conf->curve, conf->efuse_key_blk);
#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
if (!key_mgr_ll_is_supported()) {
HAL_ASSERT(false && "Key manager is not supported");
}
// Force Key Manager to use eFuse key for XTS-AES operation
if (conf->curve == ECDSA_CURVE_SECP192R1) {
key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_192_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
components/hal/esp32c5/include/hal/key_mgr_ll.h
+9 -14
View File
@@ -206,7 +206,7 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ
}
break;
default:
HAL_ASSERT(false && "Unsupported mode");
HAL_ASSERT(false && "Unsupported key type");
return;
}
}
@@ -218,28 +218,23 @@ static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_t
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
break;
case ESP_KEY_MGR_HMAC_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
break;
case ESP_KEY_MGR_DS_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
break;
default:
HAL_ASSERT(false && "Unsupported mode");
HAL_ASSERT(false && "Unsupported key type");
return ESP_KEY_MGR_USAGE_INVALID;
}
return ESP_KEY_MGR_USAGE_INVALID;
@@ -288,7 +283,7 @@ static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_
break;
default:
HAL_ASSERT(false && "Unsupported mode");
HAL_ASSERT(false && "Unsupported key type");
return;
}
}
@@ -331,28 +326,23 @@ static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
case ESP_KEY_MGR_ECDSA_384_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
break;
case ESP_KEY_MGR_HMAC_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
break;
case ESP_KEY_MGR_DS_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
break;
default:
HAL_ASSERT(false && "Unsupported mode");
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
}
@@ -448,6 +438,11 @@ static inline uint32_t key_mgr_ll_get_date_info(void)
return (uint32_t)(0x0FFFFFFF & REG_READ(KEYMNG_DATE_REG));
}
static inline bool key_mgr_ll_is_supported(void)
{
return true;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32p4/include/hal/ds_ll.h
+11 -1
View File
@@ -19,7 +19,7 @@
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/soc_caps.h"
#include "hal/ds_types.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -95,6 +95,16 @@ static inline ds_key_check_t ds_ll_key_error_source(void)
}
}
/**
* @brief Set the DS key source.
*/
static inline void ds_ll_set_key_source(ds_key_source_t key_source)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
REG_WRITE(DS_KEY_SOURCE_REG, key_source);
#endif /* HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 */
}
/**
* @brief Write the initialization vector to the corresponding register field.
*/
components/hal/esp32p4/include/hal/key_mgr_ll.h
+135 -40
View File
@@ -19,12 +19,32 @@
#include "hal/key_mgr_types.h"
#include "soc/keymng_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
#endif
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300
#define KEYMNG_USE_EFUSE_KEY_FLASH KEYMNG_USE_EFUSE_KEY_XTS
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH KEYMNG_USE_EFUSE_KEY_LOCK_XTS
#define KEYMNG_KEY_FLASH_VLD KEYMNG_KEY_XTS_VLD
#define KEYMNG_KEY_FLASH_VLD_V KEYMNG_KEY_XTS_VLD_V
#define KEYMNG_KEY_FLASH_VLD_S KEYMNG_KEY_XTS_VLD_S
#define KEYMNG_KEY_ECDSA_192_VLD KEYMNG_KEY_ECDSA_VLD
#define KEYMNG_KEY_ECDSA_192_VLD_V KEYMNG_KEY_ECDSA_VLD_V
#define KEYMNG_KEY_ECDSA_192_VLD_S KEYMNG_KEY_ECDSA_VLD_S
#define KEYMNG_KEY_ECDSA_256_VLD KEYMNG_KEY_ECDSA_VLD
#define KEYMNG_KEY_ECDSA_256_VLD_V KEYMNG_KEY_ECDSA_VLD_V
#define KEYMNG_KEY_ECDSA_256_VLD_S KEYMNG_KEY_ECDSA_VLD_S
#define KEYMNG_KEY_ECDSA_384_VLD KEYMNG_KEY_ECDSA_VLD
#define KEYMNG_KEY_ECDSA_384_VLD_V KEYMNG_KEY_ECDSA_VLD_V
#define KEYMNG_KEY_ECDSA_384_VLD_S KEYMNG_KEY_ECDSA_VLD_S
#define KEYMNG_FLASH_KEY_LEN KEYMNG_XTS_AES_KEY_LEN
#define KEYMNG_FLASH_KEY_LEN_V KEYMNG_XTS_AES_KEY_LEN_V
#define KEYMNG_FLASH_KEY_LEN_S KEYMNG_XTS_AES_KEY_LEN_S
#endif
static inline void key_mgr_ll_power_up(void)
{
// TODO: IDF-13524
@@ -116,7 +136,6 @@ static inline void key_mgr_ll_continue(void)
REG_SET_BIT(KEYMNG_START_REG, KEYMNG_CONTINUE);
}
/* @brief Enable or Disable the KEY_MGR interrupts */
static inline void key_mgr_ll_configure_interrupt(const esp_key_mgr_interrupt_type_t intr, bool en)
{
@@ -153,7 +172,6 @@ static inline void key_mgr_ll_clear_int(const esp_key_mgr_interrupt_type_t intr)
}
}
/**
* @brief Set the key manager to use the software provided init key
*/
@@ -171,20 +189,48 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
}
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_XTS);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_XTS);
}
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
}
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
}
break;
case ESP_KEY_MGR_DS_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
}
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
}
break;
#endif
default:
HAL_ASSERT(false && "Unsupported mode");
return;
@@ -196,14 +242,28 @@ static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_t
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_XTS));
break;
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
break;
case ESP_KEY_MGR_DS_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
break;
#endif
default:
HAL_ASSERT(false && "Unsupported mode");
return ESP_KEY_MGR_USAGE_INVALID;
@@ -231,12 +291,28 @@ static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_
switch(key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_XTS);
break;
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC);
break;
case ESP_KEY_MGR_DS_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
break;
#endif
default:
HAL_ASSERT(false && "Unsupported key type");
return;
@@ -246,21 +322,7 @@ static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_
/* @brief Configure the key purpose to be used by the Key Manager for key generator operation */
static inline void key_mgr_ll_set_key_purpose(const esp_key_mgr_key_purpose_t key_purpose)
{
switch(key_purpose) {
case ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192:
case ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256:
REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, KEYMNG_KEY_PURPOSE_ECDSA);
break;
case ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1:
REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, KEYMNG_KEY_PURPOSE_XTS_AES_256_1);
break;
case ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2:
REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, KEYMNG_KEY_PURPOSE_XTS_AES_256_2);
break;
default:
HAL_ASSERT(false && "Unsupported mode");
return;
}
REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, key_purpose);
}
/**
@@ -289,17 +351,27 @@ static inline bool key_mgr_ll_is_result_success(void)
static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
case ESP_KEY_MGR_ECDSA_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_VLD);
break;
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
case ESP_KEY_MGR_ECDSA_384_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_XTS_VLD);
break;
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
case ESP_KEY_MGR_DS_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
#endif
default:
HAL_ASSERT(false && "Unsupported mode");
return 0;
@@ -367,17 +439,31 @@ static inline bool key_mgr_ll_is_huk_valid(void)
{
return REG_GET_FIELD(KEYMNG_HUK_VLD_REG, KEYMNG_HUK_VALID);
}
/* @brief Set the AES-XTS key length for the Key Manager */
static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_xts_aes_key_len_t key_len)
/* @brief Set the XTS-AES (Flash Encryption) key length for the Key Manager */
static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_xts_aes_key_len_t key_len)
{
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_XTS_AES_KEY_LEN, key_len);
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_XTS_AES_256_KEY) {
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN, key_len);
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
else if (key_type == ESP_KEY_MGR_PSRAM_128_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN, key_len);
}
#endif
}
/* @brief Get the AES-XTS key length for the Key Manager */
static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(void)
/* @brief Get the XTS-AES (Flash Encryption) key length for the Key Manager */
static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type)
{
return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_XTS_AES_KEY_LEN);
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_XTS_AES_256_KEY) {
return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN);
} else {
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN);
#else
HAL_ASSERT(false && "Unsupported key type");
#endif
}
}
/**
@@ -385,10 +471,19 @@ static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(void)
*/
static inline uint32_t key_mgr_ll_get_date_info(void)
{
// Only the lest siginificantt 28 bits have desired information
// Only the least significant 28 bits have desired information
return (uint32_t)(0x0FFFFFFF & REG_READ(KEYMNG_DATE_REG));
}
static inline bool key_mgr_ll_is_supported(void)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300
return false;
#else
return true;
#endif
}
#ifdef __cplusplus
}
#endif
components/hal/hmac_hal.c
+6
View File
@@ -7,10 +7,12 @@
#include "stdio.h"
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
#include "hal/assert.h"
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
#include "hal/key_mgr_hal.h"
#include "hal/key_mgr_ll.h"
#endif
void hmac_hal_start(void)
@@ -26,6 +28,10 @@ uint32_t hmac_hal_configure(hmac_hal_output_t config, uint32_t key_id)
#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
if (key_id == HMAC_KEY_KM) {
if (!key_mgr_ll_is_supported()) {
HAL_ASSERT(false && "Key manager is not supported");
}
if (config == HMAC_OUTPUT_USER) {
key_mgr_hal_set_key_usage(ESP_KEY_MGR_HMAC_KEY, ESP_KEY_MGR_USE_OWN_KEY);
} else {
components/hal/huk_hal.c
+2
View File
@@ -15,6 +15,7 @@
#include "esp_err.h"
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
esp_huk_state_t huk_hal_get_state(void)
{
return huk_ll_get_state();
@@ -52,3 +53,4 @@ void huk_hal_recharge_huk_memory(void)
huk_ll_recharge_huk_memory();
}
#endif
#endif
components/hal/test_apps/crypto/CMakeLists.txt
-2
View File
@@ -1,7 +1,5 @@
cmake_minimum_required(VERSION 3.22)
set(COMPONENTS main)
set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/test_apps/components")
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
components/hal/test_apps/crypto/main/CMakeLists.txt
+1 -1
View File
@@ -21,7 +21,7 @@ if(CONFIG_SOC_ECDSA_SUPPORTED)
list(APPEND srcs "ecdsa/test_ecdsa.c")
endif()
if(CONFIG_SOC_KEY_MANAGER_SUPPORTED)
if(CONFIG_CRYPTO_IS_KEY_MANAGER_SUPPORTED)
list(APPEND srcs "key_manager/test_key_manager.c"
"$ENV{IDF_PATH}/components/esp_security/src/esp_key_mgr.c")
list(APPEND priv_include_dirs "$ENV{IDF_PATH}/components/esp_security/include")
components/hal/test_apps/crypto/main/Kconfig.projbuild
+9 -1
View File
@@ -37,9 +37,17 @@ menu "Test App Configuration"
config CRYPTO_TESTAPP_USE_AES_INTERRUPT
bool "Use interrupt for long AES operations"
depends on SOC_AES_SUPPORTED
depends on SOC_AES_SUPPORTED
default n
help
Use an interrupt to coordinate long AES operations.
config CRYPTO_IS_KEY_MANAGER_SUPPORTED
bool
default n if IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3
default y
depends on SOC_KEY_MANAGER_SUPPORTED
help
A hidden config to determine if the Key Manager tests should be included.
endmenu
components/hal/test_apps/crypto/main/app_main.c
+2 -1
View File
@@ -6,6 +6,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "sdkconfig.h"
#include "unity.h"
#include "unity_fixture.h"
#include "unity_fixture_extras.h"
@@ -30,7 +31,7 @@ static void run_all_tests(void)
#endif /* !CONFIG_SOC_SHA_SUPPORT_PARALLEL_ENG*/
#endif
#if CONFIG_SOC_KEY_MANAGER_SUPPORTED
#if CONFIG_CRYPTO_IS_KEY_MANAGER_SUPPORTED
RUN_TEST_GROUP(key_manager);
#endif
components/hal/test_apps/crypto/main/ds/test_ds.c
+4
View File
@@ -93,6 +93,10 @@ static esp_err_t esp_ds_start_sign(const void *message, const esp_ds_data_t *dat
#if SOC_KEY_MANAGER_DS_KEY_DEPLOY
if (key_id == HMAC_KEY_KM) {
if (!key_mgr_ll_is_supported()) {
HAL_ASSERT(false && "Key manager is not supported");
}
ds_hal_set_key_source(DS_KEY_SOURCE_KEY_MGR);
} else {
ds_hal_set_key_source(DS_KEY_SOURCE_EFUSE);
components/hal/test_apps/crypto/main/key_manager/gen_key_manager_test_cases.py
+123 -139
View File
@@ -148,11 +148,11 @@ def generate_k1_G(key_file_path: str) -> tuple:
def generate_hmac_test_data(key: bytes) -> tuple:
hmac_message = (
'Deleniti voluptas explicabo et assumenda. Sed et aliquid minus quis. '
'Praesentium cupiditate quia nemo est. Laboriosam pariatur ut distinctio tenetur. '
'Sunt architecto iure aspernatur soluta ut recusandae. '
'Ut quibusdam occaecati ut qui sit dignissimos eaque..'
).encode('utf-8')
b'Deleniti voluptas explicabo et assumenda. Sed et aliquid minus quis. '
b'Praesentium cupiditate quia nemo est. Laboriosam pariatur ut distinctio tenetur. '
b'Sunt architecto iure aspernatur soluta ut recusandae. '
b'Ut quibusdam occaecati ut qui sit dignissimos eaque..'
)
hmac_result = hmac.HMAC(key, hmac_message, hashlib.sha256).digest()
return hmac_message, hmac_result
@@ -179,22 +179,18 @@ def number_as_bignum_words(number): # type: (int) -> str
return '{ ' + ', '.join(result) + ' }'
def generate_ds_encrypted_input_params(aes_key: bytes, target: str) -> tuple:
iv = os.urandom(16)
max_key_size = max(supported_ds_key_size[target])
key_size = max_key_size
private_key = rsa.generate_private_key(public_exponent=65537, key_size=key_size, backend=default_backend())
def generate_ds_encrypted_input_params(aes_key: bytes, max_key_size: int, iv: bytes) -> tuple:
private_key = rsa.generate_private_key(public_exponent=65537, key_size=max_key_size, backend=default_backend())
priv_numbers = private_key.private_numbers()
pub_numbers = private_key.public_key().public_numbers()
Y = priv_numbers.d
M = pub_numbers.n
rr = 1 << (key_size * 2)
rr = 1 << (max_key_size * 2)
rinv = rr % pub_numbers.n
mprime = -rsa._modinv(M, 1 << 32)
mprime &= 0xFFFFFFFF
length = key_size // 32 - 1
length = max_key_size // 32 - 1
# calculate MD from preceding values and IV
# Y_max_key_size || M_max_key_size || Rb_max_key_size || M_prime32 || LENGTH32 || IV128
@@ -230,12 +226,12 @@ def generate_ds_encrypted_input_params(aes_key: bytes, target: str) -> tuple:
encryptor = cipher.encryptor()
ds_encrypted_input_params = encryptor.update(p) + encryptor.finalize()
mask = (1 << key_size) - 1 # truncate messages if needed
mask = (1 << max_key_size) - 1 # truncate messages if needed
ds_message = random.randrange(0, 1 << max_key_size)
ds_result = number_as_bytes(pow(ds_message & mask, Y, M))
return number_as_bytes(ds_message), ds_encrypted_input_params, iv, key_size, ds_result
return number_as_bytes(ds_message), ds_encrypted_input_params, ds_result
def write_to_c_header(
@@ -254,77 +250,77 @@ def write_to_c_header(
k1_G_1: bytes,
hmac_message: bytes,
hmac_result: bytes,
ds_message: bytes,
ds_encrypted_input_params: bytes,
ds_encrypted_input_params_iv: bytes,
ds_key_size: int,
ds_result: bytes,
ds_message_4096: bytes,
ds_encrypted_input_params_4096: bytes,
ds_result_4096: bytes,
ds_message_3072: bytes,
ds_encrypted_input_params_3072: bytes,
ds_result_3072: bytes,
ds_iv: bytes,
) -> None:
with open('key_manager_test_cases.h', 'w', encoding='utf-8') as file:
header_content = """#include <stdint.h>
header_content = f"""#include <stdint.h>
#include "soc/soc_caps.h"
#define TEST_COUNT 5
typedef struct test_xts_data {
typedef struct test_xts_data {{
uint16_t data_size;
uint32_t data_offset;
uint8_t ciphertext[128];
} test_xts_data_t;
}} test_xts_data_t;
typedef struct test_ecdsa_data {
typedef struct test_ecdsa_data {{
uint8_t pubx[32];
uint8_t puby[32];
} test_ecdsa_data_t;
}} test_ecdsa_data_t;
typedef struct test_hmac_data {
uint8_t message[%d];
typedef struct test_hmac_data {{
uint8_t message[{len(hmac_message)}];
uint8_t hmac_result[32];
} test_hmac_data_t;
}} test_hmac_data_t;
typedef struct test_ds_data {
uint8_t ds_message[%d / 8];
uint8_t ds_encrypted_input_params[%d];
uint8_t ds_encrypted_input_params_iv[16];
typedef struct test_ds_data {{
#if SOC_RSA_MAX_BIT_LEN == 4096
uint8_t ds_message[4096 / 8];
uint8_t ds_encrypted_input_params[1584];
uint8_t ds_result[4096 / 8];
#elif SOC_RSA_MAX_BIT_LEN == 3072
uint8_t ds_message[3072 / 8];
uint8_t ds_encrypted_input_params[1200];
uint8_t ds_result[3072 / 8];
#endif
size_t ds_key_size;
uint8_t ds_result[%d];
} test_ds_data_t;
uint8_t ds_encrypted_input_params_iv[16];
}} test_ds_data_t;
typedef struct test_data {
typedef struct test_data {{
uint8_t init_key[32];
uint8_t k2_info[64];
uint8_t k1_encrypted[2][32]; // For both 256-bit and 512-bit keys
uint8_t plaintext_data[128];
union {
union {{
test_xts_data_t xts_test_data[TEST_COUNT];
test_ecdsa_data_t ecdsa_test_data;
test_hmac_data_t hmac_test_data;
test_ds_data_t ds_test_data;
};
} test_data_aes_mode_t;
}};
}} test_data_aes_mode_t;
typedef struct test_data_ecdh0 {
typedef struct test_data_ecdh0 {{
uint8_t plaintext_data[128];
uint8_t k1[2][32];
uint8_t k1_G[2][64];
} test_data_ecdh0_mode_t;
}} test_data_ecdh0_mode_t;
// For 32-byte k1 key
test_data_aes_mode_t test_data_xts_aes_128 = {
.init_key = { %s },
.k2_info = { %s },
.k1_encrypted = { { %s }, { } },
.plaintext_data = { %s },
.xts_test_data = {
""" % (
len(hmac_message),
ds_key_size,
len(ds_encrypted_input_params),
len(ds_result),
key_to_c_format(init_key),
key_to_c_format(k2_info),
key_to_c_format(k1_encrypted_32_reversed[0]),
key_to_c_format(bytes(range(1, 129))),
)
test_data_aes_mode_t test_data_xts_aes_128 = {{
.init_key = {{ {key_to_c_format(init_key)} }},
.k2_info = {{ {key_to_c_format(k2_info)} }},
.k1_encrypted = {{ {{ {key_to_c_format(k1_encrypted_32_reversed[0])} }}, {{ }} }},
.plaintext_data = {{ {key_to_c_format(bytes(range(1, 129)))} }},
.xts_test_data = {{
"""
for data_size, flash_address, ciphertext in test_data_xts_aes_128:
header_content += (
@@ -354,85 +350,65 @@ test_data_aes_mode_t test_data_xts_aes_128 = {
)
header_content += '\t}\n};\n'
header_content += """
test_data_aes_mode_t test_data_ecdsa = {
.init_key = { %s },
.k2_info = { %s },
.k1_encrypted = { { %s }, { } },
.ecdsa_test_data = {
.pubx = { %s },
.puby = { %s }
}
};\n
""" % (
key_to_c_format(init_key),
key_to_c_format(k2_info),
key_to_c_format(k1_encrypted_32_reversed[0]),
key_to_c_format(pubx),
key_to_c_format(puby),
)
header_content += f"""
test_data_aes_mode_t test_data_ecdsa = {{
.init_key = {{ {key_to_c_format(init_key)} }},
.k2_info = {{ {key_to_c_format(k2_info)} }},
.k1_encrypted = {{ {{ {key_to_c_format(k1_encrypted_32_reversed[0])} }}, {{ }} }},
.ecdsa_test_data = {{
.pubx = {{ {key_to_c_format(pubx)} }},
.puby = {{ {key_to_c_format(puby)} }}
}}
}};
"""
header_content += """
test_data_ecdh0_mode_t test_data_ecdh0 = {
.plaintext_data = { %s },
.k1 = {
{ %s },
{ %s },
},
.k1_G = {
{ %s },
{ %s },
}
};\n
""" % (
key_to_c_format(bytes(range(1, 129))),
key_to_c_format(k1),
key_to_c_format(k1),
key_to_c_format(k1_G_0),
key_to_c_format(k1_G_1),
)
header_content += f"""
test_data_ecdh0_mode_t test_data_ecdh0 = {{
.plaintext_data = {{ {key_to_c_format(bytes(range(1, 129)))} }},
.k1 = {{
{{ {key_to_c_format(k1)} }},
{{ {key_to_c_format(k1)} }},
}},
.k1_G = {{
{{ {key_to_c_format(k1_G_0)} }},
{{ {key_to_c_format(k1_G_1)} }},
}}
}};
"""
header_content += """
test_data_aes_mode_t test_data_hmac = {
.init_key = { %s },
.k2_info = { %s },
.k1_encrypted = { { %s }, { } },
.hmac_test_data = {
.message = { %s },
.hmac_result = { %s }
}
};\n
""" % (
key_to_c_format(init_key),
key_to_c_format(k2_info),
key_to_c_format(k1_encrypted_32[0]),
key_to_c_format(hmac_message),
key_to_c_format(hmac_result),
)
header_content += f"""
test_data_aes_mode_t test_data_hmac = {{
.init_key = {{ {key_to_c_format(init_key)} }},
.k2_info = {{ {key_to_c_format(k2_info)} }},
.k1_encrypted = {{ {{ {key_to_c_format(k1_encrypted_32[0])} }}, {{ }} }},
.hmac_test_data = {{
.message = {{ {key_to_c_format(hmac_message)} }},
.hmac_result = {{ {key_to_c_format(hmac_result)} }}
}}
}};
"""
header_content += """
test_data_aes_mode_t test_data_ds = {
.init_key = { %s },
.k2_info = { %s },
.k1_encrypted = { { %s }, { } },
.ds_test_data = {
.ds_message = { %s },
.ds_encrypted_input_params = { %s },
.ds_encrypted_input_params_iv = { %s },
.ds_key_size = %d,
.ds_result = { %s }
}
};\n
""" % (
key_to_c_format(init_key),
key_to_c_format(k2_info),
key_to_c_format(k1_encrypted_32_reversed[0]),
key_to_c_format(ds_message),
key_to_c_format(ds_encrypted_input_params),
key_to_c_format(ds_encrypted_input_params_iv),
ds_key_size,
key_to_c_format(ds_result),
)
header_content += f"""
test_data_aes_mode_t test_data_ds = {{
.init_key = {{ {key_to_c_format(init_key)} }},
.k2_info = {{ {key_to_c_format(k2_info)} }},
.k1_encrypted = {{ {{ {key_to_c_format(k1_encrypted_32_reversed[0])} }}, {{ }} }},
.ds_test_data = {{
#if SOC_DS_SIGNATURE_MAX_BIT_LEN == 4096
.ds_message = {{ {key_to_c_format(ds_message_4096)} }},
.ds_encrypted_input_params = {{ {key_to_c_format(ds_encrypted_input_params_4096)} }},
.ds_key_size = 4096,
.ds_result = {{ {key_to_c_format(ds_result_4096)} }},
#elif SOC_DS_SIGNATURE_MAX_BIT_LEN == 3072
.ds_message = {{ {key_to_c_format(ds_message_3072)} }},
.ds_encrypted_input_params = {{ {key_to_c_format(ds_encrypted_input_params_3072)} }},
.ds_key_size = 3072,
.ds_result = {{ {key_to_c_format(ds_result_3072)} }},
#endif
.ds_encrypted_input_params_iv = {{ {key_to_c_format(ds_iv)} }},
}},
}};
"""
file.write(header_content)
@@ -472,8 +448,14 @@ def generate_tests_cases(target: str) -> None:
hmac_message, hmac_result = generate_hmac_test_data(k1_32)
ds_message, ds_encrypted_input_params, ds_encrypted_input_params_iv, ds_key_size, ds_result = (
generate_ds_encrypted_input_params(k1_32, target)
ds_iv = os.urandom(16)
ds_message_4096, ds_encrypted_input_params_4096, ds_result_4096 = generate_ds_encrypted_input_params(
k1_32, 4096, ds_iv
)
ds_message_3072, ds_encrypted_input_params_3072, ds_result_3072 = generate_ds_encrypted_input_params(
k1_32, 3072, ds_iv
)
write_to_c_header(
@@ -492,11 +474,13 @@ def generate_tests_cases(target: str) -> None:
k1_G_1,
hmac_message,
hmac_result,
ds_message,
ds_encrypted_input_params,
ds_encrypted_input_params_iv,
ds_key_size,
ds_result,
ds_message_4096,
ds_encrypted_input_params_4096,
ds_result_4096,
ds_message_3072,
ds_encrypted_input_params_3072,
ds_result_3072,
ds_iv,
)
components/hal/test_apps/crypto/main/key_manager/key_manager_test_cases.h
+21 -10
View File
File diff suppressed because one or more lines are too long
components/mbedtls/test_apps/main/test_mbedtls_ecdsa.c
+21
View File
@@ -28,6 +28,7 @@
#include "ecdsa/ecdsa_alt.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include "esp_key_mgr.h"
#include "hal/key_mgr_ll.h"
#endif
#if SOC_ECDSA_SUPPORTED
@@ -409,6 +410,10 @@ static void deploy_key_in_key_manager(const uint8_t *k1_encrypted, esp_key_mgr_k
TEST_CASE("mbedtls ECDSA signature generation on SECP192R1", "[mbedtls][key_manager_key]")
{
if (!key_mgr_ll_is_supported()) {
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_192_KEY);
test_ecdsa_sign(MBEDTLS_ECP_DP_SECP192R1, sha, ecdsa192_sign_pub_x, ecdsa192_sign_pub_y, false, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_192_KEY);
@@ -416,6 +421,10 @@ TEST_CASE("mbedtls ECDSA signature generation on SECP192R1", "[mbedtls][key_mana
TEST_CASE("mbedtls ECDSA signature generation on SECP256R1", "[mbedtls][key_manager_key]")
{
if (!key_mgr_ll_is_supported()) {
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_256_KEY);
test_ecdsa_sign(MBEDTLS_ECP_DP_SECP256R1, sha, ecdsa256_sign_pub_x, ecdsa256_sign_pub_y, false, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_256_KEY);
@@ -452,6 +461,10 @@ TEST_CASE("mbedtls ECDSA deterministic signature generation on SECP384R1", "[mbe
#if SOC_KEY_MANAGER_SUPPORTED
TEST_CASE("mbedtls ECDSA deterministic signature generation on SECP192R1", "[mbedtls][key_manager_key]")
{
if (!key_mgr_ll_is_supported()) {
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
if (!ecdsa_ll_is_deterministic_mode_supported()) {
ESP_LOGI(TAG, "Skipping test because ECDSA deterministic mode is not supported.");
} else {
@@ -540,6 +553,10 @@ TEST_CASE("mbedtls ECDSA export public key on SECP384R1", "[mbedtls][efuse_key]"
#if SOC_KEY_MANAGER_SUPPORTED
TEST_CASE("mbedtls ECDSA export public key on SECP192R1", "[mbedtls][key_manager_key]")
{
if (!key_mgr_ll_is_supported()) {
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_192_KEY);
test_ecdsa_export_pubkey(MBEDTLS_ECP_DP_SECP192R1, ecdsa192_sign_pub_x, ecdsa192_sign_pub_y, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_192_KEY);
@@ -547,6 +564,10 @@ TEST_CASE("mbedtls ECDSA export public key on SECP192R1", "[mbedtls][key_manager
TEST_CASE("mbedtls ECDSA export public key on SECP256R1", "[mbedtls][key_manager_key]")
{
if (!key_mgr_ll_is_supported()) {
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_256_KEY);
test_ecdsa_export_pubkey(MBEDTLS_ECP_DP_SECP256R1, ecdsa256_sign_pub_x, ecdsa256_sign_pub_y, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_256_KEY);
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+14 -2
View File
@@ -209,7 +209,11 @@ config SOC_ECDSA_SUPPORTED
config SOC_KEY_MANAGER_SUPPORTED
bool
default n
default y
config SOC_HUK_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED
bool
@@ -1753,7 +1757,7 @@ config SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
bool
default y
default n
config SOC_KEY_MANAGER_FE_KEY_DEPLOY
bool
@@ -1767,6 +1771,14 @@ config SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
bool
default y
config SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
bool
default y
config SOC_KEY_MANAGER_DS_KEY_DEPLOY
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+6 -3
View File
@@ -73,8 +73,9 @@
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_ECC_SUPPORTED 1
#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
#define SOC_ECDSA_SUPPORTED 0
#define SOC_KEY_MANAGER_SUPPORTED 0
#define SOC_ECDSA_SUPPORTED 0 // TODO: IDF-13523
#define SOC_KEY_MANAGER_SUPPORTED 1
#define SOC_HUK_SUPPORTED 1
#define SOC_FLASH_ENC_SUPPORTED 1
#define SOC_SECURE_BOOT_SUPPORTED 1
#define SOC_BOD_SUPPORTED 1
@@ -654,10 +655,12 @@
/*-------------------------- Key Manager CAPS----------------------------*/
#define SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1 /*!< Key manager supports key deployment */
#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */
#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 0 /*!< Key manager responsible to deploy ECDSA key */ // TODO: IDF-13523
#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */
#define SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 1 /*!< Key manager responsible to deploy the XTS-AES-128 key */
#define SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 1 /*!< Key manager responsible to deploy the XTS-AES-256 key */
#define SOC_KEY_MANAGER_HMAC_KEY_DEPLOY 1 /*!< Key manager responsible to deploy HMAC key */
#define SOC_KEY_MANAGER_DS_KEY_DEPLOY 1 /*!< Key manager responsible to deploy DS key */
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1
components/soc/esp32p4/register/hw_ver3/soc/keymng_eco5_reg.h
-395
View File
@@ -1,395 +0,0 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** KEYMNG_CLK_REG register
* Key Manager clock gate control register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define KEYMNG_REG_CG_FORCE_ON (BIT(0))
#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_REG_CG_FORCE_ON_S 0
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_MEM_CG_FORCE_ON_S 1
/** KEYMNG_INT_RAW_REG register
* Key Manager interrupt raw register, valid in level.
*/
#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_RAW_S 0
/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_RAW_S 1
/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_POST_DONE_INT_RAW_S 2
/** KEYMNG_INT_ST_REG register
* Key Manager interrupt status register.
*/
#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ST_S 0
/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ST_S 1
/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ST (BIT(2))
#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ST_S 2
/** KEYMNG_INT_ENA_REG register
* Key Manager interrupt enable register.
*/
#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ENA_S 0
/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ENA_S 1
/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ENA_S 2
/** KEYMNG_INT_CLR_REG register
* Key Manager interrupt clear register.
*/
#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_CLR_S 0
/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_CLR_S 1
/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_POST_DONE_INT_CLR_S 2
/** KEYMNG_STATIC_REG register
* Key Manager static configuration register
*/
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
* bit 1 for flash_key; bit 0 for ecdsa_key
*/
#define KEYMNG_USE_EFUSE_KEY 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_S 0
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_S 5
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY (BIT(10))
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_S 10
/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_FLASH_KEY_LEN (BIT(11))
#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_S 11
/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_PSRAM_KEY_LEN (BIT(12))
#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_S 12
/** KEYMNG_LOCK_REG register
* Key Manager static configuration locker register
*/
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6))
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6
/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
* Write 1 to lock reg_flash_key_len.
*/
#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7))
#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7
/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
* Write 1 to lock reg_psram_key_len.
*/
#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8))
#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8
/** KEYMNG_CONF_REG register
* Key Manager configuration register
*/
#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
#define KEYMNG_KGEN_MODE 0x00000007U
#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
#define KEYMNG_KGEN_MODE_V 0x00000007U
#define KEYMNG_KGEN_MODE_S 0
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
* ecdsa_key_384_h. Others: reserved.
*/
#define KEYMNG_KEY_PURPOSE 0x0000000FU
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
#define KEYMNG_KEY_PURPOSE_S 3
/** KEYMNG_START_REG register
* Key Manager control register
*/
#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
/** KEYMNG_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
#define KEYMNG_START (BIT(0))
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
#define KEYMNG_START_V 0x00000001U
#define KEYMNG_START_S 0
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
#define KEYMNG_CONTINUE (BIT(1))
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
#define KEYMNG_CONTINUE_V 0x00000001U
#define KEYMNG_CONTINUE_S 1
/** KEYMNG_STATE_REG register
* Key Manager state register
*/
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define KEYMNG_STATE 0x00000003U
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
#define KEYMNG_STATE_V 0x00000003U
#define KEYMNG_STATE_S 0
/** KEYMNG_RESULT_REG register
* Key Manager operation result register
*/
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
#define KEYMNG_PROC_RESULT (BIT(0))
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
#define KEYMNG_PROC_RESULT_V 0x00000001U
#define KEYMNG_PROC_RESULT_S 0
/** KEYMNG_KEY_VLD_REG register
* Key Manager key status register
*/
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_192_VLD_S 0
/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1))
#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_256_VLD_S 1
/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_FLASH_VLD (BIT(2))
#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U
#define KEYMNG_KEY_FLASH_VLD_S 2
/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_HMAC_VLD (BIT(3))
#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U
#define KEYMNG_KEY_HMAC_VLD_S 3
/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_DS_VLD (BIT(4))
#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
#define KEYMNG_KEY_DS_VLD_V 0x00000001U
#define KEYMNG_KEY_DS_VLD_S 4
/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_PSRAM_VLD (BIT(5))
#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U
#define KEYMNG_KEY_PSRAM_VLD_S 5
/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6))
#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_384_VLD_S 6
/** KEYMNG_HUK_VLD_REG register
* Key Manager HUK status register
*/
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
#define KEYMNG_HUK_VALID (BIT(0))
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
#define KEYMNG_HUK_VALID_V 0x00000001U
#define KEYMNG_HUK_VALID_S 0
/** KEYMNG_DATE_REG register
* Version control register
*/
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
* Key Manager version control register.
*/
#define KEYMNG_DATE 0x0FFFFFFFU
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
#define KEYMNG_DATE_V 0x0FFFFFFFU
#define KEYMNG_DATE_S 0
/** KEYMNG_ASSIST_INFO_MEM register
* The memory that stores assist key info.
*/
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_PUBLIC_INFO_MEM register
* The memory that stores public key info.
*/
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_SW_INIT_KEY_MEM register
* The memory that stores software written init key.
*/
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/register/hw_ver3/soc/keymng_reg.h
+190 -83
View File
@@ -15,13 +15,13 @@ extern "C" {
* Key Manager clock gate control register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define KEYMNG_CLK_EN (BIT(0))
#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
#define KEYMNG_CLK_EN_V 0x00000001U
#define KEYMNG_CLK_EN_S 0
#define KEYMNG_REG_CG_FORCE_ON (BIT(0))
#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_REG_CG_FORCE_ON_S 0
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
@@ -138,85 +138,165 @@ extern "C" {
* Key Manager static configuration register
*/
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
* bit 1 for flash_key; bit 0 for ecdsa_key
*/
#define KEYMNG_USE_EFUSE_KEY 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_S 0
/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: Set this bit to choose efuse key instead of key manager deployed key for xts_key.*/
#define KEYMNG_USE_EFUSE_KEY_XTS (BIT(1))
#define KEYMNG_USE_EFUSE_KEY_XTS_M ((KEYMNG_USE_EFUSE_KEY_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_XTS_S))
#define KEYMNG_USE_EFUSE_KEY_XTS_V 0x1
#define KEYMNG_USE_EFUSE_KEY_XTS_S 1
/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa_key.*/
/** KEYMNG_USE_EFUSE_KEY_ECDSA : R/W; bitpos:[0]; default: 0;
* Set this bit to choose efuse key instead of key manager deployed key for ecdsa.
*/
#define KEYMNG_USE_EFUSE_KEY_ECDSA (BIT(0))
#define KEYMNG_USE_EFUSE_KEY_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S))
#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x1
#define KEYMNG_USE_EFUSE_KEY_ECDSA_M (KEYMNG_USE_EFUSE_KEY_ECDSA_V << KEYMNG_USE_EFUSE_KEY_ECDSA_S)
#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_ECDSA_S 0
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
/** KEYMNG_USE_EFUSE_KEY_FLASH : R/W; bitpos:[1]; default: 0;
* Set this bit to choose efuse key instead of key manager deployed key for flash.
*/
#define KEYMNG_USE_EFUSE_KEY_FLASH (BIT(1))
#define KEYMNG_USE_EFUSE_KEY_FLASH_M (KEYMNG_USE_EFUSE_KEY_FLASH_V << KEYMNG_USE_EFUSE_KEY_FLASH_S)
#define KEYMNG_USE_EFUSE_KEY_FLASH_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_FLASH_S 1
/** KEYMNG_USE_EFUSE_KEY_HMAC : R/W; bitpos:[0]; default: 0;
* Set this bit to choose efuse key instead of key manager deployed key for hmac.
*/
#define KEYMNG_USE_EFUSE_KEY_HMAC (BIT(2))
#define KEYMNG_USE_EFUSE_KEY_HMAC_M (KEYMNG_USE_EFUSE_KEY_HMAC_V << KEYMNG_USE_EFUSE_KEY_HMAC_S)
#define KEYMNG_USE_EFUSE_KEY_HMAC_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_HMAC_S 2
/** KEYMNG_USE_EFUSE_KEY_DS : R/W; bitpos:[1]; default: 0;
* Set this bit to choose efuse key instead of key manager deployed key for ds.
*/
#define KEYMNG_USE_EFUSE_KEY_DS (BIT(3))
#define KEYMNG_USE_EFUSE_KEY_DS_M (KEYMNG_USE_EFUSE_KEY_DS_V << KEYMNG_USE_EFUSE_KEY_DS_S)
#define KEYMNG_USE_EFUSE_KEY_DS_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_DS_S 3
/** KEYMNG_USE_EFUSE_KEY_PSRAM : R/W; bitpos:[1]; default: 0;
* Set this bit to choose efuse key instead of key manager deployed key for psram.
*/
#define KEYMNG_USE_EFUSE_KEY_PSRAM (BIT(4))
#define KEYMNG_USE_EFUSE_KEY_PSRAM_M (KEYMNG_USE_EFUSE_KEY_PSRAM_V << KEYMNG_USE_EFUSE_KEY_PSRAM_S)
#define KEYMNG_USE_EFUSE_KEY_PSRAM_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_PSRAM_S 4
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_S 4
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
#define KEYMNG_RND_SWITCH_CYCLE_S 5
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY (BIT(9))
#define KEYMNG_USE_SW_INIT_KEY (BIT(10))
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_S 9
/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
* xts-aes-128.
#define KEYMNG_USE_SW_INIT_KEY_S 10
/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_XTS_AES_KEY_LEN (BIT(10))
#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U
#define KEYMNG_XTS_AES_KEY_LEN_S 10
#define KEYMNG_FLASH_KEY_LEN (BIT(11))
#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_S 11
/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_PSRAM_KEY_LEN (BIT(12))
#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_S 12
/** KEYMNG_LOCK_REG register
* Key Manager static configuration locker register
*/
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ; bitpos:[1] ; default: 1'd0 ; */
/* description: Set thus bit to choose efuse key instead of key manager deployed key for xts_key */
#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS (BIT(1))
#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_M ((KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S))
#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V 0x1
#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S 1
/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W ; bitpos:[0] ; default: 1'd0 ; */
/* description: Write 1 to lock ecdsa-key */
/** KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W1 ;bitpos:[0]; default: 0;
* Write 1 to lock reg_use_efuse_key for esdsa
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA (BIT(0))
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S))
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x1
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M (KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V << KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S 0
/** KEYMNG_USE_EFUSE_KEY_LOCK_FLASH : R/W1 ;bitpos:[1]; default: 0;
* Write 1 to lock reg_use_efuse_key for FLASH
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH (BIT(1))
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_M (KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V << KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S 1
/** KEYMNG_USE_EFUSE_KEY_LOCK_HMAC : R/W1 ;bitpos:[0]; default: 0;
* Write 1 to lock reg_use_efuse_key for hmac
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC (BIT(2))
#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_M (KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V << KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S 2
/** KEYMNG_USE_EFUSE_KEY_LOCK_DS : R/W1 ;bitpos:[1]; default: 0;
* Write 1 to lock reg_use_efuse_key for ds
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK_DS (BIT(3))
#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_M (KEYMNG_USE_EFUSE_KEY_LOCK_DS_V << KEYMNG_USE_EFUSE_KEY_LOCK_DS_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_S 3
/** KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM : R/W1 ;bitpos:[1]; default: 0;
* Write 1 to lock reg_use_efuse_key for PSRAM
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM (BIT(4))
#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_M (KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V << KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V 0x00000001U
#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S 4
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5))
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6))
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5
/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_xts_aes_key_len.
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6
/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
* Write 1 to lock reg_flash_key_len.
*/
#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6))
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6
#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7))
#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7
/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
* Write 1 to lock reg_psram_key_len.
*/
#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8))
#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8
/** KEYMNG_CONF_REG register
* Key Manager configuration register
@@ -231,29 +311,16 @@ extern "C" {
#define KEYMNG_KGEN_MODE_V 0x00000007U
#define KEYMNG_KGEN_MODE_S 0
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
* xts_256_2_key. 4. xts_128_key. others: reserved.
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
* ecdsa_key_384_h. Others: reserved.
*/
#define KEYMNG_KEY_PURPOSE 0x0000000FU
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
#define KEYMNG_KEY_PURPOSE_S 3
#define KEYMNG_KEY_PURPOSE_ECDSA (BIT(0))
#define KEYMNG_KEY_PURPOSE_ECDSA_M (KEYMNG_KEY_PURPOSE_ECDSA_V << KEYMNG_KEY_PURPOSE_ECDSA_S)
#define KEYMNG_KEY_PURPOSE_ECDSA_V 0x00000001U
#define KEYMNG_KEY_PURPOSE_ECDSA_S 0
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1 (BIT(1))
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_M (KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S)
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V 0x00000001U
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S 1
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2 (BIT(2))
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_M (KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S)
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V 0x00000001U
#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S 2
/** KEYMNG_START_REG register
* Key Manager control register
*/
@@ -302,22 +369,62 @@ extern "C" {
* Key Manager key status register
*/
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_VLD_S 0
/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_XTS_VLD (BIT(1))
#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
#define KEYMNG_KEY_XTS_VLD_V 0x00000001U
#define KEYMNG_KEY_XTS_VLD_S 1
#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_192_VLD_S 0
/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1))
#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_256_VLD_S 1
/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_FLASH_VLD (BIT(2))
#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U
#define KEYMNG_KEY_FLASH_VLD_S 2
/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_HMAC_VLD (BIT(3))
#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U
#define KEYMNG_KEY_HMAC_VLD_S 3
/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_DS_VLD (BIT(4))
#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
#define KEYMNG_KEY_DS_VLD_V 0x00000001U
#define KEYMNG_KEY_DS_VLD_S 4
/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_PSRAM_VLD (BIT(5))
#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U
#define KEYMNG_KEY_PSRAM_VLD_S 5
/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6))
#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_384_VLD_S 6
/** KEYMNG_HUK_VLD_REG register
* Key Manager HUK status register
@@ -335,7 +442,7 @@ extern "C" {
* Version control register
*/
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
* Key Manager version control register.
*/
#define KEYMNG_DATE 0x0FFFFFFFU