forked from espressif/esp-idf
esp32c6: add soc/ xxx_periph, xxx_channel, xxx_pins, etc. files
This commit is contained in:
songruojing
committed by
Song Ruo Jing
Song Ruo Jing
parent
9d515185d0
commit
688fb18faa
@ -76,12 +76,12 @@ typedef enum {
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typedef enum {
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NO_MEAN = 0,
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POWERON_RESET = 1, /**<1, Vbat power on reset*/
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RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
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DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
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TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
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TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
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RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
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INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
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RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core (hp system)*/
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DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core (hp system)*/
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SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core (hp system)*/
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TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
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TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
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RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core (hp system)*/
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TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
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RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
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RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
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@ -89,17 +89,17 @@ typedef enum {
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RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
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TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
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SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
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GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
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EFUSE_RESET = 20, /**<20, efuse reset digital core*/
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USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
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USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
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POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
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EFUSE_RESET = 20, /**<20, efuse reset digital core (hp system)*/
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USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core (hp system)*/
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USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core (hp system)*/
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JTAG_RESET = 24, /**<24, jtag reset CPU*/
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} RESET_REASON;
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// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
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_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
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_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
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_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
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_Static_assert((soc_reset_reason_t)SDIO_RESET == RESET_REASON_CORE_SDIO, "SDIO_RESET != RESET_REASON_CORE_SDIO");
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_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
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_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
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_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
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@ -110,11 +110,10 @@ _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BR
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_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
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_Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
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_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
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_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
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_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
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_Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
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_Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
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_Static_assert((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
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_Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
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typedef enum {
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NO_SLEEP = 0,
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@ -0,0 +1,30 @@
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set(srcs
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"adc_periph.c"
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"dedic_gpio_periph.c"
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"gdma_periph.c"
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"gpio_periph.c"
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"sdm_periph.c"
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"interrupts.c"
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"spi_periph.c"
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"ledc_periph.c"
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"rmt_periph.c"
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"i2s_periph.c"
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"i2c_periph.c"
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"uart_periph.c"
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"temperature_sensor_periph.c"
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"timer_periph.c")
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# ESP32C6-TODO
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list(REMOVE_ITEM srcs
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"adc_periph.c" # TODO: IDF-5310
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"dedic_gpio_periph.c" # TODO: IDF-5331
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"ledc_periph.c" # TODO: IDF-5328
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"i2s_periph.c" # TODO: IDF-5314
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"i2c_periph.c" # TODO: IDF-5326
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"temperature_sensor_periph.c" # TODO: IDF-5322
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)
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add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
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target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
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target_include_directories(${COMPONENT_LIB} PUBLIC . include)
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19
components/soc/esp32c6/adc_periph.c
Normal file
19
components/soc/esp32c6/adc_periph.c
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@ -0,0 +1,19 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/adc_periph.h"
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/* Store IO number corresponding to the ADC channel number. */
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const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
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/* ADC1 */
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{
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ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
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},
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/* ADC2 */
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{
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ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1
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}
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};
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37
components/soc/esp32c6/dedic_gpio_periph.c
Normal file
37
components/soc/esp32c6/dedic_gpio_periph.c
Normal file
@ -0,0 +1,37 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/gpio_sig_map.h"
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#include "soc/dedic_gpio_periph.h"
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const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
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.module = -1,
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.irq = -1,
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.cores = {
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[0] = {
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.in_sig_per_channel = {
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[0] = CPU_GPIO_IN0_IDX,
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[1] = CPU_GPIO_IN1_IDX,
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[2] = CPU_GPIO_IN2_IDX,
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[3] = CPU_GPIO_IN3_IDX,
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[4] = CPU_GPIO_IN4_IDX,
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[5] = CPU_GPIO_IN5_IDX,
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[6] = CPU_GPIO_IN6_IDX,
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[7] = CPU_GPIO_IN7_IDX,
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},
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.out_sig_per_channel = {
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[0] = CPU_GPIO_OUT0_IDX,
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[1] = CPU_GPIO_OUT1_IDX,
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[2] = CPU_GPIO_OUT2_IDX,
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[3] = CPU_GPIO_OUT3_IDX,
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[4] = CPU_GPIO_OUT4_IDX,
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[5] = CPU_GPIO_OUT5_IDX,
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[6] = CPU_GPIO_OUT6_IDX,
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[7] = CPU_GPIO_OUT7_IDX,
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}
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},
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},
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};
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29
components/soc/esp32c6/gdma_periph.c
Normal file
29
components/soc/esp32c6/gdma_periph.c
Normal file
@ -0,0 +1,29 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/gdma_periph.h"
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const gdma_signal_conn_t gdma_periph_signals = {
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.groups = {
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[0] = {
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.module = PERIPH_GDMA_MODULE,
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.pairs = {
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[0] = {
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.rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
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},
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[1] = {
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.rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
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},
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[2] = {
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.rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
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}
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}
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}
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}
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};
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79
components/soc/esp32c6/gpio_periph.c
Normal file
79
components/soc/esp32c6/gpio_periph.c
Normal file
@ -0,0 +1,79 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/gpio_periph.h"
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const uint32_t GPIO_PIN_MUX_REG[] = {
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IO_MUX_GPIO0_REG,
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IO_MUX_GPIO1_REG,
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IO_MUX_GPIO2_REG,
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IO_MUX_GPIO3_REG,
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IO_MUX_GPIO4_REG,
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IO_MUX_GPIO5_REG,
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IO_MUX_GPIO6_REG,
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IO_MUX_GPIO7_REG,
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IO_MUX_GPIO8_REG,
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IO_MUX_GPIO9_REG,
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IO_MUX_GPIO10_REG,
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IO_MUX_GPIO11_REG,
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IO_MUX_GPIO12_REG,
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IO_MUX_GPIO13_REG,
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IO_MUX_GPIO14_REG,
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IO_MUX_GPIO15_REG,
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IO_MUX_GPIO16_REG,
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IO_MUX_GPIO17_REG,
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IO_MUX_GPIO18_REG,
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IO_MUX_GPIO19_REG,
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IO_MUX_GPIO20_REG,
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IO_MUX_GPIO21_REG,
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IO_MUX_GPIO22_REG,
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IO_MUX_GPIO23_REG,
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IO_MUX_GPIO24_REG,
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IO_MUX_GPIO25_REG,
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IO_MUX_GPIO26_REG,
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IO_MUX_GPIO27_REG,
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IO_MUX_GPIO28_REG,
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IO_MUX_GPIO29_REG,
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IO_MUX_GPIO30_REG,
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};
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_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
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const uint32_t GPIO_HOLD_MASK[] = {
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BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
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BIT(1), //GPIO1
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BIT(2), //GPIO2
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BIT(3), //GPIO3
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BIT(4), //GPIO4
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BIT(5), //GPIO5
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BIT(6), //GPIO6
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BIT(7), //GPIO7
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BIT(8), //GPIO8
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BIT(9), //GPIO9
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BIT(10), //GPIO10
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BIT(11), //GPIO11
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BIT(12), //GPIO12
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BIT(13), //GPIO13
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BIT(14), //GPIO14
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BIT(15), //GPIO15
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BIT(16), //GPIO16
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BIT(17), //GPIO17
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BIT(18), //GPIO18
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BIT(19), //GPIO19
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BIT(20), //GPIO20
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BIT(21), //GPIO21
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BIT(22), //GPIO22
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BIT(23), //GPIO23
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BIT(24), //GPIO24
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BIT(25), //GPIO25
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BIT(26), //GPIO26
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BIT(27), //GPIO27
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BIT(28), //GPIO28
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BIT(29), //GPIO29
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BIT(30), //GPIO30
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};
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_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
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22
components/soc/esp32c6/i2c_periph.c
Normal file
22
components/soc/esp32c6/i2c_periph.c
Normal file
@ -0,0 +1,22 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/i2c_periph.h"
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#include "soc/gpio_sig_map.h"
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/*
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Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
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{
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.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
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.sda_in_sig = I2CEXT0_SDA_IN_IDX,
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.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
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.scl_in_sig = I2CEXT0_SCL_IN_IDX,
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.irq = ETS_I2C_EXT0_INTR_SOURCE,
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.module = PERIPH_I2C0_MODULE,
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},
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};
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33
components/soc/esp32c6/i2s_periph.c
Normal file
33
components/soc/esp32c6/i2s_periph.c
Normal file
@ -0,0 +1,33 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/i2s_periph.h"
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#include "soc/gpio_sig_map.h"
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/*
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Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
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{
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.mck_out_sig = I2S_MCLK_OUT_IDX,
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.m_tx_bck_sig = I2SO_BCK_OUT_IDX,
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.m_rx_bck_sig = I2SI_BCK_OUT_IDX,
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.m_tx_ws_sig = I2SO_WS_OUT_IDX,
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.m_rx_ws_sig = I2SI_WS_OUT_IDX,
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.s_tx_bck_sig = I2SO_BCK_IN_IDX,
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.s_rx_bck_sig = I2SI_BCK_IN_IDX,
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.s_tx_ws_sig = I2SO_WS_IN_IDX,
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.s_rx_ws_sig = I2SI_WS_IN_IDX,
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.data_out_sig = I2SO_SD_OUT_IDX,
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.data_in_sig = I2SI_SD_IN_IDX,
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.irq = -1,
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.module = PERIPH_I2S1_MODULE,
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}
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};
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744
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
Normal file
744
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
Normal file
@ -0,0 +1,744 @@
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#####################################################
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# This file is auto-generated from SoC caps
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# using gen_soc_caps_kconfig.py, do not edit manually
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#####################################################
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config SOC_GDMA_SUPPORTED
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bool
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default y
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config SOC_BT_SUPPORTED
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bool
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default y
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config SOC_ASYNC_MEMCPY_SUPPORTED
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bool
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default y
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config SOC_USB_SERIAL_JTAG_SUPPORTED
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bool
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default y
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config SOC_WIFI_SUPPORTED
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bool
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default y
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config SOC_SUPPORTS_SECURE_DL_MODE
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bool
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default y
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config SOC_RISCV_COPROC_SUPPORTED
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bool
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default y
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config SOC_EFUSE_KEY_PURPOSE_FIELD
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bool
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default y
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config SOC_EFUSE_HAS_EFUSE_RST_BUG
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bool
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default y
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config SOC_RTC_FAST_MEM_SUPPORTED
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bool
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default y
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config SOC_RTC_MEM_SUPPORTED
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bool
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default y
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config SOC_SYSTIMER_SUPPORTED
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bool
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default y
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config SOC_SUPPORT_COEXISTENCE
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bool
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default y
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config SOC_FLASH_ENC_SUPPORTED
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bool
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default y
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config SOC_SECURE_BOOT_SUPPORTED
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bool
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default y
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config SOC_XTAL_SUPPORT_40M
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bool
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default y
|
||||
|
||||
config SOC_AES_SUPPORT_DMA
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_AES_GDMA
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_AES_SUPPORT_AES_128
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_AES_SUPPORT_AES_256
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ADC_DIG_CTRL_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ADC_ARBITER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ADC_FILTER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ADC_MONITOR_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ADC_PERIPH_NUM
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_ADC_MAX_CHANNEL_NUM
|
||||
int
|
||||
default 5
|
||||
|
||||
config SOC_ADC_ATTEN_NUM
|
||||
int
|
||||
default 4
|
||||
|
||||
config SOC_ADC_DIGI_CONTROLLER_NUM
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_ADC_PATT_LEN_MAX
|
||||
int
|
||||
default 8
|
||||
|
||||
config SOC_ADC_DIGI_MAX_BITWIDTH
|
||||
int
|
||||
default 12
|
||||
|
||||
config SOC_ADC_DIGI_FILTER_NUM
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_ADC_DIGI_MONITOR_NUM
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
|
||||
int
|
||||
default 83333
|
||||
|
||||
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
|
||||
int
|
||||
default 611
|
||||
|
||||
config SOC_ADC_RTC_MIN_BITWIDTH
|
||||
int
|
||||
default 12
|
||||
|
||||
config SOC_ADC_RTC_MAX_BITWIDTH
|
||||
int
|
||||
default 12
|
||||
|
||||
config SOC_ADC_CALIBRATION_V1_SUPPORTED
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_APB_BACKUP_DMA
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_BROWNOUT_RESET_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SHARED_IDCACHE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CPU_CORES_NUM
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_CPU_INTR_NUM
|
||||
int
|
||||
default 32
|
||||
|
||||
config SOC_CPU_HAS_FLEXIBLE_INTC
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RV32A_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_INT_PLIC_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CPU_BREAKPOINTS_NUM
|
||||
int
|
||||
default 4
|
||||
|
||||
config SOC_CPU_WATCHPOINTS_NUM
|
||||
int
|
||||
default 4
|
||||
|
||||
config SOC_CPU_WATCHPOINT_SIZE
|
||||
hex
|
||||
default 0x80000000
|
||||
|
||||
config SOC_MMU_PAGE_SIZE_CONFIGURABLE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_DS_SIGNATURE_MAX_BIT_LEN
|
||||
int
|
||||
default 3072
|
||||
|
||||
config SOC_DS_KEY_PARAM_MD_IV_LENGTH
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_DS_KEY_CHECK_MAX_WAIT_US
|
||||
int
|
||||
default 1100
|
||||
|
||||
config SOC_GDMA_GROUPS
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_GDMA_PAIRS_PER_GROUP
|
||||
int
|
||||
default 3
|
||||
|
||||
config SOC_GPIO_PORT
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_GPIO_PIN_COUNT
|
||||
int
|
||||
default 31
|
||||
|
||||
config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPIO_SUPPORT_FORCE_HOLD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
|
||||
int
|
||||
default 0
|
||||
|
||||
config SOC_GPIO_SUPPORT_SLP_SWITCH
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
|
||||
int
|
||||
default 8
|
||||
|
||||
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
|
||||
int
|
||||
default 8
|
||||
|
||||
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2C_NUM
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_I2C_FIFO_LEN
|
||||
int
|
||||
default 32
|
||||
|
||||
config SOC_I2C_SUPPORT_SLAVE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2C_SUPPORT_HW_CLR_BUS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2C_SUPPORT_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2C_SUPPORT_RTC
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_NUM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_HW_VERSION_2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PCM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PDM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PDM_TX
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PDM_CODEC
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_TDM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_SUPPORT_APB_CLOCK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_SUPPORT_XTAL_CLOCK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_CHANNEL_NUM
|
||||
int
|
||||
default 6
|
||||
|
||||
config SOC_LEDC_TIMER_BIT_WIDE_NUM
|
||||
int
|
||||
default 14
|
||||
|
||||
config SOC_LEDC_SUPPORT_FADE_STOP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_MPU_MIN_REGION_SIZE
|
||||
hex
|
||||
default 0x20000000
|
||||
|
||||
config SOC_MPU_REGIONS_MAX_NUM
|
||||
int
|
||||
default 8
|
||||
|
||||
config SOC_MPU_REGION_RO_SUPPORTED
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_MPU_REGION_WO_SUPPORTED
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_RMT_GROUPS
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_RMT_TX_CANDIDATES_PER_GROUP
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_RMT_RX_CANDIDATES_PER_GROUP
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_RMT_CHANNELS_PER_GROUP
|
||||
int
|
||||
default 4
|
||||
|
||||
config SOC_RMT_MEM_WORDS_PER_CHANNEL
|
||||
int
|
||||
default 48
|
||||
|
||||
config SOC_RMT_SUPPORT_RX_PINGPONG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RMT_SUPPORT_RX_DEMODULATION
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RMT_SUPPORT_TX_ASYNC_STOP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RMT_SUPPORT_TX_SYNCHRO
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RMT_SUPPORT_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RMT_SUPPORT_APB
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RMT_SUPPORT_RC_FAST
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
|
||||
int
|
||||
default 128
|
||||
|
||||
config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
|
||||
int
|
||||
default 108
|
||||
|
||||
config SOC_RTCIO_PIN_COUNT
|
||||
int
|
||||
default 0
|
||||
|
||||
config SOC_RSA_MAX_BIT_LEN
|
||||
int
|
||||
default 3072
|
||||
|
||||
config SOC_SHA_DMA_MAX_BUFFER_SIZE
|
||||
int
|
||||
default 3968
|
||||
|
||||
config SOC_SHA_SUPPORT_DMA
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SHA_SUPPORT_RESUME
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SHA_GDMA
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SHA_SUPPORT_SHA1
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SHA_SUPPORT_SHA224
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SHA_SUPPORT_SHA256
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SDM_GROUPS
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_SDM_CHANNELS_PER_GROUP
|
||||
int
|
||||
default 4
|
||||
|
||||
config SOC_SPI_PERIPH_NUM
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_SPI_MAXIMUM_BUFFER_SIZE
|
||||
int
|
||||
default 64
|
||||
|
||||
config SOC_SPI_SUPPORT_DDRCLK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_SUPPORT_CD_SIG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MEMSPI_IS_INDEPENDENT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_MAX_PRE_DIVIDER
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_MEM_SUPPORT_IDLE_INTR
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_MEM_SUPPORT_CHECK_SUS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SYSTIMER_COUNTER_NUM
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_SYSTIMER_ALARM_NUM
|
||||
int
|
||||
default 3
|
||||
|
||||
config SOC_SYSTIMER_BIT_WIDTH_LO
|
||||
int
|
||||
default 32
|
||||
|
||||
config SOC_SYSTIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 20
|
||||
|
||||
config SOC_SYSTIMER_FIXED_DIVIDER
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SYSTIMER_INT_LEVEL
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_GROUPS
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
|
||||
int
|
||||
default 54
|
||||
|
||||
config SOC_TIMER_GROUP_SUPPORT_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_GROUP_SUPPORT_APB
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_GROUP_TOTAL_TIMERS
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_TWAI_BRP_MIN
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_TWAI_BRP_MAX
|
||||
int
|
||||
default 16384
|
||||
|
||||
config SOC_TWAI_SUPPORTS_RX_STATUS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SECURE_BOOT_V2_RSA
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SECURE_BOOT_V2_ECC
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
|
||||
int
|
||||
default 3
|
||||
|
||||
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
|
||||
int
|
||||
default 32
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES_128
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_MEMPROT_MEM_ALIGN_SIZE
|
||||
int
|
||||
default 512
|
||||
|
||||
config SOC_UART_NUM
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_UART_FIFO_LEN
|
||||
int
|
||||
default 128
|
||||
|
||||
config SOC_UART_BITRATE_MAX
|
||||
int
|
||||
default 5000000
|
||||
|
||||
config SOC_UART_SUPPORT_APB_CLK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_SUPPORT_RTC_CLK
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_UART_SUPPORT_XTAL_CLK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_REQUIRE_CORE_RESET
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_COEX_HW_PTI
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PHY_DIG_REGS_MEM_SIZE
|
||||
int
|
||||
default 21
|
||||
|
||||
config SOC_MAC_BB_PD_MEM_SIZE
|
||||
int
|
||||
default 192
|
||||
|
||||
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
|
||||
int
|
||||
default 12
|
||||
|
||||
config SOC_PM_SUPPORT_WIFI_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_BT_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_CPU_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_WIFI_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_BT_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_WIFI_HW_TSF
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_WIFI_FTM_SUPPORT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_WIFI_GCMP_SUPPORT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_WIFI_WAPI_SUPPORT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_WIFI_CSI_SUPPORT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_WIFI_MESH_SUPPORT
|
||||
bool
|
||||
default y
|
||||
25
components/soc/esp32c6/include/soc/adc_channel.h
Normal file
25
components/soc/esp32c6/include/soc/adc_channel.h
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define ADC1_GPIO0_CHANNEL ADC1_CHANNEL_0
|
||||
#define ADC1_CHANNEL_0_GPIO_NUM 0
|
||||
|
||||
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_1
|
||||
#define ADC1_CHANNEL_1_GPIO_NUM 1
|
||||
|
||||
#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_2
|
||||
#define ADC1_CHANNEL_2_GPIO_NUM 2
|
||||
|
||||
#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_3
|
||||
#define ADC1_CHANNEL_3_GPIO_NUM 3
|
||||
|
||||
#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_4
|
||||
#define ADC1_CHANNEL_4_GPIO_NUM 4
|
||||
|
||||
#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0
|
||||
#define ADC2_CHANNEL_0_GPIO_NUM 5
|
||||
93
components/soc/esp32c6/include/soc/boot_mode.h
Normal file
93
components/soc/esp32c6/include/soc/boot_mode.h
Normal file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_BOOT_MODE_H_
|
||||
#define _SOC_BOOT_MODE_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/*SPI Boot*/
|
||||
#define IS_1XXX(v) (((v)&0x08)==0x08)
|
||||
|
||||
/*Download Boot, SPI(or SDIO_V2)/UART0*/
|
||||
#define IS_00XX(v) (((v)&0x0c)==0x00)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
|
||||
#define IS_0000(v) (((v)&0x0f)==0x00)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
|
||||
#define IS_0001(v) (((v)&0x0f)==0x01)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
|
||||
#define IS_0010(v) (((v)&0x0f)==0x02)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
|
||||
#define IS_0011(v) (((v)&0x0f)==0x03)
|
||||
|
||||
/*legacy SPI Boot*/
|
||||
#define IS_0100(v) (((v)&0x0f)==0x04)
|
||||
|
||||
/*ATE/ANALOG Mode*/
|
||||
#define IS_0101(v) (((v)&0x0f)==0x05)
|
||||
|
||||
/*SPI(or SDIO_V1) download Mode*/
|
||||
#define IS_0110(v) (((v)&0x0f)==0x06)
|
||||
|
||||
/*Diagnostic Mode+UART0 download Mode*/
|
||||
#define IS_0111(v) (((v)&0x0f)==0x07)
|
||||
|
||||
|
||||
|
||||
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
|
||||
|
||||
/*do not include download mode*/
|
||||
#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET())
|
||||
|
||||
/*all spi boot including spi/legacy*/
|
||||
#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
|
||||
|
||||
/*all faster spi boot including spi*/
|
||||
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
|
||||
|
||||
#if SUPPORT_SDIO_DOWNLOAD
|
||||
|
||||
/*all sdio V2 of failing edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of failing edge input, raising edge output*/
|
||||
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of raising edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of raising edge input, raising edge output*/
|
||||
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V1 of raising edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
|
||||
/*do not include joint download mode*/
|
||||
#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
#else
|
||||
|
||||
/*do not include joint download mode*/
|
||||
#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
|
||||
#endif
|
||||
|
||||
/*joint download boot*/
|
||||
#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET())
|
||||
|
||||
/*ATE mode*/
|
||||
#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
|
||||
|
||||
/*used by ETS_IS_SDIO_UART_BOOT*/
|
||||
#define SEL_NO_BOOT 0
|
||||
#define SEL_SDIO_BOOT BIT0
|
||||
#define SEL_UART_BOOT BIT1
|
||||
#define SEL_SPI_SLAVE_BOOT BIT2
|
||||
|
||||
#endif /* _SOC_BOOT_MODE_H_ */
|
||||
@ -5,7 +5,7 @@
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
253
components/soc/esp32c6/include/soc/clk_tree_defs.h
Normal file
253
components/soc/esp32c6/include/soc/clk_tree_defs.h
Normal file
@ -0,0 +1,253 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: IDF-5346 Copied from C3, need to update
|
||||
/*
|
||||
************************* ESP32C6 Root Clock Source ****************************
|
||||
* 1) Internal 17.5MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description)
|
||||
*
|
||||
* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
|
||||
* The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock
|
||||
* frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description).
|
||||
*
|
||||
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
|
||||
*
|
||||
* 2) External 40MHz Crystal Clock: XTAL
|
||||
*
|
||||
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
|
||||
*
|
||||
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
|
||||
* can be computed in runtime through calibration.
|
||||
*
|
||||
* 4) External 32kHz Crystal Clock (optional): XTAL32K
|
||||
*
|
||||
* The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
|
||||
* pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the
|
||||
* XTAL_32K_P pin.
|
||||
*
|
||||
* XTAL32K_CLK can also be calibrated to get its exact frequency.
|
||||
*/
|
||||
|
||||
/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
|
||||
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
|
||||
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
|
||||
#define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */
|
||||
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
|
||||
|
||||
// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
|
||||
// {loc}: EXT, INT
|
||||
// {type}: XTAL, RC
|
||||
// [attr] - optional: [frequency], FAST, SLOW
|
||||
/**
|
||||
* @brief Root clock
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
|
||||
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
|
||||
SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
|
||||
SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */
|
||||
} soc_root_clk_t;
|
||||
|
||||
/**
|
||||
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
|
||||
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */
|
||||
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
|
||||
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
|
||||
} soc_cpu_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
|
||||
} soc_rtc_slow_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
|
||||
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: APB, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
/**
|
||||
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
|
||||
*
|
||||
* @note enum starts from 1, to save 0 for special purpose
|
||||
*/
|
||||
typedef enum {
|
||||
// For CPU domain
|
||||
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
|
||||
// For RTC domain
|
||||
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
|
||||
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
|
||||
// For digital domain: peripherals, WIFI, BLE
|
||||
SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
|
||||
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
|
||||
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
|
||||
SOC_MOD_CLK_PLL_D2, /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */
|
||||
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
|
||||
} soc_module_clk_t;
|
||||
|
||||
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of GPTimer
|
||||
*
|
||||
* The following code can be used to iterate all possible clocks:
|
||||
* @code{c}
|
||||
* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
|
||||
* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
|
||||
* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
|
||||
* // Test GPTimer with the clock `clk`
|
||||
* }
|
||||
* @endcode
|
||||
*/
|
||||
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of GPTimer clock source
|
||||
*/
|
||||
typedef enum {
|
||||
GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
|
||||
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
|
||||
} soc_periph_gptimer_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
|
||||
*/
|
||||
typedef enum {
|
||||
TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group clock source is APB */
|
||||
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
|
||||
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group clock source default choice is APB */
|
||||
} soc_periph_tg_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of RMT
|
||||
*/
|
||||
#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of RMT clock source
|
||||
*/
|
||||
typedef enum {
|
||||
RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
|
||||
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
|
||||
} soc_periph_rmt_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Type of RMT clock source, reserved for the legacy RMT driver
|
||||
*/
|
||||
typedef enum {
|
||||
RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB */
|
||||
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
|
||||
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
|
||||
} soc_periph_rmt_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of Temperature Sensor
|
||||
*/
|
||||
#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief Type of Temp Sensor clock source
|
||||
*/
|
||||
typedef enum {
|
||||
TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
|
||||
} soc_periph_temperature_sensor_clk_src_t;
|
||||
|
||||
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Type of UART clock source, reserved for the legacy UART driver
|
||||
*/
|
||||
typedef enum {
|
||||
UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */
|
||||
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
|
||||
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
|
||||
UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
|
||||
} soc_periph_uart_clk_src_legacy_t;
|
||||
|
||||
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of I2S
|
||||
*/
|
||||
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
|
||||
|
||||
/**
|
||||
* @brief I2S clock source enum
|
||||
*/
|
||||
typedef enum {
|
||||
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
|
||||
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
|
||||
} soc_periph_i2s_clk_src_t;
|
||||
|
||||
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of I2C
|
||||
*/
|
||||
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief Type of I2C clock source.
|
||||
*/
|
||||
typedef enum {
|
||||
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
|
||||
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,
|
||||
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
|
||||
} soc_periph_i2c_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of SDM
|
||||
*/
|
||||
#define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
|
||||
|
||||
/**
|
||||
* @brief Sigma Delta Modulator clock source
|
||||
*/
|
||||
typedef enum {
|
||||
SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
|
||||
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
|
||||
} soc_periph_sdm_clk_src_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
19
components/soc/esp32c6/include/soc/clkout_channel.h
Normal file
19
components/soc/esp32c6/include/soc/clkout_channel.h
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_CLKOUT_CHANNEL_H
|
||||
#define _SOC_CLKOUT_CHANNEL_H
|
||||
|
||||
// TODO: IDF-5870
|
||||
//CLKOUT channels
|
||||
#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1
|
||||
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20
|
||||
#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2
|
||||
#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19
|
||||
#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3
|
||||
#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18
|
||||
|
||||
#endif
|
||||
112
components/soc/esp32c6/include/soc/dport_access.h
Normal file
112
components/soc/esp32c6/include/soc/dport_access.h
Normal file
@ -0,0 +1,112 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _DPORT_ACCESS_H_
|
||||
#define _DPORT_ACCESS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc.h"
|
||||
#include "uart_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
|
||||
|
||||
#define DPORT_INTERRUPT_DISABLE()
|
||||
#define DPORT_INTERRUPT_RESTORE()
|
||||
|
||||
/**
|
||||
* @brief Read a sequence of DPORT registers to the buffer.
|
||||
*
|
||||
* @param[out] buff_out Contains the read data.
|
||||
* @param[in] address Initial address for reading registers.
|
||||
* @param[in] num_words The number of words.
|
||||
*/
|
||||
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
|
||||
|
||||
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
|
||||
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
|
||||
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
|
||||
|
||||
// Write value to DPORT register (does not require protecting)
|
||||
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
|
||||
|
||||
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
|
||||
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
|
||||
|
||||
//get bit or get bits from register
|
||||
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
|
||||
|
||||
//set bit or set bits to register
|
||||
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
|
||||
|
||||
//set field to register, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
|
||||
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
|
||||
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
|
||||
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
|
||||
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
|
||||
|
||||
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
|
||||
|
||||
//write value to register
|
||||
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
|
||||
|
||||
//get field of register
|
||||
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
|
||||
//}}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DPORT_ACCESS_H_ */
|
||||
107
components/soc/esp32c6/include/soc/ext_mem_defs.h
Normal file
107
components/soc/esp32c6/include/soc/ext_mem_defs.h
Normal file
@ -0,0 +1,107 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _CACHE_MEMORY_H_
|
||||
#define _CACHE_MEMORY_H_
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*IRAM0 is connected with Cache IBUS0*/
|
||||
#define IRAM0_ADDRESS_LOW 0x40000000
|
||||
#define IRAM0_ADDRESS_HIGH 0x44000000
|
||||
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define IRAM0_CACHE_ADDRESS_HIGH 0x42800000
|
||||
|
||||
/*DRAM0 is connected with Cache DBUS0*/
|
||||
#define DRAM0_ADDRESS_LOW 0x3C000000
|
||||
#define DRAM0_ADDRESS_HIGH 0x40000000
|
||||
#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
|
||||
#define DRAM0_CACHE_ADDRESS_HIGH 0x3C800000
|
||||
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
|
||||
#define ESP_CACHE_TEMP_ADDR 0x3C000000
|
||||
|
||||
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
|
||||
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
|
||||
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
|
||||
|
||||
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
|
||||
|
||||
#define CACHE_IBUS 0
|
||||
#define CACHE_IBUS_MMU_START 0
|
||||
#define CACHE_IBUS_MMU_END 0x200
|
||||
|
||||
#define CACHE_DBUS 1
|
||||
#define CACHE_DBUS_MMU_START 0
|
||||
#define CACHE_DBUS_MMU_END 0x200
|
||||
|
||||
//TODO, remove these cache function dependencies
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x200
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x200
|
||||
#define DCACHE_MMU_SIZE 0x200
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#define MMU_INVALID BIT(8)
|
||||
#define MMU_VALID 0
|
||||
#define MMU_TYPE 0
|
||||
#define MMU_ACCESS_FLASH 0
|
||||
|
||||
#define CACHE_MAX_SYNC_NUM 0x400000
|
||||
#define CACHE_MAX_LOCK_NUM 0x8000
|
||||
|
||||
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
||||
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(8), so value bits are 0xff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0xff
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 256 * 64KB, means MMU can support 16MB paddr at most
|
||||
*/
|
||||
#define MMU_MAX_PADDR_PAGE_NUM 256
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK 0x7FFFFF
|
||||
//MMU entry num
|
||||
#define MMU_ENTRY_NUM 128
|
||||
|
||||
#define CACHE_ICACHE_LOW_SHIFT 0
|
||||
#define CACHE_ICACHE_HIGH_SHIFT 2
|
||||
#define CACHE_DCACHE_LOW_SHIFT 4
|
||||
#define CACHE_DCACHE_HIGH_SHIFT 6
|
||||
|
||||
#define CACHE_MEMORY_IBANK0_ADDR 0x4037c000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_CACHE_MEMORY_H_ */
|
||||
16
components/soc/esp32c6/include/soc/gdma_channel.h
Normal file
16
components/soc/esp32c6/include/soc/gdma_channel.h
Normal file
@ -0,0 +1,16 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
|
||||
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
|
||||
#define SOC_GDMA_TRIG_PERIPH_UART0 (2)
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
|
||||
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
|
||||
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
|
||||
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
|
||||
19
components/soc/esp32c6/include/soc/gpio_pins.h
Normal file
19
components/soc/esp32c6/include/soc/gpio_pins.h
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GPIO_MATRIX_CONST_ONE_INPUT (0x1E)
|
||||
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x1F)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
15
components/soc/esp32c6/include/soc/hwcrypto_reg.h
Normal file
15
components/soc/esp32c6/include/soc/hwcrypto_reg.h
Normal file
@ -0,0 +1,15 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef __HWCRYPTO_REG_H__
|
||||
#define __HWCRYPTO_REG_H__
|
||||
|
||||
#include "soc/aes_reg.h"
|
||||
#include "soc/ds_reg.h"
|
||||
#include "soc/hmac_reg.h"
|
||||
#include "soc/rsa_reg.h"
|
||||
#include "soc/sha_reg.h"
|
||||
|
||||
#endif
|
||||
19
components/soc/esp32c6/include/soc/interrupt_reg.h
Normal file
19
components/soc/esp32c6/include/soc/interrupt_reg.h
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/interrupt_matrix_reg.h"
|
||||
#include "soc/intpri_reg.h"
|
||||
#include "soc/plic_reg.h"
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
// ESP32C6 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y)
|
||||
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG
|
||||
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG
|
||||
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG
|
||||
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG
|
||||
#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
|
||||
|
||||
#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE
|
||||
91
components/soc/esp32c6/include/soc/memprot_defs.h
Normal file
91
components/soc/esp32c6/include/soc/memprot_defs.h
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp32c6/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t cat0 : 2;
|
||||
uint32_t cat1 : 2;
|
||||
uint32_t cat2 : 2;
|
||||
uint32_t res0 : 8;
|
||||
uint32_t splitaddr : 8;
|
||||
uint32_t res1 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} constrain_reg_fields_t;
|
||||
|
||||
#ifndef I_D_SRAM_SEGMENT_SIZE
|
||||
#define I_D_SRAM_SEGMENT_SIZE 0x20000
|
||||
#endif
|
||||
|
||||
#define I_D_SPLIT_LINE_SHIFT 0x9
|
||||
#define I_D_FAULT_ADDR_SHIFT 0x2
|
||||
|
||||
#define DRAM_SRAM_START 0x3FC7C000
|
||||
|
||||
//IRAM0
|
||||
|
||||
//16kB (ICACHE)
|
||||
#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000
|
||||
#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
|
||||
|
||||
//128kB (LEVEL 1)
|
||||
#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
|
||||
#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
|
||||
|
||||
//128kB (LEVEL 2)
|
||||
#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
|
||||
#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
|
||||
|
||||
//128kB (LEVEL 3)
|
||||
#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
|
||||
#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
|
||||
|
||||
//permission bits
|
||||
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
|
||||
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
|
||||
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4
|
||||
|
||||
//DRAM0
|
||||
|
||||
//16kB ICACHE not available from DRAM0
|
||||
|
||||
//128kB (LEVEL 1)
|
||||
#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000
|
||||
#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
|
||||
|
||||
//128kB (LEVEL 2)
|
||||
#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
|
||||
#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
|
||||
|
||||
//128kB (LEVEL 3)
|
||||
#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
|
||||
#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
|
||||
|
||||
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
|
||||
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
|
||||
|
||||
//RTC FAST
|
||||
|
||||
//permission bits
|
||||
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1
|
||||
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2
|
||||
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4
|
||||
|
||||
#define AREA_LOW 0
|
||||
#define AREA_HIGH 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
32
components/soc/esp32c6/include/soc/mmu.h
Normal file
32
components/soc/esp32c6/include/soc/mmu.h
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Defined for flash mmap */
|
||||
#define SOC_MMU_REGIONS_COUNT 1
|
||||
#define SOC_MMU_PAGES_PER_REGION 128
|
||||
#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -5,12 +5,11 @@
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DR_REG_PLIC_MX_BASE ( 0x20001000 )
|
||||
#define DR_REG_PLIC_UX_BASE ( 0x20001400 )
|
||||
#define PLIC_MXINT_CONF_REG ( 0x200013FC )
|
||||
#define PLIC_UXINT_CONF_REG ( 0x200017FC )
|
||||
|
||||
|
||||
@ -4,6 +4,8 @@
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DR_REG_PLIC_MX_BASE 0x20001000
|
||||
#define DR_REG_PLIC_UX_BASE 0x20001400
|
||||
#define DR_REG_CLINT_M_BASE 0x20001800
|
||||
#define DR_REG_CLINT_U_BASE 0x20001C00
|
||||
|
||||
|
||||
56
components/soc/esp32c6/include/soc/reset_reasons.h
Normal file
56
components/soc/esp32c6/include/soc/reset_reasons.h
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
//+-----------------------------------------------Terminology---------------------------------------------+
|
||||
//| |
|
||||
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
|
||||
//| |
|
||||
//| Core Reset: Reset the whole digital system except RTC sub-system |
|
||||
//| |
|
||||
//| System Reset: Reset the whole digital system, including RTC sub-system |
|
||||
//| |
|
||||
//| Chip Reset: Reset the whole chip, including the analog part |
|
||||
//| |
|
||||
//+-------------------------------------------------------------------------------------------------------+
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
// TODO: IDF-5719
|
||||
/**
|
||||
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
|
||||
* @note refer to TRM: <Reset and Clock> chapter
|
||||
*/
|
||||
typedef enum {
|
||||
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
|
||||
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
|
||||
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET
|
||||
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system)
|
||||
RESET_REASON_CORE_SDIO = 0x06, // SDIO module resets the digital core (hp system)
|
||||
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core (hp system)
|
||||
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core (hp system)
|
||||
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core (hp system)
|
||||
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
|
||||
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET
|
||||
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
|
||||
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
|
||||
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
|
||||
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
|
||||
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
|
||||
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core (hp system)
|
||||
RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system)
|
||||
RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system)
|
||||
RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
|
||||
} soc_reset_reason_t;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
832
components/soc/esp32c6/include/soc/rtc.h
Normal file
832
components/soc/esp32c6/include/soc/rtc.h
Normal file
@ -0,0 +1,832 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock, and sleep functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
* allowing state machines to control power and clocks automatically
|
||||
* - handles sleep and wakeup functions
|
||||
* - maintains a 48-bit counter which can be used for timekeeping
|
||||
*
|
||||
* These functions are not thread safe, and should not be viewed as high level
|
||||
* APIs. For example, while this file provides a function which can switch
|
||||
* CPU frequency, this function is on its own is not sufficient to implement
|
||||
* frequency switching in ESP-IDF context: some coordination with RTOS,
|
||||
* peripheral drivers, and WiFi/BT stacks is also required.
|
||||
*
|
||||
* These functions will normally not be used in applications directly.
|
||||
* ESP-IDF provides, or will provide, drivers and other facilities to use
|
||||
* RTC subsystem functionality.
|
||||
*
|
||||
* The functions are loosely split into the following groups:
|
||||
* - rtc_clk: clock switching, calibration
|
||||
* - rtc_time: reading RTC counter, conversion between counter values and time
|
||||
* - rtc_sleep: entry into sleep modes
|
||||
* - rtc_init: initialization
|
||||
*/
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
*/
|
||||
#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
|
||||
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
|
||||
#define RTC_CNTL_DBIAS_0V95 16
|
||||
#define RTC_CNTL_DBIAS_1V00 18
|
||||
#define RTC_CNTL_DBIAS_1V05 20
|
||||
#define RTC_CNTL_DBIAS_1V10 23
|
||||
#define RTC_CNTL_DBIAS_1V15 25
|
||||
#define RTC_CNTL_DBIAS_1V20 28
|
||||
#define RTC_CNTL_DBIAS_1V25 30
|
||||
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3
|
||||
#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300
|
||||
#define SOC_DELAY_RC_FAST_ENABLE 50
|
||||
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
|
||||
|
||||
/* Core voltage:
|
||||
* Currently, ESP32C3 never adjust its wake voltage in runtime
|
||||
* Only sets dig/rtc voltage dbias at startup time
|
||||
*/
|
||||
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
|
||||
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
|
||||
/*
|
||||
set sleep_init default param
|
||||
*/
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
|
||||
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
|
||||
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
typedef struct rtc_cpu_freq_config_s {
|
||||
soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived
|
||||
uint32_t source_freq_mhz; //!< Source clock frequency
|
||||
uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
|
||||
uint32_t freq_mhz; //!< CPU clock frequency
|
||||
} rtc_cpu_freq_config_t;
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
/**
|
||||
* @brief Clock source to be calibrated using rtc_clk_cal function
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
|
||||
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
|
||||
RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
|
||||
RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
|
||||
} rtc_cal_sel_t;
|
||||
|
||||
/**
|
||||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
|
||||
uint32_t clk_rtc_clk_div : 8;
|
||||
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
|
||||
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
|
||||
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
|
||||
} rtc_clk_config_t;
|
||||
|
||||
/**
|
||||
* Default initializer for rtc_clk_config_t
|
||||
*/
|
||||
#define RTC_CLK_CONFIG_DEFAULT() { \
|
||||
.xtal_freq = CONFIG_XTAL_FREQ, \
|
||||
.cpu_freq_mhz = 80, \
|
||||
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
|
||||
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
|
||||
.clk_rtc_clk_div = 0, \
|
||||
.clk_8m_clk_div = 0, \
|
||||
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
|
||||
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uint16_t wifi_powerup_cycles : 7;
|
||||
uint16_t wifi_wait_cycles : 9;
|
||||
uint16_t bt_powerup_cycles : 7;
|
||||
uint16_t bt_wait_cycles : 9;
|
||||
uint16_t cpu_top_powerup_cycles : 7;
|
||||
uint16_t cpu_top_wait_cycles : 9;
|
||||
uint16_t dg_wrap_powerup_cycles : 7;
|
||||
uint16_t dg_wrap_wait_cycles : 9;
|
||||
uint16_t dg_peri_powerup_cycles : 7;
|
||||
uint16_t dg_peri_wait_cycles : 9;
|
||||
} rtc_init_config_t;
|
||||
|
||||
#define RTC_INIT_CONFIG_DEFAULT() { \
|
||||
.wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.bt_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
}
|
||||
|
||||
void rtc_clk_divider_set(uint32_t div);
|
||||
|
||||
void rtc_clk_8m_divider_set(uint32_t div);
|
||||
|
||||
/**
|
||||
* Initialize clocks and set CPU frequency
|
||||
*
|
||||
* @param cfg clock configuration as rtc_clk_config_t
|
||||
*/
|
||||
void rtc_clk_init(rtc_clk_config_t cfg);
|
||||
|
||||
/**
|
||||
* @brief Get main XTAL frequency
|
||||
*
|
||||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
*
|
||||
* Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
|
||||
* after startup.
|
||||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
* @param en true to enable, false to disable
|
||||
*/
|
||||
void rtc_clk_32k_enable(bool en);
|
||||
|
||||
/**
|
||||
* @brief Configure 32 kHz XTAL oscillator to accept external clock signal
|
||||
*/
|
||||
void rtc_clk_32k_enable_external(void);
|
||||
|
||||
/**
|
||||
* @brief Get the state of 32k XTAL oscillator
|
||||
* @return true if 32k XTAL oscillator has been enabled
|
||||
*/
|
||||
bool rtc_clk_32k_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Enable 32k oscillator, configuring it for fast startup time.
|
||||
* Note: to achieve higher frequency stability, rtc_clk_32k_enable function
|
||||
* must be called one the 32k XTAL oscillator has started up. This function
|
||||
* will initially disable the 32k XTAL oscillator, so it should not be called
|
||||
* when the system is using 32k XTAL as RTC_SLOW_CLK.
|
||||
*
|
||||
* @param cycle Number of 32kHz cycles to bootstrap external crystal.
|
||||
* If 0, no square wave will be used to bootstrap crystal oscillation.
|
||||
*/
|
||||
void rtc_clk_32k_bootstrap(uint32_t cycle);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 8 MHz internal oscillator
|
||||
*
|
||||
* Output from 8 MHz internal oscillator is passed into a configurable
|
||||
* divider, which by default divides the input clock frequency by 256.
|
||||
* Output of the divider may be used as RTC_SLOW_CLK source.
|
||||
* Output of the divider is referred to in register descriptions and code as
|
||||
* 8md256 or simply d256. Divider values other than 256 may be configured, but
|
||||
* this facility is not currently needed, so is not exposed in the code.
|
||||
*
|
||||
* When 8MHz/256 divided output is not needed, the divider should be disabled
|
||||
* to reduce power consumption.
|
||||
*
|
||||
* @param clk_8m_en true to enable 8MHz generator
|
||||
* @param d256_en true to enable /256 divider
|
||||
*/
|
||||
void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
|
||||
|
||||
/**
|
||||
* @brief Get the state of 8 MHz internal oscillator
|
||||
* @return true if the oscillator is enabled
|
||||
*/
|
||||
bool rtc_clk_8m_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Get the state of /256 divider which is applied to 8MHz clock
|
||||
* @return true if the divided output is enabled
|
||||
*/
|
||||
bool rtc_clk_8md256_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Select source for RTC_SLOW_CLK
|
||||
* @param clk_src clock source (one of soc_rtc_slow_clk_src_t values)
|
||||
*/
|
||||
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src);
|
||||
|
||||
/**
|
||||
* @brief Get the RTC_SLOW_CLK source
|
||||
* @return currently selected clock source (one of soc_rtc_slow_clk_src_t values)
|
||||
*/
|
||||
soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
|
||||
*
|
||||
* - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000
|
||||
* - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
|
||||
* - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000
|
||||
*
|
||||
* rtc_clk_cal function can be used to get more precise value by comparing
|
||||
* RTC_SLOW_CLK frequency to the frequency of main XTAL.
|
||||
*
|
||||
* @return RTC_SLOW_CLK frequency, in Hz
|
||||
*/
|
||||
uint32_t rtc_clk_slow_freq_get_hz(void);
|
||||
|
||||
/**
|
||||
* @brief Select source for RTC_FAST_CLK
|
||||
* @param clk_src clock source (one of soc_rtc_fast_clk_src_t values)
|
||||
*/
|
||||
void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src);
|
||||
|
||||
/**
|
||||
* @brief Get the RTC_FAST_CLK source
|
||||
* @return currently selected clock source (one of soc_rtc_fast_clk_src_t values)
|
||||
*/
|
||||
soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get CPU frequency config for a given frequency
|
||||
* @param freq_mhz Frequency in MHz
|
||||
* @param[out] out_config Output, CPU frequency configuration structure
|
||||
* @return true if frequency can be obtained, false otherwise
|
||||
*/
|
||||
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency
|
||||
*
|
||||
* This function sets CPU frequency according to the given configuration
|
||||
* structure. It enables PLLs, if necessary.
|
||||
*
|
||||
* @note This function in not intended to be called by applications in FreeRTOS
|
||||
* environment. This is because it does not adjust various timers based on the
|
||||
* new CPU frequency.
|
||||
*
|
||||
* @param config CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency (optimized for speed)
|
||||
*
|
||||
* This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
|
||||
* It works faster because it does not disable PLLs when switching from PLL to
|
||||
* XTAL and does not enabled them when switching back. If PLL is not already
|
||||
* enabled when this function is called to switch from XTAL to PLL frequency,
|
||||
* or the PLL which is enabled is the wrong one, this function will fall back
|
||||
* to calling rtc_clk_cpu_freq_set_config.
|
||||
*
|
||||
* Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
|
||||
* so it is less safe to use it e.g. from a panic handler (when memory might
|
||||
* be corrupted).
|
||||
*
|
||||
* @note This function in not intended to be called by applications in FreeRTOS
|
||||
* environment. This is because it does not adjust various timers based on the
|
||||
* new CPU frequency.
|
||||
*
|
||||
* @param config CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Get the currently used CPU frequency configuration
|
||||
* @param[out] out_config Output, CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU clock source to XTAL
|
||||
*
|
||||
* Short form for filling in rtc_cpu_freq_config_t structure and calling
|
||||
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
|
||||
* Assumes that XTAL frequency has been determined — don't call in startup code.
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_xtal(void);
|
||||
|
||||
/**
|
||||
* @brief Store new APB frequency value into RTC_APB_FREQ_REG
|
||||
*
|
||||
* This function doesn't change any hardware clocks.
|
||||
*
|
||||
* Functions which perform frequency switching and change APB frequency call
|
||||
* this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
|
||||
* (one of RTC general purpose retention registers). This should not normally
|
||||
* be called from application code.
|
||||
*
|
||||
* @param apb_freq new APB frequency, in Hz
|
||||
*/
|
||||
void rtc_clk_apb_freq_update(uint32_t apb_freq);
|
||||
|
||||
/**
|
||||
* @brief Get the current stored APB frequency.
|
||||
* @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
|
||||
*/
|
||||
uint32_t rtc_clk_apb_freq_get(void);
|
||||
|
||||
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Measure RTC slow clock's period, based on main XTAL frequency
|
||||
*
|
||||
* This function will time out and return 0 if the time for the given number
|
||||
* of cycles to be counted exceeds the expected time twice. This may happen if
|
||||
* 32k XTAL is being calibrated, but the oscillator has not started up (due to
|
||||
* incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
|
||||
*
|
||||
* @param cal_clk clock to be measured
|
||||
* @param slow_clk_cycles number of slow clock cycles to average
|
||||
* @return average slow clock period in microseconds, Q13.19 fixed point format,
|
||||
* or 0 if calibration has timed out
|
||||
*/
|
||||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
|
||||
* @param cal_clk slow clock to be measured
|
||||
* @param slow_clk_cycles number of slow clock cycles to average
|
||||
* @return average ratio between XTAL frequency and slow clock frequency,
|
||||
* Q13.19 fixed point format, or 0 if calibration has timed out.
|
||||
*/
|
||||
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
|
||||
* @param time_in_us Time interval in microseconds
|
||||
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
|
||||
* fixed point format (as returned by rtc_slowck_cali).
|
||||
* @return number of slow clock cycles
|
||||
*/
|
||||
uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
|
||||
|
||||
/**
|
||||
* @brief Convert time interval from RTC_SLOW_CLK to microseconds
|
||||
* @param time_in_us Time interval in RTC_SLOW_CLK cycles
|
||||
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
|
||||
* fixed point format (as returned by rtc_slowck_cali).
|
||||
* @return time interval in microseconds
|
||||
*/
|
||||
uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
|
||||
|
||||
/**
|
||||
* @brief Get current value of RTC counter
|
||||
*
|
||||
* RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
|
||||
* cycles. Counter value is not writable by software. The value is not adjusted
|
||||
* when switching to a different RTC_SLOW_CLK source.
|
||||
*
|
||||
* Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
|
||||
*
|
||||
* @return current value of RTC counter
|
||||
*/
|
||||
uint64_t rtc_time_get(void);
|
||||
|
||||
uint64_t rtc_light_slp_time_get(void);
|
||||
|
||||
uint64_t rtc_deep_slp_time_get(void);
|
||||
|
||||
/**
|
||||
* @brief Busy loop until next RTC_SLOW_CLK cycle
|
||||
*
|
||||
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
|
||||
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
|
||||
* one RTC_SLOW_CLK cycle later.
|
||||
*/
|
||||
void rtc_clk_wait_for_slow_cycle(void);
|
||||
|
||||
/**
|
||||
* @brief Enable the rtc digital 8M clock
|
||||
*
|
||||
* This function is used to enable the digital rtc 8M clock to support peripherals.
|
||||
* For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
|
||||
*/
|
||||
void rtc_dig_clk8m_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable the rtc digital 8M clock
|
||||
*
|
||||
* This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
|
||||
*/
|
||||
void rtc_dig_clk8m_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Get whether the rtc digital 8M clock is enabled
|
||||
*/
|
||||
bool rtc_dig_8m_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Calculate the real clock value after the clock calibration
|
||||
*
|
||||
* @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal`
|
||||
* @return Frequency of the clock in Hz
|
||||
*/
|
||||
uint32_t rtc_clk_freq_cal(uint32_t cal_val);
|
||||
|
||||
/**
|
||||
* @brief Power down flags for rtc_sleep_pd function
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep
|
||||
uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep
|
||||
uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep
|
||||
uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep
|
||||
uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep
|
||||
uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep
|
||||
} rtc_sleep_pu_config_t;
|
||||
|
||||
/**
|
||||
* Initializer for rtc_sleep_pu_config_t which sets all flags to the same value
|
||||
*/
|
||||
#define RTC_SLEEP_PU_CONFIG_ALL(val) {\
|
||||
.dig_fpu = (val), \
|
||||
.rtc_fpu = (val), \
|
||||
.cpu_fpu = (val), \
|
||||
.i2s_fpu = (val), \
|
||||
.bb_fpu = (val), \
|
||||
.nrx_fpu = (val), \
|
||||
.fe_fpu = (val), \
|
||||
.sram_fpu = (val), \
|
||||
.rom_ram_fpu = (val), \
|
||||
}
|
||||
|
||||
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg);
|
||||
|
||||
/**
|
||||
* @brief sleep configuration for rtc_sleep_init function
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
|
||||
uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
|
||||
uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
|
||||
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
|
||||
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
|
||||
uint32_t wifi_pd_en : 1; //!< power down WiFi
|
||||
uint32_t bt_pd_en : 1; //!< power down BT
|
||||
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
|
||||
uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
|
||||
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
|
||||
uint32_t deep_slp : 1; //!< power down digital domain
|
||||
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
|
||||
uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
|
||||
uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode
|
||||
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
|
||||
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
|
||||
uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode
|
||||
uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode
|
||||
uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode
|
||||
uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode
|
||||
uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode
|
||||
uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode
|
||||
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
|
||||
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
|
||||
uint32_t deep_slp_reject : 1; //!< enable deep sleep reject
|
||||
uint32_t light_slp_reject : 1; //!< enable light sleep reject
|
||||
} rtc_sleep_config_t;
|
||||
|
||||
#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)
|
||||
#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals
|
||||
#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory
|
||||
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
|
||||
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
|
||||
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
|
||||
#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI
|
||||
#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT
|
||||
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
|
||||
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
|
||||
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
|
||||
#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL
|
||||
|
||||
//These flags are not power domains, but will affect some sleep parameters
|
||||
#define RTC_SLEEP_DIG_USE_8M BIT(16)
|
||||
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
|
||||
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
|
||||
|
||||
/**
|
||||
* Default initializer for rtc_sleep_config_t
|
||||
*
|
||||
* This initializer sets all fields to "reasonable" values (e.g. suggested for
|
||||
* production use) based on a combination of RTC_SLEEP_PD_x flags.
|
||||
*
|
||||
* @param RTC_SLEEP_PD_x flags combined using bitwise OR
|
||||
*/
|
||||
void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config);
|
||||
|
||||
/**
|
||||
* @brief Prepare the chip to enter sleep mode
|
||||
*
|
||||
* This function configures various power control state machines to handle
|
||||
* entry into light sleep or deep sleep mode, switches APB and CPU clock source
|
||||
* (usually to XTAL), and sets bias voltages for digital and RTC power domains.
|
||||
*
|
||||
* This function does not actually enter sleep mode; this is done using
|
||||
* rtc_sleep_start function. Software may do some other actions between
|
||||
* rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
|
||||
* wakeup sources.
|
||||
* @param cfg sleep mode configuration
|
||||
*/
|
||||
void rtc_sleep_init(rtc_sleep_config_t cfg);
|
||||
|
||||
/**
|
||||
* @brief Low level initialize for rtc state machine waiting cycles after waking up
|
||||
*
|
||||
* This function configures the cycles chip need to wait for internal 8MHz
|
||||
* oscillator and external 40MHz crystal. As we configure fixed time for waiting
|
||||
* crystal, we need to pass period to calculate cycles. Now this function only
|
||||
* used in lightsleep mode.
|
||||
*
|
||||
* @param slowclk_period re-calibrated slow clock period
|
||||
*/
|
||||
void rtc_sleep_low_init(uint32_t slowclk_period);
|
||||
|
||||
/**
|
||||
* @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
|
||||
* @param t value of RTC counter at which wakeup from sleep will happen;
|
||||
* only the lower 48 bits are used
|
||||
*/
|
||||
void rtc_sleep_set_wakeup_time(uint64_t t);
|
||||
|
||||
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup
|
||||
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
|
||||
#define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI wakeup (light sleep only)
|
||||
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
|
||||
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
|
||||
#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
|
||||
#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12)
|
||||
#define RTC_USB_TRIG_EN BIT(14)
|
||||
#define RTC_BROWNOUT_DET_TRIG_EN BIT(16)
|
||||
|
||||
/**
|
||||
* RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip
|
||||
*/
|
||||
#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN | \
|
||||
RTC_TIMER_TRIG_EN | \
|
||||
RTC_WIFI_TRIG_EN | \
|
||||
RTC_UART0_TRIG_EN | \
|
||||
RTC_UART1_TRIG_EN | \
|
||||
RTC_BT_TRIG_EN | \
|
||||
RTC_XTAL32K_DEAD_TRIG_EN | \
|
||||
RTC_USB_TRIG_EN | \
|
||||
RTC_BROWNOUT_DET_TRIG_EN)
|
||||
|
||||
/**
|
||||
* @brief Enter deep or light sleep mode
|
||||
*
|
||||
* This function enters the sleep mode previously configured using rtc_sleep_init
|
||||
* function. Before entering sleep, software should configure wake up sources
|
||||
* appropriately (set up GPIO wakeup registers, timer wakeup registers,
|
||||
* and so on).
|
||||
*
|
||||
* If deep sleep mode was configured using rtc_sleep_init, and sleep is not
|
||||
* rejected by hardware (based on reject_opt flags), this function never returns.
|
||||
* When the chip wakes up from deep sleep, CPU is reset and execution starts
|
||||
* from ROM bootloader.
|
||||
*
|
||||
* If light sleep mode was configured using rtc_sleep_init, this function
|
||||
* returns on wakeup, or if sleep is rejected by hardware.
|
||||
*
|
||||
* @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
|
||||
* combined with OR)
|
||||
* @param reject_opt bit mask of sleep reject reasons:
|
||||
* - RTC_CNTL_GPIO_REJECT_EN
|
||||
* - RTC_CNTL_SDIO_REJECT_EN
|
||||
* These flags are used to prevent entering sleep when e.g.
|
||||
* an external host is communicating via SDIO slave
|
||||
* @return non-zero if sleep was rejected by hardware
|
||||
*/
|
||||
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
|
||||
|
||||
/**
|
||||
* @brief Enter deep sleep mode
|
||||
*
|
||||
* Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value
|
||||
* of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake
|
||||
* stub is valid to execute (if a wake address is set).
|
||||
*
|
||||
* No RAM is accessed while calculating the CRC and going into deep sleep, which makes
|
||||
* this function safe to use even if the caller's stack is in RTC FAST memory.
|
||||
*
|
||||
* @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will
|
||||
* have the same effect and takes less time as CRC calculation is skipped.
|
||||
*
|
||||
* @note This function should only be called after rtc_sleep_init() has been called to
|
||||
* configure the system for deep sleep.
|
||||
*
|
||||
* @param wakeup_opt - same as for rtc_sleep_start
|
||||
* @param reject_opt - same as for rtc_sleep_start
|
||||
*
|
||||
* @return non-zero if sleep was rejected by hardware
|
||||
*/
|
||||
uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
|
||||
|
||||
/**
|
||||
* RTC power and clock control initialization settings
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
|
||||
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
|
||||
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
|
||||
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
|
||||
uint32_t pwrctl_init : 1; //!< Perform power control related initialization
|
||||
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
|
||||
uint32_t xtal_fpu : 1;
|
||||
uint32_t bbpll_fpu : 1;
|
||||
uint32_t cpu_waiti_clk_gate : 1;
|
||||
uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise.
|
||||
} rtc_config_t;
|
||||
|
||||
/**
|
||||
* Default initializer of rtc_config_t.
|
||||
*
|
||||
* This initializer sets all fields to "reasonable" values (e.g. suggested for
|
||||
* production use).
|
||||
*/
|
||||
#define RTC_CONFIG_DEFAULT() {\
|
||||
.ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
|
||||
.xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
|
||||
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
|
||||
.clkctl_init = 1, \
|
||||
.pwrctl_init = 1, \
|
||||
.rtc_dboost_fpd = 1, \
|
||||
.xtal_fpu = 0, \
|
||||
.bbpll_fpu = 0, \
|
||||
.cpu_waiti_clk_gate = 1, \
|
||||
.cali_ocode = 0\
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize RTC clock and power control related functions
|
||||
* @param cfg configuration options as rtc_config_t
|
||||
*/
|
||||
void rtc_init(rtc_config_t cfg);
|
||||
|
||||
/**
|
||||
* Structure describing vddsdio configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
|
||||
uint32_t enable : 1; //!< Enable VDDSDIO regulator
|
||||
uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
|
||||
uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator
|
||||
uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator
|
||||
uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator
|
||||
} rtc_vddsdio_config_t;
|
||||
|
||||
/**
|
||||
* Get current VDDSDIO configuration
|
||||
* If VDDSDIO configuration is overridden by RTC, get values from RTC
|
||||
* Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
|
||||
* Otherwise, use default values and the level of MTDI bootstrapping pin.
|
||||
* @return currently used VDDSDIO configuration
|
||||
*/
|
||||
rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
|
||||
|
||||
/**
|
||||
* Set new VDDSDIO configuration using RTC registers.
|
||||
* If config.force == 1, this overrides configuration done using bootstrapping
|
||||
* pins and EFUSE.
|
||||
*
|
||||
* @param config new VDDSDIO configuration
|
||||
*/
|
||||
void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
|
||||
|
||||
|
||||
// -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
|
||||
// **WARNING**: The following are only for backwards compatibility.
|
||||
// Please use the declarations in soc/clk_tree_defs.h instead.
|
||||
/**
|
||||
* @brief CPU clock source
|
||||
*/
|
||||
typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
|
||||
#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL
|
||||
#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M or 320M)
|
||||
#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
|
||||
|
||||
/**
|
||||
* @brief RTC SLOW_CLK frequency values
|
||||
*/
|
||||
typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
|
||||
#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator
|
||||
#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL
|
||||
#define RTC_SLOW_FREQ_8MD256 SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 //!< Internal 17.5 MHz RC oscillator, divided by 256
|
||||
|
||||
/**
|
||||
* @brief RTC FAST_CLK frequency values
|
||||
*/
|
||||
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
||||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX
|
||||
#define RTC_SLOW_CLK_FREQ_8MD256 SOC_CLK_RC_FAST_D256_FREQ_APPROX
|
||||
#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX
|
||||
|
||||
/* Alias of deprecated function names */
|
||||
#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq)
|
||||
#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get()
|
||||
#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq)
|
||||
#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get()
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
262
components/soc/esp32c6/include/soc/soc.h
Normal file
262
components/soc/esp32c6/include/soc/soc.h
Normal file
@ -0,0 +1,262 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#include "esp_assert.h"
|
||||
#endif
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
#include "reg_base.h"
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
|
||||
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6
|
||||
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
|
||||
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
|
||||
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
|
||||
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
|
||||
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
|
||||
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6
|
||||
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6
|
||||
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6
|
||||
#define REG_TWAI_BASE(i) (DR_REG_TWAI_BASE + (i) * 0x2000) // TWAI0 and TWAI1
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) do { \
|
||||
(*(volatile uint32_t *)(_r)) = (_v); \
|
||||
} while(0)
|
||||
|
||||
//read value from register
|
||||
#define REG_READ(_r) ({ \
|
||||
(*(volatile uint32_t *)(_r)); \
|
||||
})
|
||||
|
||||
//get bit or get bits from register
|
||||
#define REG_GET_BIT(_r, _b) ({ \
|
||||
(*(volatile uint32_t*)(_r) & (_b)); \
|
||||
})
|
||||
|
||||
//set bit or set bits to register
|
||||
#define REG_SET_BIT(_r, _b) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \
|
||||
} while(0)
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define REG_CLR_BIT(_r, _b) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \
|
||||
} while(0)
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define REG_SET_BITS(_r, _b, _m) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \
|
||||
} while(0)
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define REG_GET_FIELD(_r, _f) ({ \
|
||||
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
|
||||
})
|
||||
|
||||
//set field of a register from variable, uses field _S & _V to determine mask
|
||||
#define REG_SET_FIELD(_r, _f, _v) do { \
|
||||
REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \
|
||||
} while(0)
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//read value from register
|
||||
#define READ_PERI_REG(addr) ({ \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
|
||||
})
|
||||
|
||||
//write value to register
|
||||
#define WRITE_PERI_REG(addr, val) do { \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
|
||||
} while(0)
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define CLEAR_PERI_REG_MASK(reg, mask) do { \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
|
||||
} while(0)
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define SET_PERI_REG_MASK(reg, mask) do { \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
|
||||
} while(0)
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define GET_PERI_REG_MASK(reg, mask) ({ \
|
||||
(READ_PERI_REG(reg) & (mask)); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
|
||||
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \
|
||||
WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \
|
||||
} while(0)
|
||||
|
||||
//get field of register
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
|
||||
((READ_PERI_REG(reg)>>(shift))&(mask)); \
|
||||
})
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
//}}
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM ( 40*1000000 )
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
|
||||
#define CPU_CLK_FREQ APB_CLK_FREQ
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
#define APB_CLK_FREQ ( 40*1000000 )
|
||||
#else
|
||||
#define APB_CLK_FREQ ( 80*1000000 )
|
||||
#endif
|
||||
#define REF_CLK_FREQ ( 1000000 )
|
||||
#define RTC_CLK_FREQ (20*1000000)
|
||||
#define XTAL_CLK_FREQ (40*1000000)
|
||||
#define UART_CLK_FREQ APB_CLK_FREQ
|
||||
#define WDT_CLK_FREQ APB_CLK_FREQ
|
||||
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
||||
#define SPI_CLK_DIV 4
|
||||
#define TICKS_PER_US_ROM 40 // CPU is 80MHz
|
||||
#define GPIO_MATRIX_DELAY_NS 0
|
||||
//}}
|
||||
|
||||
/* Overall memory map */
|
||||
/* Note: We should not use MACROs similar in cache_memory.h
|
||||
* those are defined during run-time. But the MACROs here
|
||||
* should be defined statically!
|
||||
*/
|
||||
|
||||
#define SOC_IROM_LOW 0x42000000
|
||||
#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<7))
|
||||
#define SOC_DROM_LOW SOC_IROM_HIGH
|
||||
#define SOC_DROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
|
||||
#define SOC_IROM_MASK_LOW 0x40000000
|
||||
#define SOC_IROM_MASK_HIGH 0x4004AC00
|
||||
#define SOC_DROM_MASK_LOW 0x4004AC00
|
||||
#define SOC_DROM_MASK_HIGH 0x40050000
|
||||
#define SOC_IRAM_LOW 0x40800000
|
||||
#define SOC_IRAM_HIGH 0x40880000
|
||||
#define SOC_DRAM_LOW 0x40800000
|
||||
#define SOC_DRAM_HIGH 0x40880000
|
||||
#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C6 only has 16k LP memory
|
||||
#define SOC_RTC_IRAM_HIGH 0x50004000
|
||||
#define SOC_RTC_DRAM_LOW 0x50000000
|
||||
#define SOC_RTC_DRAM_HIGH 0x50004000
|
||||
#define SOC_RTC_DATA_LOW 0x50000000
|
||||
#define SOC_RTC_DATA_HIGH 0x50004000
|
||||
|
||||
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
|
||||
#define SOC_DIRAM_IRAM_LOW 0x40800000
|
||||
#define SOC_DIRAM_IRAM_HIGH 0x40880000
|
||||
#define SOC_DIRAM_DRAM_LOW 0x40800000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x40880000
|
||||
|
||||
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x40800000
|
||||
#define SOC_DMA_HIGH 0x40880000
|
||||
|
||||
// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
|
||||
#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000
|
||||
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40880000
|
||||
|
||||
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
|
||||
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
|
||||
#define SOC_MEM_INTERNAL_LOW 0x40800000
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x40880000
|
||||
#define SOC_MEM_INTERNAL_LOW1 0x40800000
|
||||
#define SOC_MEM_INTERNAL_HIGH1 0x40880000
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
// Region of address space that holds peripherals
|
||||
#define SOC_PERIPHERAL_LOW 0x60000000
|
||||
#define SOC_PERIPHERAL_HIGH 0x60100000
|
||||
|
||||
// Debug region, not used by software
|
||||
#define SOC_DEBUG_LOW 0x20000000
|
||||
#define SOC_DEBUG_HIGH 0x28000000
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x4087c770
|
||||
|
||||
|
||||
// ESP32C6-TODO @wanglei Need check
|
||||
/* Defined for flash mmap */
|
||||
#define REGIONS_COUNT 2
|
||||
#define PAGES_PER_REGION 256
|
||||
#define IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t))
|
||||
#define IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
||||
#define DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||
#define DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
||||
#define VALID_ENTRY_VAL MMU_TABLE_VALID_VAL
|
||||
#define MMU_ADDR_MASK MMU_ADDRESS_MASK
|
||||
#define PAGE_IN_FLASH(page) ((page) | MMU_MSPI_VALID) // ESP32C6-TODO
|
||||
#define VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
#define PRO_IRAM0_FIRST_USABLE_PAGE IROM0_PAGES_START
|
||||
#define VADDR0_START_ADDR DRAM0_CACHE_ADDRESS_LOW
|
||||
#define VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
|
||||
|
||||
|
||||
|
||||
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
|
||||
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
|
||||
|
||||
//CPU0 Interrupt number reserved in riscv/vector.S, not touch this.
|
||||
#define ETS_T1_WDT_INUM 24
|
||||
#define ETS_CACHEERR_INUM 25
|
||||
#define ETS_MEMPROT_ERR_INUM 26
|
||||
//CPU0 Max valid interrupt number
|
||||
#define ETS_MAX_INUM 31
|
||||
|
||||
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
||||
#define ETS_SLC_INUM 1
|
||||
#define ETS_UART0_INUM 5
|
||||
#define ETS_UART1_INUM 5
|
||||
#define ETS_SPI2_INUM 1
|
||||
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
|
||||
#define ETS_GPIO_INUM 4
|
||||
|
||||
//Other interrupt number should be managed by the user
|
||||
|
||||
//Invalid interrupt for number interrupt matrix
|
||||
#define ETS_INVALID_INUM 0
|
||||
|
||||
//Interrupt medium level, used for INT WDT for example
|
||||
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
|
||||
405
components/soc/esp32c6/include/soc/soc_caps.h
Normal file
405
components/soc/esp32c6/include/soc/soc_caps.h
Normal file
@ -0,0 +1,405 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The long term plan is to have a single soc_caps.h for each peripheral.
|
||||
// During the refactoring and multichip support development process, we
|
||||
// seperate these information into periph_caps.h for each peripheral and
|
||||
// include them here.
|
||||
|
||||
/*
|
||||
* These defines are parsed and imported as kconfig variables via the script
|
||||
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
|
||||
*
|
||||
* If this file is changed the script will automatically run the script
|
||||
* and generate the kconfig variables as part of the pre-commit hooks.
|
||||
*
|
||||
* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c6/include/soc/'`
|
||||
*
|
||||
* For more information see `tools/gen_soc_caps_kconfig/README.md`
|
||||
*
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/*-------------------------- COMMON CAPS ---------------------------------------*/
|
||||
// #define SOC_ADC_SUPPORTED 1 // TODO: IDF-5310
|
||||
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: IDF-5331
|
||||
#define SOC_GDMA_SUPPORTED 1
|
||||
// #define SOC_TWAI_SUPPORTED 1 // TODO: IDF-5313
|
||||
#define SOC_BT_SUPPORTED 1
|
||||
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
|
||||
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
|
||||
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: IDF-5322
|
||||
#define SOC_WIFI_SUPPORTED 1
|
||||
#define SOC_SUPPORTS_SECURE_DL_MODE 1
|
||||
#define SOC_RISCV_COPROC_SUPPORTED 1
|
||||
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
|
||||
#define SOC_EFUSE_HAS_EFUSE_RST_BUG 1
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_MEM_SUPPORTED 1
|
||||
// #define SOC_I2S_SUPPORTED 1 // TODO: IDF-5314
|
||||
// #define SOC_RMT_SUPPORTED 1 // TODO: IDF-5320
|
||||
// #define SOC_SDM_SUPPORTED 1 // TODO: IDF-5318
|
||||
// #define SOC_LEDC_SUPPORTED 1 // TODO: IDF-5328
|
||||
// #define SOC_I2C_SUPPORTED 1 // TODO: IDF-5326
|
||||
#define SOC_SYSTIMER_SUPPORTED 1
|
||||
#define SOC_SUPPORT_COEXISTENCE 1
|
||||
// #define SOC_AES_SUPPORTED 1 // TODO: IDF-5356
|
||||
// #define SOC_MPI_SUPPORTED 1
|
||||
// #define SOC_SHA_SUPPORTED 1 // TODO: IDF-5353
|
||||
// #define SOC_HMAC_SUPPORTED 1 // TODO: IDF-5355
|
||||
// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: IDF-5360
|
||||
#define SOC_FLASH_ENC_SUPPORTED 1
|
||||
#define SOC_SECURE_BOOT_SUPPORTED 1
|
||||
// #define SOC_MEMPROT_SUPPORTED 1 // TODO: IDF-5684
|
||||
|
||||
/*-------------------------- XTAL CAPS ---------------------------------------*/
|
||||
#define SOC_XTAL_SUPPORT_40M 1
|
||||
|
||||
// TODO: IDF-5356 (Copy from esp32c3, need check)
|
||||
/*-------------------------- AES CAPS -----------------------------------------*/
|
||||
#define SOC_AES_SUPPORT_DMA (1)
|
||||
|
||||
/* Has a centralized DMA, which is shared with all peripherals */
|
||||
#define SOC_AES_GDMA (1)
|
||||
|
||||
#define SOC_AES_SUPPORT_AES_128 (1)
|
||||
#define SOC_AES_SUPPORT_AES_256 (1)
|
||||
|
||||
// TODO: IDF-5310 (Copy from esp32c3, need check)
|
||||
/*-------------------------- ADC CAPS -------------------------------*/
|
||||
/*!< SAR ADC Module*/
|
||||
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
|
||||
#define SOC_ADC_ARBITER_SUPPORTED 1
|
||||
#define SOC_ADC_FILTER_SUPPORTED 1
|
||||
#define SOC_ADC_MONITOR_SUPPORTED 1
|
||||
#define SOC_ADC_PERIPH_NUM (2)
|
||||
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
|
||||
#define SOC_ADC_MAX_CHANNEL_NUM (5)
|
||||
#define SOC_ADC_ATTEN_NUM (4)
|
||||
|
||||
/*!< Digital */
|
||||
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
|
||||
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
|
||||
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
|
||||
#define SOC_ADC_DIGI_FILTER_NUM (2)
|
||||
#define SOC_ADC_DIGI_MONITOR_NUM (2)
|
||||
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
|
||||
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
|
||||
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
|
||||
|
||||
/*!< RTC */
|
||||
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
|
||||
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
|
||||
|
||||
/*!< Calibration */
|
||||
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (0) /*!< support HW offset calibration version 1*/
|
||||
|
||||
// ESP32C6-TODO: Copy from esp32c6, need check
|
||||
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
|
||||
#define SOC_APB_BACKUP_DMA (0)
|
||||
|
||||
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
|
||||
#define SOC_BROWNOUT_RESET_SUPPORTED 1
|
||||
|
||||
/*-------------------------- CACHE CAPS --------------------------------------*/
|
||||
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
|
||||
|
||||
/*-------------------------- CPU CAPS ----------------------------------------*/
|
||||
#define SOC_CPU_CORES_NUM (1U)
|
||||
#define SOC_CPU_INTR_NUM 32
|
||||
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
|
||||
#define SOC_RV32A_SUPPORTED 1
|
||||
#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller
|
||||
|
||||
#define SOC_CPU_BREAKPOINTS_NUM 4
|
||||
#define SOC_CPU_WATCHPOINTS_NUM 4
|
||||
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
|
||||
|
||||
// TODO: IDF-5339 (Copy from esp32c3, need check)
|
||||
/*-------------------------- MMU CAPS ----------------------------------------*/
|
||||
#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
|
||||
|
||||
// TODO: IDF-5360 (Copy from esp32c3, need check)
|
||||
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
|
||||
/** The maximum length of a Digital Signature in bits. */
|
||||
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
|
||||
|
||||
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
|
||||
#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
|
||||
|
||||
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
|
||||
See TRM DS chapter for more details */
|
||||
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
|
||||
|
||||
// TODO: IDF-5319 (Copy from esp32c3, need check)
|
||||
/*-------------------------- GDMA CAPS -------------------------------------*/
|
||||
#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
|
||||
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
|
||||
|
||||
// TODO: IDF-5321 (Copy from esp32c3, need check)
|
||||
/*-------------------------- GPIO CAPS ---------------------------------------*/
|
||||
// ESP32-C6 has 1 GPIO peripheral
|
||||
#define SOC_GPIO_PORT (1U)
|
||||
#define SOC_GPIO_PIN_COUNT (31)
|
||||
|
||||
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
|
||||
// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
|
||||
#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1)
|
||||
// Force hold is a new function of ESP32-C6
|
||||
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
|
||||
// GPIO0~5 on ESP32C6 can support chip deep sleep wakeup
|
||||
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
|
||||
|
||||
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
|
||||
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
|
||||
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
|
||||
|
||||
// Support to configure sleep status
|
||||
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
|
||||
|
||||
// TODO: IDF-5331 (Copy from esp32c3, need check)
|
||||
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
|
||||
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
|
||||
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
|
||||
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
|
||||
|
||||
// TODO: IDF-5326 (Copy from esp32c3, need check)
|
||||
/*-------------------------- I2C CAPS ----------------------------------------*/
|
||||
// ESP32-C6 has 1 I2C
|
||||
#define SOC_I2C_NUM (1U)
|
||||
|
||||
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
|
||||
#define SOC_I2C_SUPPORT_SLAVE (1)
|
||||
|
||||
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
|
||||
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
|
||||
|
||||
#define SOC_I2C_SUPPORT_XTAL (1)
|
||||
#define SOC_I2C_SUPPORT_RTC (1)
|
||||
|
||||
// TODO: IDF-5314 (Copy from esp32c3, need check)
|
||||
/*-------------------------- I2S CAPS ----------------------------------------*/
|
||||
#define SOC_I2S_NUM (1)
|
||||
#define SOC_I2S_HW_VERSION_2 (1)
|
||||
#define SOC_I2S_SUPPORTS_PCM (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM_TX (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM_CODEC (1)
|
||||
#define SOC_I2S_SUPPORTS_TDM (1)
|
||||
|
||||
// TODO: IDF-5328 (Copy from esp32c3, need check)
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#define SOC_LEDC_SUPPORT_APB_CLOCK (1)
|
||||
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
|
||||
#define SOC_LEDC_CHANNEL_NUM (6)
|
||||
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
|
||||
#define SOC_LEDC_SUPPORT_FADE_STOP (1)
|
||||
|
||||
// TODO: IDF-5684 (Copy from esp32c3, need check)
|
||||
/*-------------------------- MPU CAPS ----------------------------------------*/
|
||||
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
|
||||
#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
|
||||
#define SOC_MPU_REGIONS_MAX_NUM 8
|
||||
#define SOC_MPU_REGION_RO_SUPPORTED 0
|
||||
#define SOC_MPU_REGION_WO_SUPPORTED 0
|
||||
|
||||
// TODO: IDF-5320 (Copy from esp32c3, need check)
|
||||
/*--------------------------- RMT CAPS ---------------------------------------*/
|
||||
#define SOC_RMT_GROUPS 1U /*!< One RMT group */
|
||||
#define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
|
||||
#define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
|
||||
#define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
|
||||
#define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
|
||||
#define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
|
||||
#define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
|
||||
#define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
|
||||
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
|
||||
#define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
|
||||
#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
|
||||
#define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
|
||||
#define SOC_RMT_SUPPORT_APB 1 /*!< Support set APB as the RMT clock source */
|
||||
#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST clock as the RMT clock source */
|
||||
|
||||
// TODO: IDF-5348 (Copy from esp32c3, need check)
|
||||
/*-------------------------- RTC CAPS --------------------------------------*/
|
||||
#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
|
||||
#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
|
||||
#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
|
||||
#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
|
||||
|
||||
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
|
||||
|
||||
/*-------------------------- RTCIO CAPS --------------------------------------*/
|
||||
/* No dedicated RTCIO subsystem on ESP32-C6. RTC functions are still supported
|
||||
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
|
||||
#define SOC_RTCIO_PIN_COUNT (0U)
|
||||
|
||||
// TODO: IDF-5359 (Copy from esp32c3, need check)
|
||||
/*--------------------------- RSA CAPS ---------------------------------------*/
|
||||
#define SOC_RSA_MAX_BIT_LEN (3072)
|
||||
|
||||
// TODO: IDF-5353 (Copy from esp32c3, need check)
|
||||
/*--------------------------- SHA CAPS ---------------------------------------*/
|
||||
|
||||
/* Max amount of bytes in a single DMA operation is 4095,
|
||||
for SHA this means that the biggest safe amount of bytes is
|
||||
31 blocks of 128 bytes = 3968
|
||||
*/
|
||||
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
|
||||
#define SOC_SHA_SUPPORT_DMA (1)
|
||||
|
||||
/* The SHA engine is able to resume hashing from a user */
|
||||
#define SOC_SHA_SUPPORT_RESUME (1)
|
||||
|
||||
/* Has a centralized DMA, which is shared with all peripherals */
|
||||
#define SOC_SHA_GDMA (1)
|
||||
|
||||
/* Supported HW algorithms */
|
||||
#define SOC_SHA_SUPPORT_SHA1 (1)
|
||||
#define SOC_SHA_SUPPORT_SHA224 (1)
|
||||
#define SOC_SHA_SUPPORT_SHA256 (1)
|
||||
|
||||
// TODO: IDF-5318 (Copy from esp32c3, need check)
|
||||
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
|
||||
#define SOC_SDM_GROUPS 1U
|
||||
#define SOC_SDM_CHANNELS_PER_GROUP 4
|
||||
|
||||
// TODO: IDF-5334 (Copy from esp32c3, need check)
|
||||
/*-------------------------- SPI CAPS ----------------------------------------*/
|
||||
#define SOC_SPI_PERIPH_NUM 2
|
||||
#define SOC_SPI_PERIPH_CS_NUM(i) 6
|
||||
|
||||
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
|
||||
|
||||
#define SOC_SPI_SUPPORT_DDRCLK 1
|
||||
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
|
||||
#define SOC_SPI_SUPPORT_CD_SIG 1
|
||||
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
|
||||
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
|
||||
|
||||
// Peripheral supports DIO, DOUT, QIO, or QOUT
|
||||
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
|
||||
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
|
||||
|
||||
// Peripheral supports output given level during its "dummy phase"
|
||||
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
|
||||
|
||||
#define SOC_MEMSPI_IS_INDEPENDENT 1
|
||||
#define SOC_SPI_MAX_PRE_DIVIDER 16
|
||||
|
||||
// TODO: IDF-5333 (Copy from esp32c3, need check)
|
||||
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
|
||||
|
||||
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
|
||||
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
|
||||
#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
|
||||
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
|
||||
|
||||
// TODO: IDF-5323 (Copy from esp32c3, need check)
|
||||
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
|
||||
#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
|
||||
#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
|
||||
#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
|
||||
#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part
|
||||
#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5
|
||||
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
|
||||
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
|
||||
|
||||
// TODO: IDF-5332 (Copy from esp32c3, need check)
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_GROUPS (2)
|
||||
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
|
||||
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_APB (1)
|
||||
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
|
||||
|
||||
// TODO: IDF-5313 (Copy from esp32c3, need check)
|
||||
/*-------------------------- TWAI CAPS ---------------------------------------*/
|
||||
#define SOC_TWAI_BRP_MIN 2
|
||||
#define SOC_TWAI_BRP_MAX 16384
|
||||
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
|
||||
|
||||
// TODO: IDF-5357 (Copy from esp32c3, need check)
|
||||
/*-------------------------- Secure Boot CAPS----------------------------*/
|
||||
#define SOC_SECURE_BOOT_V2_RSA 1
|
||||
#define SOC_SECURE_BOOT_V2_ECC 1
|
||||
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
|
||||
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
|
||||
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
|
||||
|
||||
// TODO: IDF-5358 (Copy from esp32c3, need check)
|
||||
/*-------------------------- Flash Encryption CAPS----------------------------*/
|
||||
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
|
||||
|
||||
// TODO: IDF-5684 (Copy from esp32c3, need check)
|
||||
/*-------------------------- MEMPROT CAPS ------------------------------------*/
|
||||
#define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16
|
||||
#define SOC_MEMPROT_MEM_ALIGN_SIZE 512
|
||||
|
||||
// TODO: IDF-5338 (Copy from esp32c3, need check)
|
||||
/*-------------------------- UART CAPS ---------------------------------------*/
|
||||
// ESP32-C6 has 2 UARTs
|
||||
#define SOC_UART_NUM (2)
|
||||
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
|
||||
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
|
||||
|
||||
#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
|
||||
#define SOC_UART_SUPPORT_RTC_CLK (0) /*!< Support RTC clock as the clock source */ // TODO: IDF-5338
|
||||
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
|
||||
// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: IDF-5338
|
||||
#define SOC_UART_REQUIRE_CORE_RESET (1)
|
||||
|
||||
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
|
||||
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
|
||||
|
||||
// TODO: IDF-5679 (Copy from esp32c3, need check)
|
||||
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
|
||||
#define SOC_COEX_HW_PTI (1)
|
||||
|
||||
// TODO: IDF-5680 (Copy from esp32c3, need check)
|
||||
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
|
||||
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
|
||||
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
|
||||
|
||||
// TODO: IDF-5679 (Copy from esp32c3, need check)
|
||||
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
|
||||
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
|
||||
|
||||
// TODO: IDF-5351 (Copy from esp32c3, need check)
|
||||
/*-------------------------- Power Management CAPS ----------------------------*/
|
||||
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
|
||||
|
||||
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
|
||||
|
||||
#define SOC_PM_SUPPORT_CPU_PD (1)
|
||||
|
||||
#define SOC_PM_SUPPORT_WIFI_PD (1)
|
||||
|
||||
#define SOC_PM_SUPPORT_BT_PD (1)
|
||||
|
||||
// TODO: IDF-5322 (Copy from esp32c3, need check)
|
||||
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
|
||||
#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
|
||||
#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
|
||||
|
||||
// TODO: IDF-5679 (Copy from esp32c3, need check)
|
||||
/*------------------------------------ WI-FI CAPS ------------------------------------*/
|
||||
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
|
||||
#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */
|
||||
#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
|
||||
#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
|
||||
#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
|
||||
#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
|
||||
16
components/soc/esp32c6/include/soc/soc_pins.h
Normal file
16
components/soc/esp32c6/include/soc/soc_pins.h
Normal file
@ -0,0 +1,16 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* Pin definition header file. The long term plan is to have a single soc_pins.h for all
|
||||
* peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
|
||||
* peripheral and include them here to avoid developing conflicts in those header files.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/gpio_pins.h"
|
||||
#include "soc/spi_pins.h"
|
||||
26
components/soc/esp32c6/include/soc/spi_pins.h
Normal file
26
components/soc/esp32c6/include/soc/spi_pins.h
Normal file
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_SPI_PINS_H_
|
||||
#define _SOC_SPI_PINS_H_
|
||||
|
||||
#define SPI_FUNC_NUM 0
|
||||
#define SPI_IOMUX_PIN_NUM_HD 12
|
||||
#define SPI_IOMUX_PIN_NUM_CS 14
|
||||
#define SPI_IOMUX_PIN_NUM_MOSI 16
|
||||
#define SPI_IOMUX_PIN_NUM_CLK 15
|
||||
#define SPI_IOMUX_PIN_NUM_MISO 17
|
||||
#define SPI_IOMUX_PIN_NUM_WP 13
|
||||
|
||||
#define SPI2_FUNC_NUM 2
|
||||
#define SPI2_IOMUX_PIN_NUM_MISO 2
|
||||
#define SPI2_IOMUX_PIN_NUM_HD 4
|
||||
#define SPI2_IOMUX_PIN_NUM_WP 5
|
||||
#define SPI2_IOMUX_PIN_NUM_CLK 6
|
||||
#define SPI2_IOMUX_PIN_NUM_MOSI 7
|
||||
#define SPI2_IOMUX_PIN_NUM_CS 10
|
||||
|
||||
#endif
|
||||
12
components/soc/esp32c6/include/soc/system_reg.h
Normal file
12
components/soc/esp32c6/include/soc/system_reg.h
Normal file
@ -0,0 +1,12 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/hp_system_reg.h"
|
||||
|
||||
// TODO: IDF-5720
|
||||
#include "intpri_reg.h"
|
||||
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
|
||||
#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
|
||||
21
components/soc/esp32c6/include/soc/uart_channel.h
Normal file
21
components/soc/esp32c6/include/soc/uart_channel.h
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3.
|
||||
|
||||
#ifndef _SOC_UART_CHANNEL_H
|
||||
#define _SOC_UART_CHANNEL_H
|
||||
|
||||
//UART channels
|
||||
#define UART_GPIO21_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 21
|
||||
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 20
|
||||
|
||||
#define UART_TXD_GPIO21_DIRECT_CHANNEL UART_GPIO21_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL
|
||||
|
||||
#endif
|
||||
36
components/soc/esp32c6/include/soc/uart_pins.h
Normal file
36
components/soc/esp32c6/include/soc/uart_pins.h
Normal file
@ -0,0 +1,36 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/io_mux_reg.h"
|
||||
|
||||
/* Specify the number of pins for UART */
|
||||
#define SOC_UART_PINS_COUNT (4)
|
||||
|
||||
/* Specify the GPIO pin number for each UART signal in the IOMUX */
|
||||
#define U0RXD_GPIO_NUM 17
|
||||
#define U0TXD_GPIO_NUM 16
|
||||
#define U0RTS_GPIO_NUM (-1)
|
||||
#define U0CTS_GPIO_NUM (-1)
|
||||
|
||||
#define U1RXD_GPIO_NUM (-1)
|
||||
#define U1TXD_GPIO_NUM (-1)
|
||||
#define U1RTS_GPIO_NUM (-1)
|
||||
#define U1CTS_GPIO_NUM (-1)
|
||||
|
||||
/* The following defines are necessary for reconfiguring the UART
|
||||
* to use IOMUX, at runtime. */
|
||||
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
|
||||
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
|
||||
/* No func for the following pins, they shall not be used */
|
||||
#define U0RTS_MUX_FUNC (-1)
|
||||
#define U0CTS_MUX_FUNC (-1)
|
||||
/* Same goes for UART1 */
|
||||
#define U1TXD_MUX_FUNC (-1)
|
||||
#define U1RXD_MUX_FUNC (-1)
|
||||
#define U1RTS_MUX_FUNC (-1)
|
||||
#define U1CTS_MUX_FUNC (-1)
|
||||
13
components/soc/esp32c6/include/soc/wdev_reg.h
Normal file
13
components/soc/esp32c6/include/soc/wdev_reg.h
Normal file
@ -0,0 +1,13 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
#include "soc/lpperi_reg.h"
|
||||
|
||||
/* Hardware random number generator register */
|
||||
#define WDEV_RND_REG LPPERI_RNG_DATA_REG
|
||||
17
components/soc/esp32c6/ledc_periph.c
Normal file
17
components/soc/esp32c6/ledc_periph.c
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/ledc_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for every LEDC peripheral: GPIO signals
|
||||
*/
|
||||
const ledc_signal_conn_t ledc_periph_signal[1] = {
|
||||
{
|
||||
.sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
|
||||
}
|
||||
};
|
||||
35
components/soc/esp32c6/rmt_periph.c
Normal file
35
components/soc/esp32c6/rmt_periph.c
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/rmt_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
const rmt_signal_conn_t rmt_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module = PERIPH_RMT_MODULE,
|
||||
.irq = ETS_RMT_INTR_SOURCE,
|
||||
.channels = {
|
||||
[0] = {
|
||||
.tx_sig = RMT_SIG_OUT0_IDX,
|
||||
.rx_sig = -1
|
||||
},
|
||||
[1] = {
|
||||
.tx_sig = RMT_SIG_OUT1_IDX,
|
||||
.rx_sig = -1
|
||||
},
|
||||
[2] = {
|
||||
.tx_sig = -1,
|
||||
.rx_sig = RMT_SIG_IN0_IDX
|
||||
},
|
||||
[3] = {
|
||||
.tx_sig = -1,
|
||||
.rx_sig = RMT_SIG_IN1_IDX
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
25
components/soc/esp32c6/sdm_periph.c
Normal file
25
components/soc/esp32c6/sdm_periph.c
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/sdm_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
|
||||
.channels = {
|
||||
[0] = {
|
||||
GPIO_SD0_OUT_IDX
|
||||
},
|
||||
[1] = {
|
||||
GPIO_SD1_OUT_IDX
|
||||
},
|
||||
[2] = {
|
||||
GPIO_SD2_OUT_IDX
|
||||
},
|
||||
[3] = {
|
||||
GPIO_SD3_OUT_IDX
|
||||
}
|
||||
}
|
||||
};
|
||||
53
components/soc/esp32c6/spi_periph.c
Normal file
53
components/soc/esp32c6/spi_periph.c
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/spi_periph.h"
|
||||
#include "stddef.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
|
||||
*/
|
||||
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
|
||||
{ // TODO: IDF-5333 Need check
|
||||
.spiclk_in = 0,/* SPI clock is not an input signal*/
|
||||
.spics_in = 0,/* SPI cs is not an input signal*/
|
||||
.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
|
||||
.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
|
||||
.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
|
||||
.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
|
||||
.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
|
||||
.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
|
||||
.irq = ETS_MSPI_INTR_SOURCE,
|
||||
.irq_dma = -1,
|
||||
.module = PERIPH_SPI_MODULE,
|
||||
.hw = (spi_dev_t *) &SPIMEM1,
|
||||
.func = SPI_FUNC_NUM,
|
||||
}, { // TODO: IDF-5334 Need check
|
||||
.spiclk_out = FSPICLK_OUT_IDX,
|
||||
.spiclk_in = FSPICLK_IN_IDX,
|
||||
.spid_out = FSPID_OUT_IDX,
|
||||
.spiq_out = FSPIQ_OUT_IDX,
|
||||
.spiwp_out = FSPIWP_OUT_IDX,
|
||||
.spihd_out = FSPIHD_OUT_IDX,
|
||||
.spid_in = FSPID_IN_IDX,
|
||||
.spiq_in = FSPIQ_IN_IDX,
|
||||
.spiwp_in = FSPIWP_IN_IDX,
|
||||
.spihd_in = FSPIHD_IN_IDX,
|
||||
.spics_out = {FSPICS0_OUT_IDX},
|
||||
.spics_in = FSPICS0_IN_IDX,
|
||||
.spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
|
||||
.spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
|
||||
.spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
|
||||
.spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
|
||||
.spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
|
||||
.spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
|
||||
.irq = ETS_GSPI2_INTR_SOURCE,
|
||||
.irq_dma = -1,
|
||||
.module = PERIPH_SPI2_MODULE,
|
||||
.hw = &GPSPI2,
|
||||
.func = SPI2_FUNC_NUM,
|
||||
}
|
||||
};
|
||||
16
components/soc/esp32c6/temperature_sensor_periph.c
Normal file
16
components/soc/esp32c6/temperature_sensor_periph.c
Normal file
@ -0,0 +1,16 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/temperature_sensor_periph.h"
|
||||
|
||||
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
|
||||
/*Offset reg_val min max error */
|
||||
{-2, 5, 50, 125, 3},
|
||||
{-1, 7, 20, 100, 2},
|
||||
{ 0, 15, -10, 80, 1},
|
||||
{ 1, 11, -30, 50, 2},
|
||||
{ 2, 10, -40, 20, 3},
|
||||
};
|
||||
24
components/soc/esp32c6/timer_periph.c
Normal file
24
components/soc/esp32c6/timer_periph.c
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/timer_periph.h"
|
||||
|
||||
const timer_group_signal_conn_t timer_group_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module = PERIPH_TIMG0_MODULE,
|
||||
.timer_irq_id = {
|
||||
[0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.module = PERIPH_TIMG1_MODULE,
|
||||
.timer_irq_id = {
|
||||
[0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
80
components/soc/esp32c6/uart_periph.c
Normal file
80
components/soc/esp32c6/uart_periph.c
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/uart_periph.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
|
||||
*/
|
||||
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
|
||||
{
|
||||
.pins = {
|
||||
[SOC_UART_TX_PIN_IDX] = {
|
||||
.default_gpio = U0TXD_GPIO_NUM,
|
||||
.iomux_func = U0TXD_MUX_FUNC,
|
||||
.input = 0,
|
||||
.signal = U0TXD_OUT_IDX,
|
||||
},
|
||||
|
||||
[SOC_UART_RX_PIN_IDX] = {
|
||||
.default_gpio = U0RXD_GPIO_NUM,
|
||||
.iomux_func = U0RXD_MUX_FUNC,
|
||||
.input = 1,
|
||||
.signal = U0RXD_IN_IDX,
|
||||
},
|
||||
|
||||
[SOC_UART_RTS_PIN_IDX] = {
|
||||
.default_gpio = U0RTS_GPIO_NUM,
|
||||
.iomux_func = U0RTS_MUX_FUNC,
|
||||
.input = 0,
|
||||
.signal = U0RTS_OUT_IDX,
|
||||
},
|
||||
|
||||
[SOC_UART_CTS_PIN_IDX] = {
|
||||
.default_gpio = U0CTS_GPIO_NUM,
|
||||
.iomux_func = U0CTS_MUX_FUNC,
|
||||
.input = 1,
|
||||
.signal = U0CTS_IN_IDX,
|
||||
}
|
||||
},
|
||||
.irq = ETS_UART0_INTR_SOURCE,
|
||||
.module = PERIPH_UART0_MODULE,
|
||||
},
|
||||
|
||||
{
|
||||
.pins = {
|
||||
[SOC_UART_TX_PIN_IDX] = {
|
||||
.default_gpio = U1TXD_GPIO_NUM,
|
||||
.iomux_func = U1TXD_MUX_FUNC,
|
||||
.input = 0,
|
||||
.signal = U1TXD_OUT_IDX,
|
||||
},
|
||||
|
||||
[SOC_UART_RX_PIN_IDX] = {
|
||||
.default_gpio = U1RXD_GPIO_NUM,
|
||||
.iomux_func = U1RXD_MUX_FUNC,
|
||||
.input = 1,
|
||||
.signal = U1RXD_IN_IDX,
|
||||
},
|
||||
|
||||
[SOC_UART_RTS_PIN_IDX] = {
|
||||
.default_gpio = U1RTS_GPIO_NUM,
|
||||
.iomux_func = U1RTS_MUX_FUNC,
|
||||
.input = 0,
|
||||
.signal = U1RTS_OUT_IDX,
|
||||
},
|
||||
|
||||
[SOC_UART_CTS_PIN_IDX] = {
|
||||
.default_gpio = U1CTS_GPIO_NUM,
|
||||
.iomux_func = U1CTS_MUX_FUNC,
|
||||
.input = 1,
|
||||
.signal = U1CTS_IN_IDX,
|
||||
},
|
||||
},
|
||||
.irq = ETS_UART1_INTR_SOURCE,
|
||||
.module = PERIPH_UART1_MODULE,
|
||||
},
|
||||
};
|
||||
Reference in New Issue
Block a user