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feat(sdio): supported sdio on esp32c5

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This commit is contained in:
armando
2025-04-23 15:47:09 +08:00
parent 8d02253b48
commit 69164ed912
14 changed files with 612 additions and 17 deletions
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10
components/esp_driver_sdio/src/sdio_slave.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -325,11 +325,11 @@ static inline esp_err_t sdio_slave_hw_init(sdio_slave_config_t *config)
static void recover_pin(int pin, int sdio_func)
{
uint32_t reg = GPIO_PIN_MUX_REG[pin];
assert(reg != UINT32_MAX);
gpio_io_config_t io_cfg = {};
esp_err_t ret = gpio_get_io_config(pin, &io_cfg);
assert(ret == ESP_OK);
int func = REG_GET_FIELD(reg, MCU_SEL);
if (func == sdio_func) {
if (io_cfg.fun_sel == sdio_func) {
gpio_set_direction(pin, GPIO_MODE_INPUT);
gpio_func_sel(pin, PIN_FUNC_GPIO);
}

4
components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C6 |
| ----------------- | ----- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 |
| ----------------- | ----- | -------- | -------- |
# SDIO Cross Chips Test Apps: SDIO Slave App

3
components/hal/esp32/include/hal/sdio_slave_ll.h
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@ -16,6 +16,8 @@
#pragma once
#include <sys/queue.h>
#include <stdbool.h>
#include "hal/sdio_slave_types.h"
#include "hal/misc.h"
#include "soc/sdio_slc_struct.h"
@ -23,7 +25,6 @@
#include "soc/sdio_slc_host_struct.h"
#include "soc/sdio_slc_host_reg.h"
#include "soc/sdio_hinf_struct.h"
#include "soc/lldesc.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus

538
components/hal/esp32c5/include/hal/sdio_slave_ll.h Normal file
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@ -0,0 +1,538 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for SDIO slave register operations
// It's strange but `tx_*` regs for host->slave transfers while `rx_*` regs for slave->host transfers
// To reduce ambiguity, we call (host->slave, tx) transfers receiving and (slave->host, rx) transfers receiving
#pragma once
#include <sys/queue.h>
#include <stdbool.h>
#include "hal/sdio_slave_types.h"
#include "hal/misc.h"
#include "soc/sdio_slc_struct.h"
#include "soc/sdio_slc_reg.h"
#include "soc/sdio_slc_host_struct.h"
#include "soc/sdio_slc_host_reg.h"
#include "soc/sdio_hinf_struct.h"
#include "soc/pcr_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Get address of the only SLC registers
#define sdio_slave_ll_get_slc(ID) (&SLC)
/// Get address of the only HOST registers
#define sdio_slave_ll_get_host(ID) (&HOST)
/// Get address of the only HINF registers
#define sdio_slave_ll_get_hinf(ID) (&HINF)
/*
* SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
*
* --------------------------------------------------------------
* | own | EoF | sub_sof | 1'b0 | length [13:0] | size [13:0] |
* --------------------------------------------------------------
* | buf_ptr [31:0] |
* --------------------------------------------------------------
* | next_desc_ptr [31:0] |
* --------------------------------------------------------------
*/
/* this bitfield is start from the LSB!!! */
typedef struct sdio_slave_ll_desc_s {
volatile uint32_t size : 14,
length: 14,
offset: 1, /* starting from bit28, h/w reserved 1bit, s/w use it as offset in buffer */
sosf : 1, /* start of sub-frame */
eof : 1, /* end of frame */
owner : 1; /* hw or sw */
volatile const uint8_t *buf; /* point to buffer data */
union {
volatile uint32_t empty;
STAILQ_ENTRY(sdio_slave_ll_desc_s) qe; /* pointing to the next desc */
};
} sdio_slave_ll_desc_t;
/// Mask of general purpose interrupts sending from the host.
typedef enum {
SDIO_SLAVE_LL_SLVINT_0 = BIT(0), ///< General purpose interrupt bit 0.
SDIO_SLAVE_LL_SLVINT_1 = BIT(1),
SDIO_SLAVE_LL_SLVINT_2 = BIT(2),
SDIO_SLAVE_LL_SLVINT_3 = BIT(3),
SDIO_SLAVE_LL_SLVINT_4 = BIT(4),
SDIO_SLAVE_LL_SLVINT_5 = BIT(5),
SDIO_SLAVE_LL_SLVINT_6 = BIT(6),
SDIO_SLAVE_LL_SLVINT_7 = BIT(7),
} sdio_slave_ll_slvint_t;
/**
* @brief Enable the bus clock for the SDIO slave module
*
* @param enable true to enable, false to disable
*/
static inline void sdio_slave_ll_enable_bus_clock(bool enable)
{
PCR.sdio_slave_conf.sdio_slave_clk_en = enable;
}
/**
* @brief Reset the SDIO slave module
*/
static inline void sdio_slave_ll_reset_register(void)
{
PCR.sdio_slave_conf.sdio_slave_rst_en = 1;
PCR.sdio_slave_conf.sdio_slave_rst_en = 0;
}
/**
* Initialize the hardware.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_init(slc_dev_t *slc)
{
slc->slc_slc0int_ena.val = 0;
slc->slc_conf0.slc0_rx_auto_wrback = 1;
slc->slc_conf0.slc0_token_auto_clr = 0;
slc->slc_conf0.slc0_rx_loop_test = 0;
slc->slc_conf0.slc0_tx_loop_test = 0;
slc->slc_conf1.slc0_rx_stitch_en = 0;
slc->slc_conf1.slc0_tx_stitch_en = 0;
slc->slc_conf1.slc0_len_auto_clr = 0;
slc->slc_rx_dscr_conf.slc0_token_no_replace = 1;
}
/**
* Set the timing for the communication
*
* @param host Address of the host registers
* @param timing Timing configuration to set
*/
static inline void sdio_slave_ll_set_timing(host_dev_t *host, sdio_slave_timing_t timing)
{
switch (timing) {
case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
host->conf.frc_sdio20 = 0x1f;
host->conf.frc_sdio11 = 0;
host->conf.frc_pos_samp = 0x1f;
host->conf.frc_neg_samp = 0;
break;
case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
host->conf.frc_sdio20 = 0x1f;
host->conf.frc_sdio11 = 0;
host->conf.frc_pos_samp = 0;
host->conf.frc_neg_samp = 0x1f;
break;
case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
host->conf.frc_sdio20 = 0;
host->conf.frc_sdio11 = 0x1f;
host->conf.frc_pos_samp = 0x1f;
host->conf.frc_neg_samp = 0;
break;
case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
host->conf.frc_sdio20 = 0;
host->conf.frc_sdio11 = 0x1f;
host->conf.frc_pos_samp = 0;
host->conf.frc_neg_samp = 0x1f;
break;
}
}
/**
* Set the CCCR, SDIO and Physical Layer version
*/
static inline void sdio_slave_ll_init_version(hinf_dev_t *hinf)
{
hinf->cfg_data1.sdio_ver = 0x232;
}
/**
* Set the HS supported bit to be read by the host.
*
* @param hinf Address of the hinf registers
* @param hs true if supported, otherwise false.
*/
static inline void sdio_slave_ll_enable_hs(hinf_dev_t *hinf, bool hs)
{
if (hs) {
hinf->cfg_data1.highspeed_enable = 1;
} else {
hinf->cfg_data1.highspeed_enable = 0;
}
}
/**
* Set the IO Ready bit to be read by the host.
*
* @param hinf Address of the hinf registers
* @param ready true if ready, otherwise false.
*/
static inline void sdio_slave_ll_set_ioready(hinf_dev_t *hinf, bool ready)
{
hinf->cfg_data1.sdio_ioready1 = (ready ? 1 : 0); //set IO ready to 1 to stop host from using
}
/*---------------------------------------------------------------------------
* Send
*--------------------------------------------------------------------------*/
/**
* Reset the sending DMA.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_send_reset(slc_dev_t *slc)
{
//reset to flush previous packets
slc->slc_conf0.slc0_rx_rst = 1;
slc->slc_conf0.slc0_rx_rst = 0;
}
/**
* Start the sending DMA with the given descriptor.
*
* @param slc Address of the SLC registers
* @param desc Descriptor to send
*/
static inline void sdio_slave_ll_send_start(slc_dev_t *slc, const sdio_slave_ll_desc_t *desc)
{
slc->slc_slc0rx_link_addr.slc0_rxlink_addr = (uint32_t)desc;
slc->slc_slc0rx_link.slc0_rxlink_start = 1;
}
/**
* Write the PKT_LEN register to be written by the host to a certain value.
*
* @param slc Address of the SLC registers
* @param len Length to write
*/
static inline void sdio_slave_ll_send_write_len(slc_dev_t *slc, uint32_t len)
{
slc->slc_slc0_len_conf.val = FIELD_TO_VALUE2(SDIO_SLC0_LEN_WDATA, len) | FIELD_TO_VALUE2(SDIO_SLC0_LEN_WR, 1);
}
/**
* Read the value of PKT_LEN register. The register may keep the same until read
* by the host.
*
* @param host Address of the host registers
* @return The value of PKT_LEN register.
*/
static inline uint32_t sdio_slave_ll_send_read_len(host_dev_t *host)
{
return host->pkt_len.hostslchost_slc0_len;
}
/**
* Enable the rx_done interrupt. (sending)
*
* @param slc Address of the SLC registers
* @param ena true if enable, otherwise false.
*/
static inline void sdio_slave_ll_send_part_done_intr_ena(slc_dev_t *slc, bool ena)
{
slc->slc_slc0int_ena.slc0_rx_done_int_ena = (ena ? 1 : 0);
}
/**
* Clear the rx_done interrupt. (sending)
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_send_part_done_clear(slc_dev_t *slc)
{
slc->slc_slc0int_clr.slc0_rx_done_int_clr = 1;
}
/**
* Check whether the hardware is ready for the SW to use rx_done to invoke
* the ISR.
*
* @param slc Address of the SLC registers
* @return true if ready, otherwise false.
*/
static inline bool sdio_slave_ll_send_invoker_ready(slc_dev_t *slc)
{
return slc->slc_slc0int_raw.slc0_rx_done_int_raw;
}
/**
* Stop the sending DMA.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_send_stop(slc_dev_t *slc)
{
slc->slc_slc0rx_link.slc0_rxlink_stop = 1;
}
/**
* Enable the sending interrupt (rx_eof).
*
* @param slc Address of the SLC registers
* @param ena true to enable, false to disable
*/
static inline void sdio_slave_ll_send_intr_ena(slc_dev_t *slc, bool ena)
{
slc->slc_slc0int_ena.slc0_rx_eof_int_ena = (ena ? 1 : 0);
}
/**
* Clear the sending interrupt (rx_eof).
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_send_intr_clr(slc_dev_t *slc)
{
slc->slc_slc0int_clr.slc0_rx_eof_int_clr = 1;
}
/**
* Check whether the sending is done.
*
* @param slc Address of the SLC registers
* @return true if done, otherwise false
*/
static inline bool sdio_slave_ll_send_done(slc_dev_t *slc)
{
return slc->slc_slc0int_st.slc0_rx_eof_int_st != 0;
}
/**
* Clear the host interrupt indicating the slave having packet to be read.
*
* @param host Address of the host registers
*/
static inline void sdio_slave_ll_send_hostint_clr(host_dev_t *host)
{
host->slc0host_int_clr.slc0_rx_new_packet_int_clr = 1;
}
/*---------------------------------------------------------------------------
* Receive
*--------------------------------------------------------------------------*/
/**
* Enable the receiving interrupt.
*
* @param slc Address of the SLC registers
* @param ena
*/
static inline void sdio_slave_ll_recv_intr_ena(slc_dev_t *slc, bool ena)
{
slc->slc_slc0int_ena.slc0_tx_done_int_ena = (ena ? 1 : 0);
}
/**
* Start receiving DMA with the given descriptor.
*
* @param slc Address of the SLC registers
* @param desc Descriptor of the receiving buffer.
*/
static inline void sdio_slave_ll_recv_start(slc_dev_t *slc, sdio_slave_ll_desc_t *desc)
{
slc->slc_slc0tx_link_addr.slc0_txlink_addr = (uint32_t)desc;
slc->slc_slc0tx_link.slc0_txlink_start = 1;
}
/**
* Increase the receiving buffer counter by 1.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_size_inc(slc_dev_t *slc)
{
// fields wdata and inc_more should be written by the same instruction.
slc->slc_slc0token1.val = FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WDATA, 1) | FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_INC_MORE, 1);
}
/**
* Reset the receiving buffer.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_size_reset(slc_dev_t *slc)
{
slc->slc_slc0token1.val = FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WDATA, 0) | FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WR, 1);
}
/**
* Check whether there is a receiving finished event.
*
* @param slc Address of the SLC registers
* @return
*/
static inline bool sdio_slave_ll_recv_done(slc_dev_t *slc)
{
return slc->slc_slc0int_raw.slc0_tx_done_int_raw != 0;
}
/**
* Clear the receiving finished interrupt.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_done_clear(slc_dev_t *slc)
{
slc->slc_slc0int_clr.slc0_tx_done_int_clr = 1;
}
/**
* Restart the DMA. Call after you modified the next pointer of the tail descriptor to the appended
* descriptor.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_restart(slc_dev_t *slc)
{
slc->slc_slc0tx_link.slc0_txlink_restart = 1;
}
/**
* Reset the receiving DMA.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_reset(slc_dev_t *slc)
{
slc->slc_conf0.slc0_tx_rst = 1;
slc->slc_conf0.slc0_tx_rst = 0;
}
/**
* Stop the receiving DMA.
*
* @param slc Address of the SLC registers
*/
static inline void sdio_slave_ll_recv_stop(slc_dev_t *slc)
{
slc->slc_slc0tx_link.slc0_txlink_stop = 1;
}
/*---------------------------------------------------------------------------
* Host
*--------------------------------------------------------------------------*/
/**
* Get the address of the shared general purpose register. Internal.
*
* @param host Address of the host registers
* @param pos Position of the register, 0-63 except 24-27.
* @return address of the register.
*/
static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t *host, int pos)
{
return (intptr_t) & (host->conf_w0) + pos + (pos > 23 ? 4 : 0) + (pos > 31 ? 12 : 0);
}
/**
* Get the value of the shared general purpose register.
*
* @param host Address of the host registers
* @param pos Position of the register, 0-63, except 24-27.
* @return value of the register.
*/
static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
{
return *(uint8_t *)sdio_slave_ll_host_get_w_reg(host, pos);
}
/**
* Set the value of the shared general purpose register.
*
* @param host Address of the host registers
* @param pos Position of the register, 0-63, except 24-27.
* @param reg Value to set.
*/
static inline void sdio_slave_ll_host_set_reg(host_dev_t *host, int pos, uint8_t reg)
{
uint32_t *addr = (uint32_t *)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
uint32_t shift = (pos % 4) * 8;
*addr &= ~(0xff << shift);
*addr |= ((uint32_t)reg << shift);
}
/**
* Get the interrupt enable bits for the host.
*
* @param host Address of the host registers
* @return Enabled interrupts
*/
static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t *host)
{
return (sdio_slave_hostint_t)host->slc0host_func1_int_ena.val;
}
/**
* Set the interrupt enable bits for the host.
*
* @param host Address of the host registers
* @param mask Mask of interrupts to enable
*/
static inline void sdio_slave_ll_host_set_intena(host_dev_t *host, const sdio_slave_hostint_t *mask)
{
host->slc0host_func1_int_ena.val = (*mask);
}
/**
* Clear the interrupt bits for the host.
* @param host Address of the host registers
* @param mask Mask of interrupts to clear.
*/
static inline void sdio_slave_ll_host_intr_clear(host_dev_t *host, const sdio_slave_hostint_t *mask)
{
host->slc0host_int_clr.val = (*mask);
}
/**
* Send general purpose interrupts to the host.
* @param slc Address of the SLC registers
* @param mask Mask of interrupts to seend to host
*/
static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_hostint_t *mask)
{
//use registers in SLC to trigger, rather than write HOST registers directly
//other interrupts than tohost interrupts are not supported yet
HAL_FORCE_MODIFY_U32_REG_FIELD(slc->slc_slcintvec_tohost, slc0_tohost_intvec, *mask);
}
/**
* Enable some of the slave interrupts (send from host)
*
* @param slc Address of the SLC registers
* @param mask Mask of interrupts to enable, all those set to 0 will be disabled.
*/
static inline void sdio_slave_ll_slvint_set_ena(slc_dev_t *slc, const sdio_slave_ll_slvint_t *mask)
{
//other interrupts are not enabled
slc->slc_slc0int_ena.val = (slc->slc_slc0int_ena.val & (~0xff)) | ((*mask) & 0xff);
}
/**
* Fetch the slave interrupts (send from host) and clear them.
*
* @param slc Address of the SLC registers
* @param out_slv_int Output of the slave interrupts fetched and cleared.
*/
static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_ll_slvint_t *out_slv_int)
{
sdio_slave_ll_slvint_t slv_int = (sdio_slave_ll_slvint_t)(slc->slc_slc0int_st.val & 0xff);
*out_slv_int = slv_int;
slc->slc_slc0int_clr.val = slv_int;
}
#ifdef __cplusplus
}
#endif

3
components/hal/esp32c6/include/hal/sdio_slave_ll.h
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@ -16,6 +16,8 @@
#pragma once
#include <sys/queue.h>
#include <stdbool.h>
#include "hal/sdio_slave_types.h"
#include "hal/misc.h"
#include "soc/sdio_slc_struct.h"
@ -23,7 +25,6 @@
#include "soc/sdio_slc_host_struct.h"
#include "soc/sdio_slc_host_reg.h"
#include "soc/sdio_hinf_struct.h"
#include "soc/lldesc.h"
#include "soc/pcr_struct.h"
#ifdef __cplusplus

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@ -223,6 +223,10 @@ config SOC_WDT_SUPPORTED
bool
default y
config SOC_SDIO_SLAVE_SUPPORTED
bool
default y
config SOC_SPI_FLASH_SUPPORTED
bool
default y

14
components/soc/esp32c5/include/soc/sdio_slave_pins.h Normal file
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@ -0,0 +1,14 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD 10
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK 9
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0 8
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1 7
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2 14
#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3 13
#define SDIO_SLAVE_SLOT0_FUNC 0

1
components/soc/esp32c5/include/soc/soc_caps.h
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@ -72,6 +72,7 @@
#define SOC_CLK_TREE_SUPPORTED 1
#define SOC_ASSIST_DEBUG_SUPPORTED 1
#define SOC_WDT_SUPPORTED 1
#define SOC_SDIO_SLAVE_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32C5] IDF-8715
#define SOC_ECDSA_SUPPORTED 1
#define SOC_RNG_SUPPORTED 1

20
components/soc/esp32c5/sdio_slave_periph.c Normal file
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@ -0,0 +1,20 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "soc/sdio_slave_periph.h"
#include "soc/sdio_slave_pins.h"
const sdio_slave_slot_info_t sdio_slave_slot_info[1] = {
{
.clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK,
.cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD,
.d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0,
.d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1,
.d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2,
.d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3,
.func = SDIO_SLAVE_SLOT0_FUNC,
},
};

2
docs/conf_common.py
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@ -285,7 +285,7 @@ ESP32C3_DOCS = ['hw-reference/esp32c3/**', 'api-guides/RF_calibration.rst', 'api
ESP32C2_DOCS = ['api-guides/RF_calibration.rst', 'api-guides/phy.rst']
ESP32C5_DOCS = ['api-guides/phy.rst']
ESP32C5_DOCS = ['api-guides/phy.rst', 'api-reference/peripherals/sd_pullup_requirements.rst']
ESP32C61_DOCS = ['api-guides/phy.rst']

17
examples/peripherals/sdio/host/main/Kconfig.projbuild
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@ -47,6 +47,13 @@ menu "Example Configuration"
If the example does not work, please try disabling the HS mode.
config EXAMPLE_SDIO_HOST_DELAY
int "SDIO Host Delay"
range 0 5
default 0
help
SDIO Host delay phase
config EXAMPLE_ADJUSTABLE_PIN
bool
default EXAMPLE_SDIO_OVER_SPI || SOC_SDMMC_USE_GPIO_MATRIX
@ -55,36 +62,42 @@ menu "Example Configuration"
int "CMD (MOSI) GPIO number"
depends on EXAMPLE_ADJUSTABLE_PIN
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 4 if IDF_TARGET_ESP32P4
default 15
config EXAMPLE_PIN_CLK
int "CLK GPIO number"
depends on EXAMPLE_ADJUSTABLE_PIN
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 33 if IDF_TARGET_ESP32P4
default 14
config EXAMPLE_PIN_D0
int "D0 (MISO) GPIO number"
depends on EXAMPLE_ADJUSTABLE_PIN
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 32 if IDF_TARGET_ESP32P4
default 2
config EXAMPLE_PIN_D1
int "D1 (INTR) GPIO number"
depends on EXAMPLE_ADJUSTABLE_PIN
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 23 if IDF_TARGET_ESP32P4
default 4
config EXAMPLE_PIN_D2
int "D2 GPIO number"
depends on EXAMPLE_ADJUSTABLE_PIN
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 53 if IDF_TARGET_ESP32P4
default 12
config EXAMPLE_PIN_D3
int "D3 (CS) GPIO number"
depends on EXAMPLE_ADJUSTABLE_PIN
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 5 if IDF_TARGET_ESP32P4
default 13
choice EXAMPLE_SLAVE
@ -100,11 +113,11 @@ menu "Example Configuration"
endchoice
config EXAMPLE_SLAVE_PWR_NEGTIVE_ACTIVE
bool "Slave power control pin is negtive active, otherwise postive active"
bool "Slave power control pin is negative active, otherwise positive active"
depends on !EXAMPLE_SLAVE_NONE
default n
help
Slave power control pin is negtive active, otherwise postive active
Slave power control pin is negative active, otherwise positive active
config EXAMPLE_NO_INTR_LINE
bool "The host is not connected to the interrupt line (DAT1) of slave"

7
examples/peripherals/sdio/host/main/app_main.c
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@ -78,12 +78,12 @@
- 0 is the register to hold tasks. Bits:
- 0: the slave should reset.
- 1: the slave should send interrupts.
- 2: the slave should write the shared registers acoording to the value in register 1.
- 2: the slave should write the shared registers according to the value in register 1.
- 1 is the register to hold test value.
- other registers will be written by the slave for testing.
- FIFO:
The receving FIFO is size of 256 bytes.
The receiving FIFO is size of 256 bytes.
When the host writes something to slave recv FIFO, the slave should return it as is to the sending FIFO.
The example works as following process:
@ -190,6 +190,7 @@ esp_err_t slave_init(essl_handle_t* handle)
ESP_LOGI(TAG, "Probe using SD 1-bit...");
config.flags = SDMMC_HOST_FLAG_1BIT;
#endif
config.input_delay_phase = CONFIG_EXAMPLE_SDIO_HOST_DELAY;
#ifdef CONFIG_EXAMPLE_SDIO_HIGHSPEED
config.max_freq_khz = SDMMC_FREQ_HIGHSPEED;
@ -440,7 +441,7 @@ void job_fifo(essl_handle_t handle)
/* CAUTION: This example shows that we can send random length of packet to the slave.
* However it takes time of two transactions if the length is not multiples of 4 bytes.
* e.g. sending 6 bytes is done by sending 4 + 2 bytes each transaction.
* Try to avoid unaligned packets if possible to get higher effeciency.
* Try to avoid unaligned packets if possible to get higher efficiency.
*/
for (int i = 0; i < sizeof(packet_len) / sizeof(int); i++) {
//Prepare data to send. The length can be random, but data should start at the 32-bit boundary.

2
examples/peripherals/sdio/host/sdkconfig.defaults.esp32p4 Normal file
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@ -0,0 +1,2 @@
## On P4-SDMMC + C5 SDIO test runner environment, hardware delay needs to be considered
CONFIG_EXAMPLE_SDIO_HOST_DELAY=2

4
examples/peripherals/sdio/slave/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32 | ESP32-C6 |
| ----------------- | ----- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 |
| ----------------- | ----- | -------- | -------- |
See README.md in the parent folder