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Merge branch 'feat/add_gpio_extension_for_esp32c5' into 'master'

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feat(gpio_extension): add gpio extension support for esp32c5

Closes IDF-8718 and IDF-8725

See merge request espressif/esp-idf!32058
This commit is contained in:
morris
2024-07-18 11:08:07 +08:00
parent 40034622b8 38b1fe9b11
commit 6b952f1043
26 changed files with 257 additions and 93 deletions
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21
components/esp_driver_gpio/src/dedic_gpio.c
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@@ -10,22 +10,21 @@
#include <string.h>
#include <sys/lock.h>
#include "sdkconfig.h"
#include "esp_compiler.h"
#include "esp_heap_caps.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_check.h"
#include "esp_cpu.h"
#include "soc/soc_caps.h"
#include "soc/gpio_periph.h"
#include "soc/io_mux_reg.h"
#include "hal/dedic_gpio_cpu_ll.h"
#include "hal/gpio_hal.h"
#include "esp_private/gpio.h"
#include "esp_private/periph_ctrl.h"
#include "esp_rom_gpio.h"
#include "freertos/FreeRTOS.h"
#include "driver/dedic_gpio.h"
#include "soc/dedic_gpio_periph.h"
#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
#include "soc/dedic_gpio_struct.h"
#endif
@@ -59,7 +58,7 @@ struct dedic_gpio_platform_t {
};
struct dedic_gpio_bundle_t {
uint32_t core_id; // CPU core ID, a GPIO bundle must be installed to a specific CPU core
int core_id; // CPU core ID, a GPIO bundle must be installed to a specific CPU core
uint32_t out_mask; // mask of output channels in the bank
uint32_t in_mask; // mask of input channels in the bank
uint32_t out_offset; // offset in the bank (seen from output channel)
@@ -104,7 +103,7 @@ err:
return ret;
}
static void dedic_gpio_break_platform(uint32_t core_id)
static void dedic_gpio_break_platform(int core_id)
{
if (s_platform[core_id]) {
// prevent breaking platform concurrently
@@ -151,7 +150,7 @@ static void dedic_gpio_default_isr(void *arg)
}
}
static esp_err_t dedic_gpio_install_interrupt(uint32_t core_id)
static esp_err_t dedic_gpio_install_interrupt(int core_id)
{
esp_err_t ret = ESP_OK;
if (!s_platform[core_id]->intr_hdl) {
@@ -172,7 +171,7 @@ err:
return ret;
}
static void dedic_gpio_uninstall_interrupt(uint32_t core_id)
static void dedic_gpio_uninstall_interrupt(int core_id)
{
if (s_platform[core_id]->intr_hdl) {
// prevent uninstall interrupt concurrently
@@ -187,7 +186,7 @@ static void dedic_gpio_uninstall_interrupt(uint32_t core_id)
}
}
static void dedic_gpio_set_interrupt(uint32_t core_id, uint32_t channel, dedic_gpio_intr_type_t type)
static void dedic_gpio_set_interrupt(int core_id, uint32_t channel, dedic_gpio_intr_type_t type)
{
dedic_gpio_ll_set_interrupt_type(s_platform[core_id]->dev, channel, type);
if (type != DEDIC_GPIO_INTR_NONE) {
@@ -269,13 +268,13 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
// route dedicated GPIO channel signals to GPIO matrix
if (config->flags.in_en) {
for (size_t i = 0; i < config->array_size; i++) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[config->gpio_array[i]], PIN_FUNC_GPIO);
gpio_func_sel(config->gpio_array[i], PIN_FUNC_GPIO);
esp_rom_gpio_connect_in_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].in_sig_per_channel[in_offset + i], config->flags.in_invert);
}
}
if (config->flags.out_en) {
for (size_t i = 0; i < config->array_size; i++) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[config->gpio_array[i]], PIN_FUNC_GPIO);
gpio_func_sel(config->gpio_array[i], PIN_FUNC_GPIO);
esp_rom_gpio_connect_out_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].out_sig_per_channel[out_offset + i], config->flags.out_invert, false);
}
#if !SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
@@ -314,7 +313,7 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle)
bool recycle_all = false;
ESP_GOTO_ON_FALSE(bundle, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
uint32_t core_id = esp_cpu_get_core_id();
int core_id = esp_cpu_get_core_id();
ESP_GOTO_ON_FALSE(core_id == bundle->core_id, ESP_FAIL, err, TAG, "del bundle on wrong CPU");
portENTER_CRITICAL(&s_platform[core_id]->spinlock);

4
components/esp_driver_gpio/test_apps/gpio_extensions/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

14
components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c
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@@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@@ -60,7 +61,7 @@ TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]")
typedef struct {
SemaphoreHandle_t sem;
const int gpios[TEST_GPIO_GROUP_SIZE];
int gpios[TEST_GPIO_GROUP_SIZE];
} test_dedic_task_context_t;
static void test_dedic_gpio_on_specific_core(void *args)
@@ -144,6 +145,7 @@ TEST_CASE("Dedicated_GPIO_run_on_multiple_CPU_cores", "[dedic_gpio]")
{
SemaphoreHandle_t sem = xSemaphoreCreateCounting(SOC_CPU_CORES_NUM, 0);
TaskHandle_t task_handle[SOC_CPU_CORES_NUM];
test_dedic_task_context_t isr_ctx[SOC_CPU_CORES_NUM];
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
#if CONFIG_IDF_TARGET_ESP32P4
@@ -151,11 +153,11 @@ TEST_CASE("Dedicated_GPIO_run_on_multiple_CPU_cores", "[dedic_gpio]")
#else
int start_gpio = i * TEST_GPIO_GROUP_SIZE;
#endif
test_dedic_task_context_t isr_ctx = {
.sem = sem,
.gpios = {start_gpio, start_gpio + 1, start_gpio + 2, start_gpio + 3}
};
xTaskCreatePinnedToCore(test_dedic_gpio_on_specific_core, "dedic_gpio_test_tsk", 4096, &isr_ctx, 1,
isr_ctx[i].sem = sem;
const int gpios[TEST_GPIO_GROUP_SIZE] = {start_gpio, start_gpio + 1, start_gpio + 2, start_gpio + 3};
memcpy(isr_ctx[i].gpios, gpios, sizeof(gpios));
xTaskCreatePinnedToCore(test_dedic_gpio_on_specific_core, "dedic_gpio_test_tsk", 4096, &isr_ctx[i], 1,
&task_handle[i], i);
}

2
components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c
View File

@@ -16,6 +16,8 @@
#if CONFIG_IDF_TARGET_ESP32P4
#define TEST_FILTER_GPIO 20
#elif CONFIG_IDF_TARGET_ESP32C5
#define TEST_FILTER_GPIO 0
#else
#define TEST_FILTER_GPIO 2
#endif

2
components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py
View File

@@ -11,6 +11,7 @@ CONFIGS = [
@pytest.mark.esp32c2
@pytest.mark.esp32c3
@pytest.mark.esp32c5
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.esp32s2
@@ -24,6 +25,7 @@ def test_gpio_filter(dut: IdfDut) -> None:
@pytest.mark.esp32c2
@pytest.mark.esp32c3
@pytest.mark.esp32c5
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.esp32s2

55
components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h Normal file
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@@ -0,0 +1,55 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "riscv/csr.h"
/*fast gpio*/
#define CSR_GPIO_OEN_USER 0x803
#define CSR_GPIO_IN_USER 0x804
#define CSR_GPIO_OUT_USER 0x805
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
{
RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask);
}
static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
{
RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
}
__attribute__((always_inline))
static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
{
uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
return value;
}
__attribute__((always_inline))
static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
{
uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
return value;
}
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
{
RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value));
}
#ifdef __cplusplus
}
#endif

66
components/hal/esp32c5/include/hal/gpio_glitch_filter_ll.h Normal file
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@@ -0,0 +1,66 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
#include <stdbool.h>
#include "hal/assert.h"
#include "soc/gpio_ext_struct.h"
#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable GPIO glitch filter
*
* @param hw Glitch filter register base address
* @param filter_idx Glitch filter index
* @param enable True to enable, false to disable
*/
static inline void gpio_ll_glitch_filter_enable(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, bool enable)
{
hw->glitch_filter_chn[filter_idx].filter_chn_en = enable;
}
/**
* @brief Set the input GPIO for the glitch filter
*
* @param hw Glitch filter register base address
* @param filter_idx Glitch filter index
* @param gpio_num GPIO number
*/
static inline void gpio_ll_glitch_filter_set_gpio(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t gpio_num)
{
hw->glitch_filter_chn[filter_idx].filter_chn_input_io_num = gpio_num;
}
/**
* @brief Set the coefficient of the glitch filter window
*
* @param hw Glitch filter register base address
* @param filter_idx Glitch filter index
* @param window_width Window width, in IOMUX clock ticks
* @param window_threshold Window threshold, in IOMUX clock ticks
*/
static inline void gpio_ll_glitch_filter_set_window_coeff(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t window_width, uint32_t window_thres)
{
HAL_ASSERT(window_thres <= window_width);
hw->glitch_filter_chn[filter_idx].filter_chn_window_width = window_width - 1;
hw->glitch_filter_chn[filter_idx].filter_chn_window_thres = window_thres - 1;
}
#ifdef __cplusplus
}
#endif

1
components/soc/esp32c2/dedic_gpio_periph.c
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@@ -8,7 +8,6 @@
#include "soc/dedic_gpio_periph.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.module = -1,
.irq = -1,
.cores = {
[0] = {

1
components/soc/esp32c3/dedic_gpio_periph.c
View File

@@ -8,7 +8,6 @@
#include "soc/dedic_gpio_periph.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.module = -1,
.irq = -1,
.cores = {
[0] = {

36
components/soc/esp32c5/dedic_gpio_periph.c Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_sig_map.h"
#include "soc/dedic_gpio_periph.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.irq = -1,
.cores = {
[0] = {
.in_sig_per_channel = {
[0] = CPU_GPIO_IN0_IDX,
[1] = CPU_GPIO_IN1_IDX,
[2] = CPU_GPIO_IN2_IDX,
[3] = CPU_GPIO_IN3_IDX,
[4] = CPU_GPIO_IN4_IDX,
[5] = CPU_GPIO_IN5_IDX,
[6] = CPU_GPIO_IN6_IDX,
[7] = CPU_GPIO_IN7_IDX,
},
.out_sig_per_channel = {
[0] = CPU_GPIO_OUT0_IDX,
[1] = CPU_GPIO_OUT1_IDX,
[2] = CPU_GPIO_OUT2_IDX,
[3] = CPU_GPIO_OUT3_IDX,
[4] = CPU_GPIO_OUT4_IDX,
[5] = CPU_GPIO_OUT5_IDX,
[6] = CPU_GPIO_OUT6_IDX,
[7] = CPU_GPIO_OUT7_IDX,
}
},
},
};

24
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -7,6 +7,10 @@ config SOC_ADC_SUPPORTED
bool
default y
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_UART_SUPPORTED
bool
default y
@@ -395,6 +399,14 @@ config SOC_GPIO_PIN_COUNT
int
default 29
config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
int
default 8
config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
@@ -463,6 +475,18 @@ config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 1

2
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@@ -402,7 +402,7 @@ typedef enum {
* @brief Glitch filter clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8718 (inherit from C6)
typedef enum {
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */

23
components/soc/esp32c5/include/soc/gpio_ext_struct.h
View File

@@ -142,13 +142,13 @@ typedef union {
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
/** filter_chn_en : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable channel n of Glitch Filter.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
uint32_t filter_chn_en:1;
/** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Configures to select the input GPIO for Glitch Filter. \\
* 0: Select GPIO0\\
* 1: Select GPIO1\\
@@ -157,20 +157,20 @@ typedef union {
* 28: Select GPIO28\\
* 29 ~ 63: Reserved\\
*/
uint32_t filter_ch0_input_io_num:6;
uint32_t filter_chn_input_io_num:6;
uint32_t reserved_7:1;
/** filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0;
/** filter_chn_window_thres : R/W; bitpos: [13:8]; default: 0;
* Configures the window threshold for Glitch Filter. The window threshold should be
* less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.\\ %see DOC-4768\\
* Measurement unit: IO MUX operating clock cycle\\
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0;
uint32_t filter_chn_window_thres:6;
/** filter_chn_window_width : R/W; bitpos: [19:14]; default: 0;
* Configures the window width for Glitch Filter. The effective value of window width
* is 0 ~ 63. \\
* Measurement unit: IO MUX operating clock cycle\\
*/
uint32_t filter_ch0_window_width:6;
uint32_t filter_chn_window_width:6;
uint32_t reserved_20:12;
};
uint32_t val;
@@ -454,13 +454,17 @@ typedef struct gpio_etm_dev_t {
volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[6];
} gpio_etm_dev_t;
typedef struct {
volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8];
} gpio_glitch_filter_dev_t;
typedef struct {
volatile gpio_sd_dev_t sigma_delta;
uint32_t reserved_018[16];
volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0;
volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0;
uint32_t reserved_060[30];
volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8];
volatile gpio_glitch_filter_dev_t glitch_filter;
uint32_t reserved_0f8[8];
volatile gpio_etm_dev_t etm;
uint32_t reserved_170[24];
@@ -474,6 +478,7 @@ typedef struct {
} gpio_ext_dev_t;
extern gpio_sd_dev_t SDM;
extern gpio_glitch_filter_dev_t GLITCH_FILTER;
extern gpio_etm_dev_t GPIO_ETM;
extern gpio_ext_dev_t GPIO_EXT;

14
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -18,7 +18,7 @@
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_ADC_SUPPORTED 1
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
@@ -188,9 +188,9 @@
// ESP32-C5 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 29
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// GPIO peripheral has the ETM extension
#define SOC_GPIO_SUPPORT_ETM 1
@@ -234,9 +234,9 @@
#define SOC_RTCIO_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
// #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C5 has 1 I2C

1
components/soc/esp32c5/ld/esp32c5.peripherals.ld
View File

@@ -44,6 +44,7 @@ PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091e00 );
PROVIDE ( SDM = 0x60091e00 );
PROVIDE ( GLITCH_FILTER = 0x60091ed8 );
PROVIDE ( GPIO_ETM = 0x60091f18 );
PROVIDE ( MEM_MONITOR = 0x60092000 );
PROVIDE ( PAU = 0x60093000 );

1
components/soc/esp32c6/dedic_gpio_periph.c
View File

@@ -8,7 +8,6 @@
#include "soc/dedic_gpio_periph.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.module = -1,
.irq = -1,
.cores = {
[0] = {

1
components/soc/esp32h2/dedic_gpio_periph.c
View File

@@ -8,7 +8,6 @@
#include "soc/dedic_gpio_periph.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.module = -1,
.irq = -1,
.cores = {
[0] = {

19
components/soc/esp32s2/dedic_gpio_periph.c
View File

@@ -1,22 +1,13 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/dedic_gpio_periph.h"
#include "soc/gpio_sig_map.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.module = PERIPH_DEDIC_GPIO_MODULE,
.irq = ETS_DEDICATED_GPIO_INTR_SOURCE,
.cores = {
[0] = {

19
components/soc/esp32s3/dedic_gpio_periph.c
View File

@@ -1,22 +1,13 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/dedic_gpio_periph.h"
#include "soc/gpio_sig_map.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.module = PERIPH_DEDIC_GPIO_MODULE,
.irq = -1,
.cores = {
[0] = {

19
components/soc/include/soc/dedic_gpio_periph.h
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@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -25,7 +17,6 @@ extern "C" {
#if SOC_DEDICATED_GPIO_SUPPORTED
typedef struct {
const periph_module_t module; // Peripheral module
const int irq; // Interrupt resource (-1 means no interrupt supported)
struct {
const int in_sig_per_channel[SOC_DEDIC_GPIO_IN_CHANNELS_NUM];

4
examples/peripherals/dedicated_gpio/soft_i2c/README.md
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# Example: Software I2C Master via Dedicated/Fast GPIOs

4
examples/peripherals/dedicated_gpio/soft_spi/README.md
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
# Example: SPI software emulation using dedicated/fast GPIOs

4
examples/peripherals/dedicated_gpio/soft_uart/README.md
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# Example: UART software emulation using dedicated/fast GPIOs

6
examples/peripherals/dedicated_gpio/soft_uart/components/soft_uart/riscv/soft_uart.S
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@@ -4,12 +4,18 @@
* SPDX-License-Identifier: CC0-1.0
*/
#include "sdkconfig.h"
#include "soc/soc_caps.h"
/* RISC-V fast GPIO special registers, taken from "hal/dedic_gpio_cpu_ll.h" */
#define CSR_GPIO_IN_USER 0x804
#define CSR_GPIO_OUT_USER 0x805
/* Special register for machine cycle count */
#if SOC_CPU_HAS_CSR_PC
#define CSR_PCCR_MACHINE 0x7e2
#else
#define CSR_PCCR_MACHINE mcycle
#endif
.section .text

4
examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/README.md
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C6 | ESP32-H2 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- | -------- |
# Parallel IO TX Example: Simple RGB LED Matrix

3
tools/ci/check_copyright_ignore.txt
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@@ -590,7 +590,6 @@ components/soc/esp32c3/include/soc/wdev_reg.h
components/soc/esp32c3/interrupts.c
components/soc/esp32c3/ledc_periph.c
components/soc/esp32s2/adc_periph.c
components/soc/esp32s2/dedic_gpio_periph.c
components/soc/esp32s2/i2c_periph.c
components/soc/esp32s2/include/soc/apb_saradc_reg.h
components/soc/esp32s2/include/soc/assist_debug_reg.h
@@ -626,7 +625,6 @@ components/soc/esp32s2/include/soc/usb_wrap_reg.h
components/soc/esp32s2/include/soc/usb_wrap_struct.h
components/soc/esp32s2/include/soc/wdev_reg.h
components/soc/esp32s2/ledc_periph.c
components/soc/esp32s3/dedic_gpio_periph.c
components/soc/esp32s3/i2c_periph.c
components/soc/esp32s3/include/soc/apb_saradc_reg.h
components/soc/esp32s3/include/soc/assist_debug_reg.h
@@ -684,7 +682,6 @@ components/soc/esp32s3/include/soc/usb_wrap_reg.h
components/soc/esp32s3/include/soc/usb_wrap_struct.h
components/soc/esp32s3/include/soc/wdev_reg.h
components/soc/esp32s3/ledc_periph.c
components/soc/include/soc/dedic_gpio_periph.h
components/soc/include/soc/gpio_periph.h
components/soc/include/soc/ledc_periph.h
components/soc/lldesc.c