fix(esp_hw_support): fix wrong APB clock freq on retenion

components/esp_hw_support/include/esp_private/rtc_clk.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,11 +22,24 @@ extern "C" {
  * source to XTAL (except for S2).
  *
  * Currently, this function is only called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
- * clock source back to XTAL (by default) before reset, and in `esp_sleep_start` to switch CPU clock source to XTAL
- * before entering sleep for PMU supported chips.
+ * clock source back to XTAL (by default) before reset.
  */
 void rtc_clk_cpu_set_to_default_config(void);
 
+/**
+ * @brief Switch CPU clock source to XTAL, the PLL has different processing methods for different chips.
+ *        1. For earlier chips without PMU, there is no PMU module that can turn off the CPU's PLL, so it has to be
+ *           disabled at here to save the power consumption. Though ESP32C3/S3 has USB CDC device, it can not function
+ *           properly during sleep due to the lack of APB clock (before C6, USJ relies on APB clock to work). Therefore,
+ *           we will always disable CPU's PLL (i.e. BBPLL).
+ *        2. For PMU supported chips, CPU's PLL power can be turned off by PMU, so no need to disable the PLL at here.
+ *           Leaving PLL on at this stage also helps USJ keep connection and retention operation (if they rely on this PLL).
+ *           For ESP32P4, if the APB frequency is configured as the hardware default value (10MHz), this will cause the
+ *           regdma backup/restore to not achieve optimal performance. The MEM/APB frequency divider needs to be configured
+ *           to 40MHz to speed up the retention speed.
+ */
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void);
+
 /**
  * @brief Notify that the BBPLL has a new in-use consumer
  *

components/esp_hw_support/port/esp32/rtc_clk.c

@@ -426,6 +426,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     rtc_clk_wait_for_slow_cycle();
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_freq_set_xtal();
+}
+
 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config)
 {
     uint32_t source_freq_mhz;

components/esp_hw_support/port/esp32c2/rtc_clk.c

@@ -296,6 +296,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_freq_set_xtal();
+}
+
 /**
  * Switch to use XTAL as the CPU clock source.
  * Must satisfy: cpu_freq = XTAL_FREQ / div.

components/esp_hw_support/port/esp32c3/rtc_clk.c

@@ -325,6 +325,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_freq_set_xtal();
+}
+
 /**
  * Switch to use XTAL as the CPU clock source.
  * Must satisfy: cpu_freq = XTAL_FREQ / div.

components/esp_hw_support/port/esp32c5/rtc_clk.c

@@ -386,6 +386,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_set_to_default_config();
+}
+
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
 {
     // TODO: IDF-8641 CPU_MAX_FREQ don't know what to do... pll_240 or pll_160...

components/esp_hw_support/port/esp32c6/rtc_clk.c

@@ -340,6 +340,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_set_to_default_config();
+}
+
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
 {
     rtc_clk_cpu_freq_to_pll_mhz(cpu_freq_mhz);

components/esp_hw_support/port/esp32c61/rtc_clk.c

@@ -329,6 +329,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_set_to_default_config();
+}
+
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
 {
     rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz);

components/esp_hw_support/port/esp32h2/rtc_clk.c

@@ -400,6 +400,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_set_to_default_config();
+}
+
 soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
 {
     uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();

components/esp_hw_support/port/esp32h21/rtc_clk.c

@@ -400,6 +400,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_set_to_default_config();
+}
+
 soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
 {
     uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();

components/esp_hw_support/port/esp32h4/rtc_clk.c

@@ -338,6 +338,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_set_to_default_config();
+}
+
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
 {
     rtc_clk_cpu_freq_to_pll_mhz(cpu_freq_mhz);

components/esp_hw_support/port/esp32p4/rtc_clk.c

@@ -438,6 +438,13 @@ void rtc_clk_cpu_set_to_default_config(void)
     int freq_mhz = (int)rtc_clk_xtal_freq_get();
 
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, true);
+}
+
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    int freq_mhz = (int)rtc_clk_xtal_freq_get();
+
+    rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, false);
     s_cur_cpll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 

components/esp_hw_support/port/esp32s2/rtc_clk.c

@@ -446,6 +446,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     rtc_clk_cpu_freq_to_xtal(CLK_LL_XTAL_FREQ_MHZ, 1);
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_freq_set_xtal();
+}
+
 /**
  * Switch to use XTAL as the CPU clock source.
  * Must satisfy: cpu_freq = XTAL_FREQ / div.

components/esp_hw_support/port/esp32s3/rtc_clk.c

@@ -387,6 +387,11 @@ void rtc_clk_cpu_set_to_default_config(void)
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
 }
 
+void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
+{
+    rtc_clk_cpu_freq_set_xtal();
+}
+
 /**
  * Switch to use XTAL as the CPU clock source.
  * Must satisfy: cpu_freq = XTAL_FREQ / div.

components/esp_hw_support/sleep_modes.c

@@ -847,16 +847,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, uint32_t clk_fl
     // Save current frequency and switch to XTAL
     rtc_cpu_freq_config_t cpu_freq_config;
     rtc_clk_cpu_freq_get_config(&cpu_freq_config);
-#if SOC_PMU_SUPPORTED
-    // For PMU supported chips, CPU's PLL power can be turned off by PMU, so no need to disable the PLL at here.
-    // Leaving PLL on at this stage also helps USJ keep connection and retention operation (if they rely on this PLL).
-    rtc_clk_cpu_set_to_default_config();
-#else
-    // For earlier chips, there is no PMU module that can turn off the CPU's PLL, so it has to be disabled at here to save the power consumption.
-    // Though ESP32C3/S3 has USB CDC device, it can not function properly during sleep due to the lack of APB clock (before C6, USJ relies on APB clock to work).
-    // Therefore, we will always disable CPU's PLL (i.e. BBPLL).
-    rtc_clk_cpu_freq_set_xtal();
-#endif
+    rtc_clk_cpu_freq_set_xtal_for_sleep();
 
 #if SOC_PM_SUPPORT_EXT0_WAKEUP
     // Configure pins for external wakeup