forked from espressif/esp-idf
bootloader, esp_system: increase static allocation space for esp32s3
The previously used splits between memory allocated for ROM code,
2nd stage bootloader and the app were somewhat safe and conservative.
This resulted in some space being unavailable for static allocation
in the app.
This commit increases the space available for static allocation to the
maximum possible amount.
1. Some of the ROM code static allocation is only used in UART/USB/SPI
download modes. This region ("shared buffers") has been placed at
the lower end of ROM memory area, to be reusable in flash boot
mode. The 2nd stage bootloader linker script is modified to "pack"
all sections exactly up to the end but with roughly 8K margin between
startup stacks.
2. Instead of calculating the sections placement and hardcoding the
addresses in the LD script again, rewrite it to calculate the
start address of each memory region automatically based on the
logic above.
3. Adjust the app memory layout (SRAM_IRAM_END) accordingly,
increasing the space available for static allocation.
Overall these changes increase the space available for static
allocation by about 78kB.
The downside of these changes is that the 2nd stage bootloader .data
segment is now directly adjacent to the startup stack on the PRO CPU.
Previously, there was effectively about 78kB of extra stack space for
the PRO CPU, before the stack would run into the data segment.
This commit is contained in:
Ivan Grokhotkov
committed by
Mahavir Jain
Mahavir Jain
parent
6c5fb29c2c
commit
6e6b9ec5a6
@@ -1,16 +1,51 @@
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
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* We put 2nd bootloader in the high address space (before ROM stack/data/bss).
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* See memory usage for ROM bootloader at the end of this file.
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*
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* ESP32-S3 ROM static data usage is as follows:
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* - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700).
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*/
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/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
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iram_dram_offset = 0x6f0000;
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/* We consider 0x3fce9700 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
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* and work out iram_seg and iram_loader_seg addresses from there, backwards.
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*/
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/* These lengths can be adjusted, if necessary: */
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bootloader_usable_dram_end = 0x3fce9700;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x4000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x3000;
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/* Start of the lower region is determined by region size and the end of the higher region */
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bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
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bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
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bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
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bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
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MEMORY
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{
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iram_seg (RWX) : org = 0x403B6000, len = 0x4000
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iram_loader_seg (RWX) : org = 0x403BA000, len = 0x6000
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dram_seg (RW) : org = 0x3FCD0000, len = 0x4000
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iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
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iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
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dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
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}
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/* The app may use RAM for static allocations up to the start of iram_loader_seg.
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* If you have changed something above and this assert fails:
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* 1. Check what the new value of bootloader_iram_loader_seg start is.
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* 2. Update the value in this assert.
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* 3. Update SRAM_IRAM_END in components/esp_system/ld/esp32s3/memory.ld.in to the same value.
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*/
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ASSERT(bootloader_iram_loader_seg_start == 0x403cc700, "bootloader_iram_loader_seg_start inconsistent with SRAM_IRAM_END");
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/* Default entry point: */
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ENTRY(call_start_cpu0);
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@@ -172,28 +207,3 @@ SECTIONS
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} > iram_seg
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}
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/**
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* Appendix: Memory Usage of ROM bootloader
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*
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* +--------+--------------+------+ 0x3FCD_8000
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* | ^ |
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* | | |
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* | | data/bss |
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* | | |
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* | v |
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* +------------------------------+ 0x3FCE_9910
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* | ^ |
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* | | |
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* | | stack (pro) |
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* | | |
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* | v |
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* +------------------------------+ 0x3FCE_B910
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* | ^ |
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* | | |
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* | | stack (app) |
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* | | |
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* | v |
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* +--------+--------------+------+ 0x3FCE_D910
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*/
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@@ -36,7 +36,7 @@
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#define SRAM_IRAM_START 0x40370000
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#define SRAM_DIRAM_I_START 0x40378000
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#define SRAM_IRAM_END 0x403BA000
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#define SRAM_IRAM_END 0x403CC700 /* Please refer to ESP32-S3 bootloader.ld for more information on this */
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#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
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#define SRAM_DRAM_START 0x3FC88000
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