set fosc div to 1 to make chip run stablly for C2

2022-08-17 10:58:14 +08:00
parent 6d1f1eccfb
commit 7243032123
1 changed files with 1 additions and 1 deletions
--- a/components/soc/esp32c2/include/soc/rtc.h
+++ b/components/soc/esp32c2/include/soc/rtc.h
@@ -179,7 +179,7 @@ typedef struct {
    .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
    .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
    .clk_rtc_clk_div = 0, \
-    .clk_8m_clk_div = 0, \
+    .clk_8m_clk_div = 1, \
    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
 }